wip
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28b8ac4b62
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4 changed files with 20 additions and 130 deletions
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@ -7,21 +7,18 @@
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#[cfg_attr(adc_v4, path = "v4.rs")]
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mod _version;
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#[cfg(not(any(adc_f1, adc_v1)))]
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#[cfg(not(adc_f1))]
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mod resolution;
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#[cfg(not(adc_v1))]
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mod sample_time;
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#[allow(unused)]
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pub use _version::*;
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#[cfg(not(any(adc_f1, adc_v1)))]
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#[cfg(not(adc_f1))]
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pub use resolution::Resolution;
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#[cfg(not(adc_v1))]
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pub use sample_time::SampleTime;
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use crate::peripherals;
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#[cfg(not(adc_v1))]
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pub struct Adc<'d, T: Instance> {
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#[allow(unused)]
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adc: crate::PeripheralRef<'d, T>,
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@ -44,9 +41,9 @@ pub(crate) mod sealed {
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}
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}
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#[cfg(not(any(adc_f1, adc_v2, adc_v4)))]
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#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4)))]
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pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
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#[cfg(any(adc_f1, adc_v2, adc_v4))]
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#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4))]
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pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
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pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}
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@ -1,4 +1,4 @@
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#[cfg(any(adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub enum Resolution {
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TwelveBit,
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@ -19,7 +19,7 @@ pub enum Resolution {
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impl Default for Resolution {
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fn default() -> Self {
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#[cfg(any(adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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{
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Self::TwelveBit
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}
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@ -40,7 +40,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
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Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
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Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
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Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
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#[cfg(any(adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
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}
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}
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@ -56,7 +56,7 @@ impl Resolution {
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Resolution::TwelveBit => (1 << 12) - 1,
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Resolution::TenBit => (1 << 10) - 1,
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Resolution::EightBit => (1 << 8) - 1,
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#[cfg(any(adc_v2, adc_v3, adc_g0))]
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#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
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Resolution::SixBit => (1 << 6) - 1,
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}
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}
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@ -25,7 +25,7 @@ macro_rules! impl_sample_time {
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};
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}
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#[cfg(adc_f1)]
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#[cfg(any(adc_f1, adc_v1))]
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impl_sample_time!(
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"1.5",
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Cycles1_5,
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@ -1,10 +1,8 @@
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use core::marker::PhantomData;
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use embassy_hal_common::into_ref;
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use embedded_hal_02::blocking::delay::DelayUs;
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use crate::adc::{AdcPin, Instance};
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use crate::{pac, Peripheral};
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use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
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use crate::Peripheral;
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pub const VDDA_CALIB_MV: u32 = 3300;
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pub const VREF_INT: u32 = 1230;
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@ -15,39 +13,6 @@ fn enable() {
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});
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}
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pub enum Resolution {
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TwelveBit,
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TenBit,
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EightBit,
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SixBit,
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}
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impl Default for Resolution {
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fn default() -> Self {
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Self::TwelveBit
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}
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}
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impl Resolution {
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fn res(&self) -> pac::adc::vals::Res {
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match self {
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Resolution::TwelveBit => pac::adc::vals::Res::TWELVEBIT,
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Resolution::TenBit => pac::adc::vals::Res::TENBIT,
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Resolution::EightBit => pac::adc::vals::Res::EIGHTBIT,
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Resolution::SixBit => pac::adc::vals::Res::SIXBIT,
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}
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}
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pub fn to_max_count(&self) -> u32 {
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match self {
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Resolution::TwelveBit => (1 << 12) - 1,
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Resolution::TenBit => (1 << 10) - 1,
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Resolution::EightBit => (1 << 8) - 1,
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Resolution::SixBit => (1 << 6) - 1,
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}
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}
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}
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pub trait InternalChannel<T>: sealed::InternalChannel<T> {}
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mod sealed {
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@ -80,68 +45,9 @@ impl<T: Instance> sealed::InternalChannel<T> for Temperature {
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}
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}
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mod sample_time {
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#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
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pub enum SampleTime {
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/// 1.5 ADC clock cycles
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Cycles1_5 = 0b000,
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/// 7.5 ADC clock cycles
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Cycles7_5 = 0b001,
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/// 13.5 ADC clock cycles
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Cycles13_5 = 0b010,
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/// 28.5 ADC clock cycles
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Cycles28_5 = 0b011,
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/// 41.5 ADC clock cycles
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Cycles41_5 = 0b100,
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/// 55.5 ADC clock cycles
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Cycles55_5 = 0b101,
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/// 71.5 ADC clock cycles
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Cycles71_5 = 0b110,
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/// 239.5 ADC clock cycles
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Cycles239_5 = 0b111,
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}
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impl SampleTime {
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pub(crate) fn sample_time(&self) -> crate::pac::adc::vals::Smp {
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match self {
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SampleTime::Cycles1_5 => crate::pac::adc::vals::Smp::CYCLES1_5,
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SampleTime::Cycles7_5 => crate::pac::adc::vals::Smp::CYCLES7_5,
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SampleTime::Cycles13_5 => crate::pac::adc::vals::Smp::CYCLES13_5,
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SampleTime::Cycles28_5 => crate::pac::adc::vals::Smp::CYCLES28_5,
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SampleTime::Cycles41_5 => crate::pac::adc::vals::Smp::CYCLES41_5,
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SampleTime::Cycles55_5 => crate::pac::adc::vals::Smp::CYCLES55_5,
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SampleTime::Cycles71_5 => crate::pac::adc::vals::Smp::CYCLES71_5,
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SampleTime::Cycles239_5 => crate::pac::adc::vals::Smp::CYCLES239_5,
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}
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}
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}
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impl Default for SampleTime {
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fn default() -> Self {
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Self::Cycles1_5
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}
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}
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}
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pub use sample_time::SampleTime;
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pub struct Adc<'d, T: Instance> {
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sample_time: SampleTime,
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vref_mv: u32,
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resolution: Resolution,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(_peri: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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into_ref!(_peri);
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pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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into_ref!(adc);
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enable();
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// Delay 1μs when using HSI14 as the ADC clock.
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delay.delay_us(1);
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let s = Self {
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adc,
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sample_time: Default::default(),
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vref_mv: VDDA_CALIB_MV,
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resolution: Resolution::default(),
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phantom: PhantomData,
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};
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s.calibrate();
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s
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@ -215,16 +119,10 @@ impl<'d, T: Instance> Adc<'d, T> {
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self.sample_time = sample_time;
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}
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pub fn set_vref_mv(&mut self, vref_mv: u32) {
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self.vref_mv = vref_mv;
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}
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pub fn set_resolution(&mut self, resolution: Resolution) {
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self.resolution = resolution;
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}
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pub fn to_millivolts(&self, sample: u16) -> u16 {
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((u32::from(sample) * self.vref_mv) / self.resolution.to_max_count()) as u16
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unsafe {
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T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
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}
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}
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pub fn read<P>(&mut self, pin: &mut P) -> u16
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@ -240,9 +138,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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pub fn read_internal(&mut self, channel: &mut impl InternalChannel<T>) -> u16 {
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let channel = channel.channel();
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unsafe {
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self.read_channel(channel)
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}
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unsafe { self.read_channel(channel) }
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}
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unsafe fn read_channel(&mut self, channel: u8) -> u16 {
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@ -258,17 +154,14 @@ impl<'d, T: Instance> Adc<'d, T> {
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T::regs().cr().modify(|reg| reg.set_aden(true));
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}
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T::regs().cfgr1().modify(|reg| reg.set_res(self.resolution.res()));
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T::regs().isr().modify(|reg| {
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reg.set_eoc(true);
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reg.set_eosmp(true);
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});
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// A.7.5 Single conversion sequence code example - Software trigger
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T::regs()
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.chselr()
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.write(|reg| reg.set_chselx(channel as usize, true));
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T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.sample_time()));
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T::regs().chselr().write(|reg| reg.set_chselx(channel as usize, true));
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T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
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T::regs().cr().modify(|reg| reg.set_adstart(true));
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while !T::regs().isr().read().eoc() {
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// spin
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