implement mwe of a DMA write() method for DAC
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ec36225f8a
commit
f5d084552d
2 changed files with 71 additions and 7 deletions
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@ -699,6 +699,8 @@ fn main() {
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// SDMMCv1 uses the same channel for both directions, so just implement for RX
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(("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
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(("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
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(("dac", "CH1"), quote!(crate::dac::Dma)),
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(("dac", "CH2"), quote!(crate::dac::Dma)),
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]
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.into();
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@ -2,6 +2,7 @@
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::{slice_ptr_parts, word, Transfer};
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use crate::pac::dac;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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@ -97,39 +98,58 @@ pub enum Value {
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Bit12(u16, Alignment),
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}
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pub struct Dac<'d, T: Instance> {
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pub struct Dac<'d, T: Instance, Tx> {
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channels: u8,
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txdma: PeripheralRef<'d, Tx>,
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_peri: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> Dac<'d, T> {
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pub fn new_1ch(peri: impl Peripheral<P = T> + 'd, _ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd) -> Self {
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impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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pub fn new_1ch(
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peri: impl Peripheral<P = T> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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) -> Self {
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into_ref!(peri);
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Self::new_inner(peri, 1)
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Self::new_inner(peri, 1, txdma)
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}
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pub fn new_2ch(
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peri: impl Peripheral<P = T> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
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) -> Self {
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into_ref!(peri);
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Self::new_inner(peri, 2)
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Self::new_inner(peri, 2, txdma)
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}
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fn new_inner(peri: PeripheralRef<'d, T>, channels: u8) -> Self {
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fn new_inner(peri: PeripheralRef<'d, T>, channels: u8, txdma: impl Peripheral<P = Tx> + 'd) -> Self {
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into_ref!(txdma);
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T::enable();
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T::reset();
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unsafe {
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T::regs().mcr().modify(|reg| {
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for ch in 0..channels {
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reg.set_mode(ch as usize, 0);
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reg.set_mode(ch as usize, 0);
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}
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});
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T::regs().cr().modify(|reg| {
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for ch in 0..channels {
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reg.set_en(ch as usize, true);
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reg.set_ten(ch as usize, true);
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}
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});
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}
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Self { channels, _peri: peri }
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Self {
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channels,
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txdma,
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_peri: peri,
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}
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}
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/// Check the channel is configured
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@ -215,6 +235,47 @@ impl<'d, T: Instance> Dac<'d, T> {
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}
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Ok(())
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}
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/// TODO: Allow an array of Value instead of only u16, right-aligned
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pub async fn write(&mut self, data: &[u16]) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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// TODO: Make this a parameter or get it from the struct or so...
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const CHANNEL: usize = 0;
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//debug!("Starting DAC");
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unsafe {
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T::regs().cr().modify(|w| {
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w.set_en(CHANNEL, true);
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w.set_dmaen(CHANNEL, true);
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});
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}
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let tx_request = self.txdma.request();
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// Use the 12 bit right-aligned register for now. TODO: distinguish values
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let tx_dst = T::regs().dhr12r(CHANNEL).ptr() as *mut u16;
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let tx_f = unsafe { Transfer::new_write(&mut self.txdma, tx_request, data, tx_dst, Default::default()) };
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//debug!("Awaiting tx_f");
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tx_f.await;
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// finish dma
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unsafe {
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// TODO: Do we need to check any status registers here?
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T::regs().cr().modify(|w| {
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// Disable the dac peripheral
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//w.set_en(CHANNEL, false);
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// Disable the DMA. TODO: Is this necessary?
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//w.set_dmaen(CHANNEL, false);
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});
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}
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Ok(())
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}
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}
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pub(crate) mod sealed {
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@ -224,6 +285,7 @@ pub(crate) mod sealed {
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}
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pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
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dma_trait!(Dma, Instance);
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pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
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