feat: Add spi support for STM32F1 variants
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3 changed files with 18 additions and 3 deletions
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@ -1,6 +1,7 @@
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#![macro_use]
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#![macro_use]
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#[cfg_attr(spi_v1, path = "v1.rs")]
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#[cfg_attr(spi_v1, path = "v1.rs")]
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#[cfg_attr(spi_f1, path = "v1.rs")]
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#[cfg_attr(spi_v2, path = "v2.rs")]
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#[cfg_attr(spi_v2, path = "v2.rs")]
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#[cfg_attr(spi_v3, path = "v3.rs")]
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#[cfg_attr(spi_v3, path = "v3.rs")]
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mod _version;
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mod _version;
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@ -414,7 +414,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(
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let sr = unsafe { regs.sr().read() };
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let sr = unsafe { regs.sr().read() };
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if sr.ovr() {
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if sr.ovr() {
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return Err(Error::Overrun);
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return Err(Error::Overrun);
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} else if sr.fre() {
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} else if sr_fre(sr) {
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return Err(Error::Framing);
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return Err(Error::Framing);
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} else if sr.modf() {
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} else if sr.modf() {
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return Err(Error::ModeFault);
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return Err(Error::ModeFault);
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@ -438,7 +438,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
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return Err(Error::Overrun);
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return Err(Error::Overrun);
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} else if sr.modf() {
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} else if sr.modf() {
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return Err(Error::ModeFault);
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return Err(Error::ModeFault);
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} else if sr.fre() {
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} else if sr_fre(sr) {
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return Err(Error::Framing);
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return Err(Error::Framing);
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} else if sr.crcerr() {
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} else if sr.crcerr() {
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return Err(Error::Crc);
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return Err(Error::Crc);
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@ -450,3 +450,17 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
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}
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}
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}
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}
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}
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}
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// SPI on F1 is just V1 without FRE and FRF fields
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// This driver only uses FRE, so add a simple function here to read fre on v1,
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// and return false on f1
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#[cfg(spi_v1)]
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fn sr_fre(sr: crate::pac::spi::regs::Sr) -> bool {
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sr.fre()
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}
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#[cfg(spi_f1)]
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fn sr_fre(_sr: crate::pac::spi::regs::Sr) -> bool {
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false
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}
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@ -1 +1 @@
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Subproject commit e78ea6f05058dc1eff1dd4a4f07227d502a3b657
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Subproject commit bae2d34445f87e7b9a88b683c789c5d0c7560fb6
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