rp/spi: start rx dma first.
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d36feb6405
commit
fa7510968a
1 changed files with 19 additions and 13 deletions
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@ -360,18 +360,22 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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reg.set_txdmae(true);
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})
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write_repeated(tx_ch, self.inner.regs().dr().ptr() as *mut u8, buffer.len(), T::TX_DREQ)
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};
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, buffer, T::RX_DREQ)
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write_repeated(tx_ch, self.inner.regs().dr().ptr() as *mut u8, buffer.len(), T::TX_DREQ)
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};
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join(tx_transfer, rx_transfer).await;
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Ok(())
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}
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@ -395,6 +399,15 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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})
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};
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
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};
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let mut tx_ch = self.tx_dma.as_mut().unwrap();
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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@ -411,13 +424,6 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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}
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}
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};
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
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};
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join(tx_transfer, rx_transfer).await;
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// if tx > rx we should clear any overflow of the FIFO SPI buffer
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