bors[bot]
f0a071790d
Merge #673
...
673: Inline GPIO functions r=Dirbaio a=nviennot
All GPIO functions are monomorphized (per pin). Inlining these make the ROM smaller when using opt-level="z"
Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-19 20:34:07 +00:00
Nicolas Viennot
4aba87f983
Inline GPIO functions
...
All GPIO functions are monomorphized (per pin). Inlining these make the
ROM smaller when using opt-level="z"
2022-03-19 14:06:11 -04:00
chemicstry
bdeb537ffa
Fix compile for stm32wb
2022-03-18 01:33:39 +02:00
chemicstry
b30a42aff8
Fix RCC safety and add reset to DAC
2022-03-18 01:16:07 +02:00
chemicstry
ca88ace98d
Reset peripherals on enable
2022-03-18 00:46:46 +02:00
chemicstry
d26b751edc
Add comments
2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea
Make UART futures Send
2022-03-17 18:23:47 +02:00
chemicstry
c24d482d51
Fix DMA channels
2022-03-17 01:54:56 +02:00
chemicstry
24a9e19062
More cleanup
2022-03-17 01:12:29 +02:00
chemicstry
9d71acc49e
Cleanup
2022-03-16 23:55:07 +02:00
chemicstry
224071f08e
Add F7 example
2022-03-16 23:44:02 +02:00
chemicstry
ea467e0acb
Rename DMA trait
2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73
Fix SDMMC v2 and add H7 example
2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d
Fix BDMA
2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06
Use RCC frequency instead of config
2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143
SDIO working on stm32f4
2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c
Add more options to DMA
2022-03-16 18:52:06 +02:00
chemicstry
2d224cf6a0
Update
2022-03-15 19:58:19 +02:00
Ulf Lilleengen
e09bde9345
Add support for splitting stm32 usart into TX and RX
...
* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
parts
* Implements e-h traits for TX and RX types
* Add stm32h7 example
2022-03-15 10:35:37 +01:00
Dario Nieuwenhuis
1dc618f0e4
stm32/spi: fix blocking transfer hanging after async.
2022-03-15 04:13:33 +01:00
Grant Miller
49ef19c0b2
stm32/spi: Clear rx fifo in blocking methods
2022-03-14 21:55:37 -05:00
Dario Nieuwenhuis
059b164234
stm32/spi: do not clear rxfifo in SPIv3, the hw already does it.
2022-03-15 02:37:08 +01:00
Dario Nieuwenhuis
4579192832
stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma.
2022-03-15 02:36:34 +01:00
Dario Nieuwenhuis
306110f56e
stm32/spi: implement async trasnfer_in_place
2022-03-15 00:40:48 +01:00
Grant Miller
f1d6c95205
rustfmt
2022-03-14 18:22:41 -05:00
Grant Miller
71632648c7
Fix zero-length-slice bugs
2022-03-14 18:14:55 -05:00
Grant Miller
15c533fe2a
Fix async write
bug
2022-03-14 18:04:31 -05:00
Grant Miller
6e00c58854
Make all functions generic over word size
2022-03-14 16:53:50 -05:00
Grant Miller
f0b62bc8e0
Use const REGS
2022-03-14 15:56:08 -05:00
Grant Miller
482ffea4dd
Finish unification
2022-03-14 15:56:08 -05:00
Grant Miller
406b1b3dd2
Finish matching versions
2022-03-14 15:56:08 -05:00
Grant Miller
7cd6f00a90
Add set_txdmaen
and set_rxdmaen
functions
2022-03-14 15:56:08 -05:00
Grant Miller
444b37fcdf
Add flush_rx_fifo
function
2022-03-14 15:56:08 -05:00
Grant Miller
683c11f399
Call set_word_size
before disabling SPE
2022-03-14 15:56:08 -05:00
Dario Nieuwenhuis
9bad9365dc
Update rust nightly, embedded-hal 1.0, embedded-hal-async.
2022-03-11 00:38:07 +01:00
Dario Nieuwenhuis
77841a4676
stm32/dma: panic on DMA error.
2022-03-09 03:19:05 +01:00
Grant Miller
8f7bb570ae
Ignore BDMA1 in H7
2022-03-08 16:46:42 -06:00
Grant Miller
8c45c98e41
stm32: Refactor DMA interrupts
...
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.
Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
2022-03-08 14:18:31 -06:00
Timo Kröger
372b71890d
[can] Typo fix: l7 -> f7
2022-03-05 09:46:06 +01:00
Timo Kröger
d6d25e6470
[can] cfgs
for naming inconsistencies
...
Approach is similar to USB OTG.
STM32L49x and STML4Ax have CAN1 and CAN2.
All others STM32L4xx do only have CAN1.
STM32F72x and STM32F73x are the only F7 devices with only CAN1.
2022-03-05 09:46:06 +01:00
Timo Kröger
6929350552
[can] Update macrotable comment
...
The chip description are corrected in:
https://github.com/embassy-rs/stm32-data/pull/123
2022-03-05 09:46:06 +01:00
Timo Kröger
4c30543938
[can] Do not use wildcard reexport for bxcan
2022-03-05 09:46:06 +01:00
bors[bot]
9ebf7eee6d
Merge #652 #653
...
652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff
This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.
I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.
653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio
Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-04 17:07:04 +00:00
Dario Nieuwenhuis
609975f821
rustfmt
2022-03-04 18:04:12 +01:00
Matthew W. Samsonoff
047ff9a2f2
Use new stm32-data registers and fix AHB clock calculation
...
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
2022-03-04 18:03:55 +01:00
Dario Nieuwenhuis
265cd1115b
stm32: allow unused macrotables.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
44096358a2
docs: add metadata.embassy_docs to cargo tomls.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
53d9a0b516
stm32: exclude spammy files from docs by prefixing with _
.
...
These files end up containing chip-specific info, so they deduplicate
really badly when building docs for all 1200 chips.
The doc generator removes files starting with `_`.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
94b232cf88
docs: prevent inline doc spam for reexports.
2022-03-04 18:03:41 +01:00
Matous Hybl
0172ca5b81
stm32: Add support for using TIM12 and TIM15 as time driver
2022-02-28 19:20:22 +01:00
Matous Hybl
a88c5e716e
stm32: Register access for timers now doesn't require self
2022-02-28 16:20:42 +01:00
Dario Nieuwenhuis
dd828a7a92
stm32: move macrotables to embassy-stm32 build.rs
2022-02-26 03:23:09 +01:00
Dario Nieuwenhuis
e6299549a0
stm32/i2c: use one static per instance instead of an array.
2022-02-26 01:23:17 +01:00
Dario Nieuwenhuis
8d46d31824
stm32/dbgmcu: do not use macrotable.
2022-02-26 01:20:42 +01:00
Timo Kröger
48f700b35c
stm32 usart: Fix RX interrupt flag handling
...
* On v1 interrupts cannot be cleared individually.
Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
Handle them all in one go intstead of re-entering the ISR for each one so that
we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
from the buffer before receiving the next byte.
2022-02-25 14:32:39 +01:00
Dario Nieuwenhuis
0ad7a3aa6f
stm32: fix chips without dbgmcu (wl55 cm0 core)
2022-02-25 01:16:23 +01:00
Dario Nieuwenhuis
ea5cd19c30
stm32: fix build for h7ab
2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
1ff80f8438
stm32/mco: fix on h7ab
2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
2a246be06e
stm32/time_driver: use trait impls from the main timer mod.
2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
e8ca5f9b04
stm32/rcc: fix build on l0 chips without CRS
2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
bf80504ac7
stm32: centralize gpio reg access in the gpio module.
2022-02-24 02:49:20 +01:00
Dario Nieuwenhuis
1b3c34b923
stm32/gpio: fix wrong conf for AF input.
2022-02-24 00:37:15 +01:00
Dario Nieuwenhuis
17e77ede3f
stm32f1: fix wrong AF type in uart, can.
2022-02-24 00:37:15 +01:00
Dario Nieuwenhuis
052f370de9
stm32: move ADC, DAC pin impls to build.rs
2022-02-23 20:21:28 +01:00
Dario Nieuwenhuis
30ce71127a
stm32: move MCO pin impls to build.rs
2022-02-23 19:54:46 +01:00
Dario Nieuwenhuis
1e69a8c484
stm32: move pin trait impls from macrotables to build.rs
2022-02-23 19:54:46 +01:00
Dario Nieuwenhuis
b4abb1f5c2
stm32: move dma trait impls from macrotables to build.rs
2022-02-23 19:16:37 +01:00
Dario Nieuwenhuis
2abb04d4d1
stm32/rcc: fix f3 build failure.
2022-02-23 03:42:46 +01:00
Dario Nieuwenhuis
39d06b59cd
Update stm32-data
2022-02-14 02:12:06 +01:00
bors[bot]
eb922c4655
Merge #608
...
608: stm32f4: add adc + example r=Dirbaio a=ain101
Example tested on stm32f407vg Discovery Board.
minimal adc: no vref, dma, complex sequence
Co-authored-by: Frederik <frederik@frederik.at>
2022-02-13 11:44:59 +00:00
Frederik
7a3d34c1ed
fix build for stm32f410tb
2022-02-12 23:56:50 +01:00
Frederik
6f0488cbe7
remove unnecessary mod
2022-02-12 23:55:58 +01:00
Dario Nieuwenhuis
340eb4eead
stm32: add rust stable support
2022-02-12 02:45:52 +01:00
bors[bot]
f2eb438905
Merge #615
...
615: rp: remove OptionalPin r=Dirbaio a=Dirbaio
Mirror of https://github.com/embassy-rs/embassy/pull/605 for rp2040
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-12 00:46:40 +00:00
Dario Nieuwenhuis
4a75475cfc
stm32: remove unused sealed::OptionalPin
2022-02-12 01:34:09 +01:00
Dario Nieuwenhuis
20e14b8edb
embassy, embassy-nrf: add nightly
Cargo feature to gate nightly-only features.
2022-02-12 01:16:31 +01:00
Dario Nieuwenhuis
6c925b2342
blocking_mutex: refactor to work on stable. No GATs, and can be constructed in const.
2022-02-12 01:16:31 +01:00
Frederik
e4f240823d
adc cleanup retval
2022-02-11 17:48:32 +01:00
Frederik
7a3d28ad00
stm32f4: add adc + example
...
Example tested on stm32f407vg Discovery Board.
minimal adc: no vref, dma, complex sequence
2022-02-10 23:28:41 +01:00
Dario Nieuwenhuis
b99ab3d5d9
stm32: Add standard crate-wide macros for pin/dma traits, switch all drivers to use them.
2022-02-10 21:38:03 +01:00
Dario Nieuwenhuis
a8bd3ab952
Add missing + 'd
on unborrows.
2022-02-10 16:06:42 +01:00
Dario Nieuwenhuis
550da471be
stm32: Remove OptionalPin
...
The idea behind OptionalPin has a few problems:
- you need to impl the signal traits for NoPin which is a bit weird https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/dcmi.rs#L413-L416
- you can pass any combination of set/unset pins, which needs checking at runtime https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/dcmi.rs#L130
The replacement is to do multiple `new` constructors for each combination of pins you want to take.
2022-02-10 02:38:10 +01:00
bors[bot]
1d265b73b2
Merge #601
...
601: [part 1/n] Change macrotables to build.rs codegen r=lulf a=Dirbaio
This PR replaces the "macrotables" (the macros like `stm32_data::peripherals!`) with a `const METADATA`.
Macrotables had some problems:
- Hard to debug
- Somewhat footgunny (typo the "pattern" and then nothing matches and the macro now expands to nothing, silently!)
- Limited power
- Can't count, so we had to add a [special macrotable for that](f50f3f0a73/embassy-stm32/src/dma/bdma.rs (L26)
).
- Can't remove duplicates, so we had to fallback to [Rust code in build.rs](f50f3f0a73/embassy-stm32/build.rs (L105-L145)
)
- Can't include the results as a listto another macro, so again [build.rs](https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/build.rs#L100-L101 ).
They work fine for the 95% of cases, but for the remaining 5% we need Rust code in build.rs. So we might as well do everything with Rust code, so everything is consistent.
The new approach generates a `const METADATA: Metadata = Metadata { ... }` with [these structs](https://github.com/embassy-rs/embassy/blob/unmacrotablize/stm32-metapac-gen/src/assets/metadata.rs ) in `stm32-metapac`. `build.rs` can then read that and generate whatever code.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-09 15:27:35 +00:00
bors[bot]
d91bd0b9a6
Merge #602
...
602: Add stm32 USB OTG peripherals r=Dirbaio a=chemicstry
Fixes #557 . This is similar to #580 , but for synopsys IP.
I could add examples to other chips, but I have no way of testing them. The F4 example is tested and working.
Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-02-09 00:29:00 +00:00
chemicstry
10981ee809
Cleanup
2022-02-09 02:10:54 +02:00
chemicstry
1f81a69347
Merge USB FS and HS peripherals. Add ULPI.
2022-02-09 02:02:23 +02:00
Dario Nieuwenhuis
8160af6af9
stm32: replace peripheral_rcc!
macrotable with build.rs
2022-02-09 00:58:17 +01:00
Dario Nieuwenhuis
d1a9680422
stm32: change interrupt declarations from macrotables to build.rs.
2022-02-09 00:45:52 +01:00
Dario Nieuwenhuis
940412c034
stm32/build.rs: switch to using stm32-metapac metadata and quote.
2022-02-09 00:31:21 +01:00
Matous Hybl
d37d714314
stm32: Add support for FMC
2022-02-08 17:30:20 +01:00
Matous Hybl
fee1de109d
Fix RCC configuration for H7.
2022-02-08 14:36:53 +01:00
chemicstry
db0d798b48
Add stm32 USB OTG peripherals
2022-02-08 01:46:32 +02:00
Dario Nieuwenhuis
fbaa7e59d5
stm32/dma: fix interrupt codegen for new stm32-data
2022-02-05 03:03:32 +01:00
Dario Nieuwenhuis
f8b8872fa6
Merge pull request #593 from embassy-rs/remove-traits
...
traits: migrate Delay to embedded-hal 1.0+async, remove Rng and Flash.
2022-02-05 01:53:01 +01:00
Greg V
8bb41a3281
stm32f3: fix nonexistent cfg tests
...
The rcc code was taken from stm32-rs which uses 'x' features, but
embassy uses features with full chip names.
Add these 'x' wildcards as cfgs and use them in rcc.
They will be useful for USB too.
2022-02-02 22:53:03 +03:00
Dario Nieuwenhuis
0719b05d63
traits: migrate Delay to embedded-hal 1.0+async, remove Rng and Flash.
2022-01-27 00:08:02 +01:00
Ulf Lilleengen
4032fc0655
Support unstable-trait feature for stm32
2022-01-26 22:39:06 +01:00
Sam Lakerveld
3fc54236ea
stm32/i2c: allow empty transfers with async api
2022-01-25 16:28:49 +01:00
Dario Nieuwenhuis
a8580ec78a
stm32/rcc: fix stm32f410
2022-01-24 00:50:35 +01:00
Dario Nieuwenhuis
533ceb707c
stm32: add tim4, tim5 support for time-driver (stm32f410 doesn't have tim2, tim3)
2022-01-24 00:50:10 +01:00
Dario Nieuwenhuis
79f60adbfb
stm32: add time-driver-any
cargo feature that automatically picks one available timer.
2022-01-24 00:24:53 +01:00
Dario Nieuwenhuis
889d757ab8
stm32/spi: expose all functionality as inherent methods.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
3d27a0e7cb
stm32/dma: make lowlevel api take ptrs instead of slices.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
97ab859f00
stm32/i2c: expose all functionality as inherent methods.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
c949519714
stm32/usart: expose all functionality as inherent methods.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
ade44e91c4
stm32/exti: add wait_for_high, wait_for_low.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
b526addf7b
stm32/exti: expose all functionality as inherent methods.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
58fc64722c
stm32/gpio: expose all functionality as inherent methods.
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
52e156b429
stm32: use critical_section instead of cortex_m::interrupt
2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
ecda57dff1
stm32: remove unused .pep8 file
2022-01-19 17:59:55 +01:00
Matous Hybl
4988dfe981
Make advanced timer trait not require general purpose timer trait as the timers are too different.
2022-01-18 11:18:54 +01:00
Greg V
9fcc207629
stm32l1/rcc: fix clock frequency assertion
...
It was comparing a number in Hz (!) to "32" (MHz).
embassy-stm32's units don't work like those used by stm32-hal :/
2022-01-14 22:59:57 +03:00
Greg V
456b56d4fd
stm32l1/rcc: set required flash bits for high frequencies
...
As is done for lots of other families
2022-01-14 22:59:57 +03:00
Matous Hybl
66e46d8012
Add the possibility to reconfigure Spi mode and bit order configuration on the fly.
2022-01-14 12:50:58 +01:00
Matous Hybl
e07df92651
Make RCC accessible using low-level API.
2022-01-13 16:12:45 +01:00
Matous Hybl
16d09f074a
Add simple PWM, add PWM pin definitions also accessible from low-level API.
2022-01-13 16:05:54 +01:00
Matous Hybl
a1f7a94c69
Add low level timer API.
2022-01-13 16:05:54 +01:00
Ulf Lilleengen
2bc105803a
Make exti an optional feature
...
* Add embassy-stm32 build with exti
* Add exti to examples
2022-01-12 14:28:10 +01:00
Dario Nieuwenhuis
3486d59d73
stm32: remove Dbgmcu from public API.
...
The use case is already covered by `config.enable_debug_during_sleep`.
2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
2eb0cc5df7
stm32/rcc: remove Rcc struct, RccExt trait.
...
All the RCC configuration is executed in init().
2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
c3fd9a0f44
stm32/rcc: f4/f7 cleanup and make a bit more consistent.
2022-01-04 21:17:17 +01:00
Dario Nieuwenhuis
b06e705a73
stm32/rcc: change family-specific code from dirs to single files.
...
Consistent with how other peripherals handle their versions.
2022-01-04 19:28:15 +01:00
Dario Nieuwenhuis
89b009b11d
stm32h7/rcc: remove unneeded DMA enable settings.
...
These are automatically enabled by dma::init().
2022-01-04 13:31:30 +01:00
Dario Nieuwenhuis
5d2f40b337
stm32wl/rcc: remove unneded gpio enables in RCC.
...
These are already done by gpio::init().
2022-01-04 13:31:30 +01:00
Dario Nieuwenhuis
cdc66e110f
stm32/rcc: remove builders on Config.
...
This makes API consistent with other Config structs in Embassy, where
the convention is to not use builders.
2022-01-04 13:31:30 +01:00
bors[bot]
cdfd128185
Merge #545
...
545: Add adapter for implementing async traits for blocking types r=lulf a=lulf
This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-01-03 14:17:21 +00:00
bors[bot]
c0e94a7042
Merge #563
...
563: Initial ADC support for on STM32F1xx r=Dirbaio a=sjoerdsimons
Add an ADC implementation for F1 based chips. Primarily tested using ADC1, proper functionality for ADC2 probably needs some extra work as it's mainly a slave and can't e.g. measure vrefint by itself.
Needs https://github.com/embassy-rs/stm32-data/pull/115
Co-authored-by: Sjoerd Simons <sjoerd@collabora.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-01-01 11:45:23 +00:00
bors[bot]
c20ef419a6
Merge #558
...
558: Port buffered uart to v1 stm32 hardware r=Dirbaio a=DCNick3
#526 seems to suggest that it will be rewritten for DMA support, but I am not sure how to implement it and the port was quite straightforward, so here it is. It might be immediately useful before DMA version will be implemented
Note that I have not tested this on v2 hardware
Co-authored-by: Nikita Strygin <nikita6@bk.ru>
2022-01-01 10:51:14 +00:00
Sjoerd Simons
92f2c6d09c
adc: Implement support for f1 ADC block
...
Add basic support for the STM32F1xx ADC blocks.
2021-12-30 10:51:54 +01:00
Sjoerd Simons
a93b1141e9
stm32f1: Store adc clock rate in Clocks struct
2021-12-30 10:50:28 +01:00
Ben Gamari
8da6471a50
stm32/dac: Fix disable_channel
...
Previously disable_channel enabled rather than disabled the requested
channel due to an apparent copy-paste error. Refactor to eliminate this
sort of issue by construction.
2021-12-28 23:27:59 -05:00
Nikita Strygin
a94932be02
Mark clear_interrupt_flag as unsafe
2021-12-26 18:29:41 +03:00
Nikita Strygin
6b08c70273
Port buffered uart to v1 stm32 hardware
...
- No DMA
- Create clear_interrupt_flag function to
handle differences between v1 and v2 hardware
2021-12-26 18:13:19 +03:00
Dario Nieuwenhuis
d1740b10f0
Lower some verbose logs to trace.
2021-12-23 13:43:14 +01:00
Ulf Lilleengen
3811c0a401
Add adapter for implementing async traits for blocking types
...
This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.
Add examples to stm32l4 for using this feature.
2021-12-17 12:54:51 +01:00
Ulf Lilleengen
2bbd1ddb8a
Remove unneeded rustfmt::skip
2021-12-16 11:37:53 +01:00
Ulf Lilleengen
985c11fad5
Update rust-toolchain
2021-12-16 11:34:20 +01:00
bors[bot]
d5a3064c2c
Merge #540
...
540: Initial support for STM32F3 r=Dirbaio a=VasanthakumarV
The [companion PR](https://github.com/embassy-rs/stm32-data/pull/109 ) in `stm32-data` should be merged before this PR.
The examples were tested on an STM32F303VC MCU.
Co-authored-by: VasanthakumarV <vasanth260m12@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-16 07:30:03 +00:00
Grant Miller
6597e67036
Add finish_dma function
2021-12-14 17:46:25 -06:00
Grant Miller
a13a7a6616
Replace wait_for_idle with spin_until_idle
2021-12-14 17:46:25 -06:00
Grant Miller
e75cb1a564
Regs type alias
2021-12-14 15:39:00 -06:00
Grant Miller
b06658c195
Refactor new
2021-12-14 15:39:00 -06:00
VasanthakumarV
78c5d65ca9
[lint] Add newline in pwr file
2021-12-13 18:16:58 +05:30
VasanthakumarV
3f33d307ff
[feature] Add rcc register support for F3
2021-12-13 14:50:13 +05:30
VasanthakumarV
e2c074d133
[feature] Add pwr register support for F3
2021-12-13 13:49:41 +05:30
VasanthakumarV
7733d11f90
[generate] Add stm32f3 chips to the Cargo manifest
2021-12-13 13:49:41 +05:30
huntc
45ef944457
Stm flush required implementing also, along with std alloc split
2021-12-10 15:11:41 +11:00
Matous Hybl
1dd5a71c07
Add DCMI peripheral support.
2021-12-09 12:56:39 +01:00
Dario Nieuwenhuis
4ddd23d623
stm32/usart: unify v1 and v2
2021-12-08 05:12:48 +01:00
Dario Nieuwenhuis
022c4cb739
stm32/dma: simplify impls a bit.
2021-12-08 03:30:07 +01:00
Dario Nieuwenhuis
b316d2620c
stm32/dma: improve trait docs, seal Word.
2021-12-08 03:18:15 +01:00
Dario Nieuwenhuis
6179da6b9c
stm32/dma: eagerly start transfers when calling the functions.
...
`async fn`s do nothing until polled, but we want the DMA transfer to
immediately start in this case. Drivers rely on it. Some require special
orders, such as "start DMA, start SPI, then wait for DMA" which is awkward
to do without eager start.
Also use a manually-impl'd future, this allows getting rid of the "double"
Unborrow channel clone.
2021-12-08 03:04:39 +01:00
Dario Nieuwenhuis
4e349d0f5d
stm32/dma: use the right waker slot number for DMA2 (must add 8)
2021-12-08 01:54:31 +01:00
Dario Nieuwenhuis
fd2fe62b5f
stm32/dma: rename is_stopped to is_running.
...
Note that this does NOT invert the result of `en()` because it was
wrong before.
2021-12-08 01:51:39 +01:00
Matous Hybl
b2910558d3
Refactor DMA traits.
2021-12-07 21:43:47 +01:00
Joshua Salzedo
e2719aba10
Further extend the dma channel trait
2021-12-07 21:43:47 +01:00
Joshua Salzedo
93e047ede2
cargo fmt
2021-12-07 21:43:47 +01:00
Joshua Salzedo
3411039cb9
Implement extended Channel trait to bdma.rs
2021-12-07 21:43:47 +01:00
Joshua Salzedo
2d2c6d0e01
Implement extended Channel trait to dma.rs
2021-12-07 21:43:47 +01:00
Joshua Salzedo
3272987d92
Expand channel trait
2021-12-07 21:43:47 +01:00
Ulf Lilleengen
f9ac0c8047
Add back MISO flush
2021-12-07 09:40:45 +01:00
Grant Miller
79baa04118
Implement blocking traits with a macro
2021-12-07 00:03:52 -06:00
Grant Miller
bf1f80afa1
Unify blocking trait impls
2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5
Move async trait impls to mod
2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d
check_error_flags function
2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b
Move Word trait to mod
2021-12-07 00:03:52 -06:00
Grant Miller
7c78247be3
v2: set frxth and ds in new
2021-12-06 22:36:53 -06:00
Grant Miller
d76bc45e30
Move Spi drop impl to mod
2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024
Move set_word_size to mod
2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc
Add tx_ptr and rx_ptr methods
2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6
Move Spi::new and Spi::compute_baud_rate to mod
2021-12-06 15:19:24 -06:00
Grant Miller
75374ce7e8
Fix ssoe in v1
2021-12-06 14:57:53 -06:00
Grant Miller
e1cccc8391
Move Spi to mod (without NoDma defaults)
2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665
Track current word size in v2 and v3 also
2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb
Move WordSize methods to mod
2021-12-06 14:13:25 -06:00
Grant Miller
d426caefbf
Move NoPin impls from v1 to mod
2021-12-06 14:02:21 -06:00
Ulf Lilleengen
81ec4c82fd
Flush MISO before transfer operation
2021-12-03 09:53:28 +01:00
Matous Hybl
6e0eb33ea8
Downcast timer to GP16 for time drivers.
2021-12-02 18:07:05 +01:00
Matous Hybl
f0cb77443c
Fix wrong pin configuration in STM32's SPI v3.
2021-12-01 22:18:14 +01:00
Dario Nieuwenhuis
b0fabfab5d
Update stm32-data: rcc regs info comes from yamls now.
2021-11-29 02:28:02 +01:00
Ulf Lilleengen
25b49a8a2a
Remove common clock types
...
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
Dario Nieuwenhuis
006e567716
stm32/pwm: allow using the advanced timer instances too.
2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
d7d1258411
stm32/pwm: small cleanups
2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc
stm32/pwm: impl instance/pin for all chips
2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2
stm32/pwm: initial commit
2021-11-27 02:50:30 +01:00
Dario Nieuwenhuis
88d4b0c00d
stm32: add stm32g4 support.
2021-11-27 02:34:23 +01:00
Ulf Lilleengen
cd9a1d547c
Ensure SPI DMA write is completed
...
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
Dario Nieuwenhuis
e187f50f4b
stm32: remove unused deps
2021-11-24 01:41:51 +01:00
Dario Nieuwenhuis
dfb6d407a1
stm32: rename core features from _cmX to -cmX, cleanup gen.
2021-11-23 23:49:06 +01:00
Wilfried Chauveau
eac604accd
Fix missing lifetime bounds
2021-11-21 10:10:28 +00:00
Dario Nieuwenhuis
24e5013c00
Allow unused to fix build failure in u5
2021-11-17 21:43:05 +01:00
Bob McWhirter
ee1490bce1
Move to the newly released bxcan crate that supports defmt 0.3.
2021-11-15 13:18:53 -05:00
Bob McWhirter
c2da498263
Update to defmt 3.0ish.
...
Lots of gitrevs deps.
2021-11-15 11:09:08 -05:00
bors[bot]
8193885cb5
Merge #482
...
482: Add MCO peripheral. r=Dirbaio a=matoushybl
This PR adds an abstraction over STM32 RCC feature called MCO (Microcontroller Clock Output). The clock output can bind to several clock sources and then can be scaled using a prescaler.
Given that from the embassy ecosystem the RCC is generaly invisible to the user, the MCO was implemented as a separate peripheral bound to the pin where the clock should appear.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-11 16:20:02 +00:00
Matous Hybl
c14642cffc
Add MCO peripheral.
2021-11-11 11:34:09 +01:00
bors[bot]
96e2f0dfc5
Merge #468
...
468: Add v1c ethernet driver for the STM32F7 family. r=Dirbaio a=matoushybl
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-10 22:07:38 +00:00
Matous Hybl
f0ba79059e
Add v1c ethernet driver for the STM32F7 family.
2021-11-10 10:16:46 +01:00
Bob McWhirter
12a64b867b
More support for U5 PWR (ish), RCC, and FLASH (ish).
2021-11-08 14:27:33 -05:00
Bob McWhirter
5f124ec49f
Update U5 to init RCC.
2021-11-08 14:20:51 -05:00
Matous Hybl
9b5d9fbfca
Fix v2 ethernet pin definitions. Fix ethernet example for H7 nucleos.
2021-11-04 16:25:30 +01:00
bors[bot]
1bf6e646c9
Merge #465
...
465: Adjust for STM32U5. r=lulf a=bobmcwhirter
Co-authored-by: Bob McWhirter <bmcwhirt@redhat.com>
2021-11-02 20:42:41 +00:00
Bob McWhirter
d1272e00bb
Prefix unused variable for now.
2021-11-02 15:45:56 -04:00
Bob McWhirter
44056c2e75
Less allowy.
2021-11-02 15:32:20 -04:00
Bob McWhirter
076c795ebb
Even more allowed unused.
2021-11-02 15:28:14 -04:00
Bob McWhirter
6bbf450478
Allow unused macros temporarily until U5 supports DMA.
2021-11-02 15:20:42 -04:00
Ulf Lilleengen
205a223af3
Update versions of critical-section and atomic-polyfill
2021-11-02 18:52:03 +01:00
Bob McWhirter
705523d0ea
Fix formatting.
2021-11-02 12:13:42 -04:00
Bob McWhirter
f12b70535b
Adjust for STM32U5.
2021-11-02 12:05:24 -04:00
Bob McWhirter
bbff98ed0d
Move the use
inside the macro call, inside another set of braces in case it percolates up twice.
2021-10-26 14:34:03 -04:00
Bob McWhirter
a72816492a
Only attempt to enable the dmamux peri clock if it has an enable bit.
2021-10-26 14:19:03 -04:00
Bob McWhirter
959aecf6ac
Enable the DMAMUX clocks.
2021-10-26 14:01:39 -04:00
Matous Hybl
015cad84dd
Initial support for STM32F767ZI.
2021-10-26 17:33:28 +02:00
bors[bot]
01e5376b25
Merge #456
...
456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf
Example is tested on STM32L475VG.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-10-26 11:59:14 +00:00
Ulf Lilleengen
e55726964d
Fix clock setup for MSI and PLL to allow RNG opereation
...
Add RNG example using PLL as clock source.
2021-10-26 13:45:53 +02:00
Ulf Lilleengen
f8ebc967a9
Add implementation of async trait for STM32 I2C v2
...
* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
2021-10-21 12:30:02 +02:00
Ulf Lilleengen
d2a79a46c5
Configure the correct pin instances
2021-10-21 11:57:00 +02:00
Tobias Pisani
43a7226d8b
inline FRE register check for SPI on F1
2021-10-11 23:33:32 +02:00
Tobias Pisani
2cbb8a7ece
Add AFType::Input for input configurations.
2021-10-11 22:57:21 +02:00
Tobias Pisani
259e84e68e
Make miso/mosi optional when for unidirectional spi
...
Only suported on v1 currently
2021-10-11 22:57:21 +02:00
Tobias Pisani
c44bed300b
Correctly set alternate function for stm32f1 gpios
2021-10-11 22:57:21 +02:00
Tobias Pisani
091e7e1f98
Generate USART pin definitions for stm32f1
2021-10-11 22:57:21 +02:00
Tobias Pisani
39880de958
partial alternate function configuration on STM32f1
2021-10-11 22:57:10 +02:00
Tobias Pisani
f9a576d13d
feat: Add spi support for STM32F1 variants
2021-10-11 22:39:48 +02:00
Ben Gamari
006bbea51a
stm32/adc: Add IN0 channel
2021-09-29 00:32:40 -04:00
Ben Gamari
5a38cc2140
stm32/dac: Ensure that clock is enabled
2021-09-29 00:32:40 -04:00
Ben Gamari
0b9961584b
stm32/adc: Ensure that clock is enabled
...
Sadly due to the inconsistency in clocking configuration across devices
we cannot use RccPeripheral.
2021-09-29 00:32:40 -04:00
Ben Gamari
573e6ec373
stm32g0: Add support for low-power run
2021-09-28 21:19:10 -04:00
Ben Gamari
794798e225
stm32g0: Add support for HSI divider
2021-09-28 21:19:10 -04:00
Ben Gamari
aa4069fe10
stm32/adc: Fix ADC support for STM32G0
2021-09-28 21:19:10 -04:00
Ben Gamari
e2e0464d04
stm32/adc: Factor out conversion logic
...
Also guard errata workaround correctly.
2021-09-28 18:00:05 -04:00
Mariusz Ryndzionek
ce361abb1b
Changing the casts (code review request)
2021-09-28 18:31:04 +02:00
Mariusz Ryndzionek
bce909ec1e
Initial STM32F1 family support with two examples for STM32F103C8 (Blue Pill)
2021-09-28 18:31:04 +02:00
Joshua Salzedo
ab60cfd64b
Patch additional regressions
2021-09-27 15:48:56 -07:00
Joshua Salzedo
67e2f9159c
set moder::ALTERNATE last when configuring pins to AF modes.
...
- as per STM32F4xx_hal's impl
2021-09-27 15:27:43 -07:00
Joshua Salzedo
07e20a7443
Pub use version-specific CRC symbols, not just the CRC struct.
2021-09-27 11:17:31 -07:00
Joshua Salzedo
a26ffeb84b
Cargo fmt
2021-09-27 10:49:32 -07:00
Joshua Salzedo
e36d4f460a
Fix variable names in crc_v2/v3.
...
removed `reclaim` in crc_v1.
used write instead of modify.
renamed `init` to `reset` in crc_v1.
2021-09-27 10:46:09 -07:00
Joshua Salzedo
43ad28b9f9
Use unborrow for CRC constructor
...
sort feature gates
fix repetition in CRC config names
2021-09-27 10:38:55 -07:00
Joshua Salzedo
7392e33ad5
cargo fmt
2021-09-26 19:20:21 -07:00
Joshua Salzedo
e67af514e9
Fix v2/3 module paths
2021-09-26 19:15:54 -07:00
Joshua Salzedo
642b0825a6
V3 is just an extension of V2, merge modules.
2021-09-26 19:14:08 -07:00
Joshua Salzedo
f9ff5336d4
Merge all of the crc_v2 configurations into a single modify call
2021-09-26 18:46:19 -07:00
Joshua Salzedo
8fac444c4e
Flesh out v2 config writes
2021-09-26 18:39:55 -07:00
Joshua Salzedo
afef19d813
Start work towards CRC_V2
2021-09-26 18:26:20 -07:00
Joshua Salzedo
7899d73359
Expose read so the value can be obtained without a write.
2021-09-26 17:28:58 -07:00
Joshua Salzedo
c892289b2c
Actually export CRC
2021-09-26 17:26:33 -07:00
Joshua Salzedo
24dea91f5a
Fix interface changes
2021-09-26 17:24:48 -07:00
Joshua Salzedo
e18a27eea2
First pass at CRC_V1
2021-09-26 16:46:17 -07:00
Joshua Salzedo
e527892d89
Start work on CRC_v1
2021-09-26 16:29:22 -07:00
Dario Nieuwenhuis
f8d833e0c5
Merge pull request #403 from mryndzionek/af_type
...
Small adjustment to 'set_as_af' interface
2021-09-24 20:20:45 +02:00
Mariusz Ryndzionek
e4b37c40c9
Code review request - moving OutputType
to mod sealed
2021-09-24 19:56:48 +02:00
Mariusz Ryndzionek
d371298a27
Small adjustment to 'set_as_af' interface
...
Small adjustment to 'set_as_af' interface - v2
2021-09-24 18:39:07 +02:00
Vincent Stakenburg
7d6d274d55
Add MSI and PLL clock source for L4
2021-09-24 18:27:39 +02:00
Ulf Lilleengen
b6fc19182b
Add pwr for L1 and update RCC to new reg block
2021-09-23 14:51:16 +02:00
Ulf Lilleengen
9d45018077
Refactor V1 SPI
2021-09-21 14:50:23 +02:00
Ulf Lilleengen
c79485c286
Support for STM32L1
...
* Add RCC
* Fix more issues with dash in chip names
* Update stm32-data version
* Add blinky and spi example
2021-09-21 14:50:23 +02:00
Ulf Lilleengen
fb697a2657
Updates
2021-09-15 12:46:20 +02:00
Dario Nieuwenhuis
bb72f7eb98
Merge pull request #390 from lulf/wasm-executor
...
Wasm executor support
2021-09-13 18:55:17 +02:00
Ulf Lilleengen
99a94f1d50
Update version of critical-section
2021-09-13 17:05:17 +02:00
Dario Nieuwenhuis
d6faf69e09
Merge pull request #378 from numero-744/gen-features-using-rust-not-python
...
Use our beloved Rust instead of Python
2021-09-13 16:47:01 +02:00
Ulf Lilleengen
e24528051b
Add WASM support for executor
...
* Adds an executor for WASM runtimes based on wasm_bindgen.
* Add time driver based on JS time handling.
* Add example that can run in browser locally.
* Update to critical-section version that supports 'std' flag
2021-09-13 16:42:39 +02:00
Côme ALLART
99ccf18160
fix(gen-features): keep data files order
2021-09-11 20:04:57 +02:00
Dario Nieuwenhuis
ead987245d
embassy: Refactor module structure to remove kitchen-sink util
.
2021-09-11 02:35:35 +02:00
Dario Nieuwenhuis
f2623e7e9b
Update lots of deps
2021-09-11 01:35:23 +02:00
Adam Greig
14fa6c2760
STM32H7: Ethernet: Disable RA in MAC filtering, fix order of MACA0 register writes.
2021-09-06 23:16:43 +01:00
Bob McWhirter
d4bf78a0c1
Don't set SAF=true, do set RA=true for Ethernet.
...
Source-Address-Filtering is not helping the board to receive packets.
For unknown reasons, the Receive-All is required, when in theory
it should not be required. Until we figure it out, follow the
stm32h7xx-hal example of setting RA=true.
2021-09-06 14:21:26 -04:00
Dario Nieuwenhuis
eff8ae9c4d
Merge pull request #381 from lulf/stm32wl55-subghz
...
Add HAL for SubGhz peripheral for STM32 WL series
2021-09-06 00:58:42 +02:00
Dario Nieuwenhuis
de016e8456
Remove trait_alias, allow(incomplete_features).
...
trait_alias seems unused. no idea why it's there.
2021-09-03 17:00:58 +02:00
Ulf Lilleengen
0f3d278ce3
Temporarily comment unused code
2021-09-02 11:31:38 +02:00
Ulf Lilleengen
4dccda085f
Add missing files for G0
2021-09-02 11:19:54 +02:00
Ulf Lilleengen
f175574bcf
Cargo fmt
2021-09-02 10:43:08 +02:00
Ulf Lilleengen
16aa1d1770
ADd missing file
2021-09-02 10:42:11 +02:00
Ulf Lilleengen
7ad6280e65
Add HAL for SubGhz peripheral for STM32 WL series
...
Based on the HAL from stm32wl, the peripheral driver has been
modified to fit into embassy, using the embassy APIs, providing
operation of the radio peripheral.
The initial version does not offer any async APIs, but the example
shows how the radio IRQ can be used to perform async TX of the radio.
2021-09-02 10:39:56 +02:00
Bob McWhirter
37ceae908b
Rename Random impl to Rng.
...
Create Random struct providing next_x(range) for all T:Rng.
2021-09-01 09:39:33 -04:00
Bob McWhirter
7fa3b27cac
Move random utils to another trait.
2021-08-30 09:55:29 -04:00
Bob McWhirter
d525f51940
Add a convenience next(range) to Rng.
2021-08-27 16:10:01 -04:00
Côme ALLART
022b809248
refactor(gen_features): use Rust instead of Python
...
Done for /embassy-stm32 only
The new generator is in /stm32-gen-features
/stm32-metapac could/should be added too
A CI check "generated features up to date" could/should be performed
2021-08-27 11:09:27 +02:00
Dario Nieuwenhuis
e56c6166dc
Merge pull request #373 from embassy-rs/docs
...
Time driver improvements, docs.
2021-08-26 23:37:37 +02:00
Bob McWhirter
dc394dd477
Fixes #374 : Ensure Rng's error is defmt-able.
2021-08-26 14:04:12 -04:00
numero-744
1098072384
build(stm32): remove gen.py build dependency
2021-08-26 18:59:37 +02:00
Dario Nieuwenhuis
7c0990ad1e
time: allow storing state inside the driver struct.
2021-08-25 21:06:27 +02:00
Bob McWhirter
4aa52f1b9e
Formatting.
2021-08-24 14:56:45 -04:00
Bob McWhirter
e36ae76e45
Fix blocking-write for SPI.
2021-08-24 14:44:47 -04:00
Ben Gamari
e2f71ffbbd
Add support for STM32G0
2021-08-20 00:15:11 +02:00
Dario Nieuwenhuis
174c51f097
stm32/metapac: check GPIO RCC regs are always found.
2021-08-19 23:59:50 +02:00
Dario Nieuwenhuis
2c992f7010
stm32: move dbgmcu stuff to toplevel config setting, defaulting to true.
2021-08-19 23:50:19 +02:00
Dario Nieuwenhuis
446d6c275c
stm32: remove last use of python at build time
2021-08-19 23:42:18 +02:00
Dario Nieuwenhuis
9f51f9a170
stm32/wl: add stub APB3 to get it to build.
...
Completely untested.
2021-08-19 22:51:41 +02:00
Dario Nieuwenhuis
637fcdd316
stm32/rcc: update for new version naming
2021-08-19 22:17:45 +02:00
Dario Nieuwenhuis
ec51880e28
stm32/exti: unify all versions into single impl
2021-08-19 22:17:17 +02:00
Dario Nieuwenhuis
d3aeb45fb3
Update cortex-m-rt to v0.7 for stm32, rp.
2021-08-19 00:56:11 +02:00
Timo Kröger
f141b98741
bxcan: Cleanup
...
Older families like F1 and F4 have a consistent naming for the CAN
peripherals: CAN when there is only one instance, CAN1/CAN2/CAN2 if
there are multiple instances.
Newer families like L4 and F7 use the name CAN1 even if there is only
one instance. The number of filter banks is incorrect for those.
Affected chips:
* STM32F722
* STM32F723
* STM32F730
* STM32F732
* STM32F733
* STM32L4P5
* STM32L4Q5
* STM32L4R5
* STM32L4R7
* STM32L4R9
* STM32L4S5
* STM32L4S7
* STM32L4S9
* STM32L431
* STM32L432
* STM32L433
* STM32L442
* STM32L443
* STM32L451
* STM32L452
* STM32L462
* STM32L471
* STM32L475
* STM32L476
* STM32L485
* STM32L486
2021-08-18 21:58:50 +02:00
Timo Kröger
0c3bede64f
bxcan: Make bxcan
a hard dependency
...
There seems no way to enable a optional dependency from build.rs or
features passed through the command line.
2021-08-18 21:58:50 +02:00
Timo Kröger
191a589820
bxcan: namechange "bxcan_v1" -> "can_bxcan"
2021-08-18 21:58:50 +02:00
Timo Kröger
dc6b7f3cba
bxcan: Disable on drop
2021-08-18 21:58:50 +02:00
Timo Kröger
7c405250a7
CAN support with bxcan crate
2021-08-18 21:58:50 +02:00
Ulf Lilleengen
4df63f5379
Add per-core EXTI support
...
* Generate a core index put into the PAC for the peripherals to use as
index into registers.
* Add EXTI v2 which uses CORE_INDEX to index exti registers
2021-08-17 16:22:47 +02:00
Ulf Lilleengen
61409e2fb6
Add example for STM32WL55
2021-08-17 16:22:47 +02:00
Bob McWhirter
a93ed2bed6
Add H7 exti button example using correct EXTI reg block offsets.
2021-08-16 15:15:07 -04:00
Ulf Lilleengen
cbff0398bb
Add IRQ-driven buffered USART implementation for STM32 v2 usart ( #356 )
...
* Add IRQ-driven buffered USART implementation for STM32 v2 usart
* Implementation based on nRF UARTE, but simplified to not use DMA to
avoid complex interaction between DMA and USART.
* Implementation of AsyncBufRead and AsyncWrite traits
* Some unit tests to ring buffer
* Update polyfill version
* Update sub module to get usart IRQ fix
2021-08-16 17:16:49 +02:00
Thales Fragoso
c7ae2d2a3a
stm32: Add fences to DMA code
2021-08-10 20:45:41 -03:00
Ben Gamari
40e7176e13
embassy-stm32: Eliminate use of unwrap
2021-08-05 22:40:08 +02:00
Ben Gamari
41aaff95f8
stm32h7: Use unwrap!
2021-08-05 22:39:59 +02:00
Ben Gamari
e44acd0d56
stm32f4: Use unwrap! where possible
2021-08-05 22:39:59 +02:00
Dario Nieuwenhuis
05e50e1f4a
time_driver: use regular fn ptr -> raw ptr casts
2021-08-05 19:19:47 +02:00
Dario Nieuwenhuis
b1d631d639
stm32/time: add Cargo features to choose tim2/tim3
2021-08-05 19:14:09 +02:00
Dario Nieuwenhuis
0ea6a2d890
time: replace dyn clock/alarm with a global Driver trait
2021-08-05 19:14:09 +02:00
Dario Nieuwenhuis
cfa1f61154
Merge pull request #344 from bobmcwhirter/remove_builders
...
Remove builders from Config(s) and examples.
2021-08-04 21:32:39 +02:00
Dario Nieuwenhuis
07d4b196f7
Update nightly, remove removed features.
2021-08-04 19:48:14 +02:00
Dario Nieuwenhuis
9bd34429f3
stm32: add missing + 'a
bounds on trait GATs
2021-08-04 19:39:54 +02:00
Bob McWhirter
f4971fbb79
Further work sharing config for example and removing duplicated code.
2021-08-04 13:39:02 -04:00
Bob McWhirter
03f15d3a60
Remove builders from Config(s) and examples.
2021-08-04 11:32:39 -04:00
Dario Nieuwenhuis
de77dc11ca
Merge pull request #301 from thalesfragoso/i2cv2-dma
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i2c-v2: Implement write_dma and write_dma_vectored
2021-08-04 12:28:18 +02:00
Dario Nieuwenhuis
5d31dd328f
Merge pull request #341 from lulf/usart-dma-read
...
Add uart::Read DMA-based implementation
2021-08-04 11:02:15 +02:00
Ulf Lilleengen
0d02342b2d
Rename bread -> read_blocking
2021-08-04 08:34:30 +02:00
Bob McWhirter
88c11a653c
Formatting fixes.
2021-08-03 14:12:11 -04:00
Bob McWhirter
d7409d63e8
Enhance Rcc configuration to be more fluentish.
...
Clean up H7 examples to remove all vegan HALs and PACs.
2021-08-03 13:57:18 -04:00
Ulf Lilleengen
6ff0614cb6
Add uart::Read DMA-based implementation
...
* Rename existing read() to bread() (blocking)
2021-08-03 15:31:24 +02:00
Dario Nieuwenhuis
3f28bb6c77
common: Initialize PeripheralMutex state with closure to ensure it's done in-place.
2021-08-02 20:13:41 +02:00
Dario Nieuwenhuis
e238079d7d
Make const the states when able.
2021-08-02 19:59:02 +02:00
Dario Nieuwenhuis
63ac7ac799
Mark new
s as unsafe due to not being leak-safe.
2021-08-02 19:55:04 +02:00
Dario Nieuwenhuis
af87031d62
hal-common: remove Pin in PeripheralMutex
2021-08-02 19:55:04 +02:00
Bob McWhirter
63b32b39e1
Use an em bikeshed instead of an underscore bikeshed.
2021-08-02 13:29:06 -04:00
Bob McWhirter
5f9447abb4
Put the implicit memory.x behind a memory_x
feature on embassy-stm32.
2021-08-02 13:21:30 -04:00
Bob McWhirter
3a00a1dba7
Undo the pwr-guarding cfg.
2021-08-02 11:34:41 -04:00
Bob McWhirter
f6c5f039c8
Emit a default memory.x alongside device.x from metapac.
2021-08-02 11:23:55 -04:00
Thales Fragoso
64a3ebd183
i2c-v2: Use new interrupts macro
2021-08-01 19:10:42 -03:00
Thales Fragoso
c1bb83d29d
i2c-v2: Deref interrupt enabling in write_dma_internal
2021-08-01 19:10:42 -03:00
Thales Fragoso
6ddc83029a
i2c-v2: Simplify write_dma
2021-08-01 19:10:42 -03:00
Thales Fragoso
362f7efe99
i2c-v2: Implement write_dma and write_dma_vectored
2021-08-01 19:10:42 -03:00
Dario Nieuwenhuis
3835278567
Merge pull request #321 from thalesfragoso/f4-pll
...
F4 PLL
2021-07-31 11:08:46 +02:00
Thales Fragoso
21e3acaa00
stm32: Use build.rs to generate a more coarse feature
2021-07-31 02:52:26 -03:00
Thales Fragoso
0421c57bd6
F4: Add PWR configuration to PLL
2021-07-29 18:43:15 -03:00
Thales Fragoso
5cfb9adad8
f4-pll: Add max values per chip
2021-07-29 18:43:15 -03:00
Thales Fragoso
e7714983b3
f4-rcc: Add option to enable debug_wfe and add hello example
2021-07-29 18:43:15 -03:00
Thales Fragoso
5abaf8e9d6
Start working on the F4 PLL
2021-07-29 18:43:13 -03:00
Timo Kröger
9342497132
stm32wl55: Use Dbgmcu::enable_all
2021-07-29 17:38:40 +02:00
Timo Kröger
cad43587e6
stm32l0: Use embassy::main
for examples
2021-07-29 17:37:32 +02:00
Timo Kröger
2a4890165d
stm32f0: Enable debug access in low power modes
2021-07-29 15:35:23 +02:00
Dario Nieuwenhuis
7bfb763e09
Rename embassy-extras to embassy-hal-common
2021-07-29 13:44:51 +02:00
Dario Nieuwenhuis
c8a48d726a
Merge pull request #277 from Liamolucko/fix-peripheral-ub
...
extras: Fix UB in `Peripheral`
2021-07-29 13:08:30 +02:00
Liam Murphy
d5ba35424d
Replace PeripheralStateUnchecked
with register_interrupt_unchecked
2021-07-29 15:11:26 +10:00
Bob McWhirter
8759213fcc
Use new interrupt! table format to /enable/ the IRQs also.
2021-07-27 13:23:33 -04:00
Bob McWhirter
b910551c9a
Generate more rows in the interrupts! table.
...
Adjust DMA/BDMA to use the new style.
2021-07-27 12:52:01 -04:00
Liam Murphy
079526559f
Remove critical sections from PeripheralMutex
interrupt handler by checking the interrupt's priority on startup.
...
Since `PeripheralMutex` is the only way to safely maintain state across interrupts, and it no longer allows setting the interrupt's priority, the priority changing isn't a concern.
This also prevents other causes of UB due to the interrupt being exposed during `with`, and allowing enabling the interrupt and setting its context to a bogus pointer.
2021-07-27 17:28:52 +10:00
Timo Kröger
06fb2a7a80
Enable SYSCFG clock in exti::init()
2021-07-24 11:13:49 +02:00
Dario Nieuwenhuis
3c7375c6cd
stm32/bdma: do not clear IF on IRQ handler
2021-07-24 10:01:11 +02:00
Timo Kröger
43c4f24207
STM32 BDMA: Use interrupt flags instead of atomics
2021-07-24 09:26:07 +02:00
Timo Kröger
5a4a5ce334
STM32 DMA: Use interrupt flags instead of atomics
2021-07-24 09:26:07 +02:00
Bob McWhirter
83f63890e5
Actually take a &mut of that read slice.
2021-07-23 13:22:39 -04:00