Commit graph

1573 commits

Author SHA1 Message Date
Rasmus Melchior Jacobsen
14e3e72b0f Add missing implementations for f4 alternate regions 2023-05-23 22:51:26 +02:00
Rasmus Melchior Jacobsen
faf506b300 Remove Drop for AltFlashLayout 2023-05-23 22:50:41 +02:00
Rasmus Melchior Jacobsen
879c621394 Ensure FlashRegion can only be created within this crate 2023-05-23 22:49:27 +02:00
bors[bot]
1fdde8f03f
Merge #1457
1457: TL Mbox read and write for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, built upon the work done in #1405 and #1424, and was tested on an stm32wb55rg.

This pull request aims to add read and write functionality to the TL mailbox for stm32wb microcontrollers

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-23 01:15:22 +00:00
Rasmus Melchior Jacobsen
e9121cba2c stm32: Fix watchdog timeout computation 2023-05-22 14:22:27 +02:00
xoviat
7f702fd6f1 stm32/ipcc: fix warnings 2023-05-20 11:29:53 -05:00
xoviat
383bef1711 stm32/ipcc: naming 2023-05-20 10:24:26 -05:00
xoviat
5e86188c25 stm32/ipcc: cleanup naming 2023-05-20 10:24:13 -05:00
xoviat
661b1f3373 stm32/ipcc: remove constrain 2023-05-20 10:23:57 -05:00
Dario Nieuwenhuis
8b9306ed5c stm32/sdmmc: fix "drop with a value that implements Copy does nothing" warning. 2023-05-19 18:00:33 +02:00
Dario Nieuwenhuis
9f7392474b Update Rust nightly. 2023-05-19 17:12:39 +02:00
bors[bot]
9dff6b9d81
Merge #1419
1419: stm32/pwm: improve dead-time api r=Dirbaio a=xoviat



Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-19 14:41:44 +00:00
Dario Nieuwenhuis
f43d57846e stm32/usb: do not require embassy-time.
Fixes #1466
2023-05-19 15:20:37 +02:00
goueslati
a8953b5c66 cleanup 2023-05-15 10:34:52 +01:00
goueslati
d97724cca3 tl_mbox read and write 2023-05-15 10:25:02 +01:00
bors[bot]
4567eff78e
Merge #1455
1455: Remove unused `feature(type_alias_impl_trait)`. r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-05-14 21:57:51 +00:00
Dario Nieuwenhuis
2d65373f63 Remove unused feature(type_alias_impl_trait). 2023-05-14 23:44:53 +02:00
bors[bot]
ae4827587c
Merge #1454
1454: stm32f0 flash implementation r=Dirbaio a=jp99

i've copied and modified the f3 implementation and it seems to be working.


Co-authored-by: Jaap Prickartz <jaap@tetra.nl>
2023-05-14 21:39:55 +00:00
Jaap Prickartz
ec7a4fd9cc stm32f0 flash implementation 2023-05-14 21:57:31 +02:00
Timo Kröger
977a7906e4 stm32 uart: Fix error flag handling for blocking operations
Clear and report the error flags one by one and pop the data byte only
after all error flags were handled.

For v1/v2 we emulate the v3/v4 behaviour by buffering the status
register because a read to the data register clears all flags at once
which means we might loose all but the first error.
2023-05-14 21:10:37 +02:00
goueslati
3810fe6a20 tl_mbox: added zigee, lld tests and ble lld tables to ref table 2023-05-12 10:26:46 +01:00
bors[bot]
7f96359804
Merge #1424
1424: add TL maibox for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, build upon the work done in #1405, and was tested on an stm32wb55rg.

This pull request aims to add the transport layer mailbox for stm32wb microcontrollers. For now it's only capable of initializing it and getting the firmware information

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: Ghaith Oueslati <73850124+OueslatiGhaith@users.noreply.github.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-11 22:48:55 +00:00
Dirk Stolle
0584312ef0 Fix some typos 2023-05-08 23:25:01 +02:00
Marco Pastrello
db2bc8783e Improve readability 2023-05-05 19:04:58 +02:00
Marco Pastrello
c37f86ff1c removes unecessary braces 2023-05-05 00:12:32 +02:00
Marco Pastrello
2dcbe75cca beautify 2023-05-04 23:51:42 +02:00
Marco Pastrello
5158014f3f PPLXTPRE is a bool.
This flag for example permits the following clock tree
configuration on stm32f103r8

    let mut config = Config::default();
    config.rcc.hse = Some(Hertz(16_000_000));
    config.rcc.sys_ck = Some(Hertz(72_000_000));
    config.rcc.pclk1 = Some(Hertz(36_000_000));
    config.rcc.pclk2 = Some(Hertz(72_000_000));
    config.rcc.pllxtpre = true;

Init fails if pllxtpre is false.
2023-05-04 22:59:52 +02:00
Marco Pastrello
1cc61dc68a Support PLLXTPRE switch.
See figure 2. Clock tree page 12 DS5319 Rev 18
https://www.st.com/resource/en/datasheet/stm32f103cb.pdf
2023-05-04 21:32:37 +02:00
ceekdee
91612b7446 Simplify SUBGHZSPI configuration. 2023-05-04 09:45:18 -05:00
goueslati
007f452927 removed hardcoded addresses in memory.x 2023-05-04 11:02:17 +01:00
Chuck Davis
91d1fff4ed
Merge branch 'embassy-rs:master' into master 2023-05-03 21:07:28 -05:00
ceekdee
629e0ea595 Handle SUBGHZSPI as async. 2023-05-03 21:05:47 -05:00
xoviat
02d6e0d14d stm32/i2s: add module and example for f4 2023-05-03 18:17:57 -05:00
goueslati
0997021a05 fixed ble table cmd buffer being constant 2023-05-03 11:11:51 +01:00
Dario Nieuwenhuis
a61701b756 stm32/usart: add OVER8 and PRESC support, update PAC 2023-05-02 19:36:00 +02:00
goueslati
371a80e1a2 whoops, plugin formatted Cargo.toml, reverting 2023-05-02 14:16:59 +01:00
goueslati
bab30a7e87 added TL Mailbox initialization for STM32WB 2023-05-02 12:16:48 +01:00
xoviat
cd88e39f5f stm32/pwm: improve dead-time api 2023-05-01 16:42:03 -05:00
Dario Nieuwenhuis
00cde67abe stm32/dma: solve overlapping impl on DmaCtrl on stm32h7 2023-05-01 23:20:51 +02:00
Dario Nieuwenhuis
96e8a7ddb9 stm32/uart: feature-gate ringbuffer out when using gpdma, not supported yet. 2023-05-01 22:43:23 +02:00
Dario Nieuwenhuis
25864ae4dc stm32/bdma: add ringbuffer support. 2023-05-01 22:42:36 +02:00
Dario Nieuwenhuis
14e0090cb1 stm32/dma: remove separate process_tcif. 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
45843034ec Actually clear idle flag 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
7757405908 Remove unused import 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
fc268df6f5 Support overflow detection for more than one ring-period 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
4ea6662e55 Do not disable dma request when idle line is detected 2023-05-01 22:42:36 +02:00
Rasmus Melchior Jacobsen
49455792cb Ring-buffered uart rx with one-period overrun detection 2023-05-01 22:42:36 +02:00
bors[bot]
855c0d1423
Merge #1376
1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat

This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-01 19:32:06 +00:00
Chuck Davis
ff6748a0d8
Merge branch 'embassy-rs:master' into master 2023-04-30 11:09:43 -05:00
bors[bot]
7646f18836
Merge #1405
1405: add IPCC peripheral for stm32wb r=xoviat a=OueslatiGhaith

Hello again,

This pull request is related to #1397 and #1401, inspired by #24, and was tested on an stm32wb55rg.

This pull request aims to add the IPCC peripheral for stm32wb microcontrollers.
I am debating whether this should be included in the public API, since the IPCC peripheral would be typically managed by the TL Mailbox, not by the app directly.

Co-authored-by: OueslatiGhaith <ghaith.oueslati@enis.tn>
2023-04-30 15:23:55 +00:00
bors[bot]
41fe718ea8
Merge #1412
1412: stm32/uart: abort on error r=Dirbaio a=xoviat

This PR aborts the DMA transfer in the event of a UART error. Otherwise, the transfer will never complete, and an error will not be returned.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-04-30 14:58:36 +00:00
xoviat
b77794c9a7 stm32/uart: abort on error 2023-04-28 21:43:03 -05:00
Chuck Davis
49bed094a3
Merge branch 'embassy-rs:master' into master 2023-04-28 13:35:22 -05:00
OueslatiGhaith
29cc661dca removed constrain method 2023-04-28 10:17:01 +01:00
OueslatiGhaith
91cddd50f6 reversed changes in Cargo.toml 2023-04-27 18:26:19 +01:00
ceekdee
9d610c6866 Remove legacy LoRa drivers. 2023-04-27 11:05:33 -05:00
OueslatiGhaith
d960bf344a fixed missing imports 2023-04-27 16:22:41 +01:00
OueslatiGhaith
3ba73b5ff4 fixed mistake with casting channel to a usize 2023-04-27 16:08:57 +01:00
OueslatiGhaith
8c733c29cc add IPCC peripheral for stm32wb 2023-04-27 16:03:22 +01:00
Ulf Lilleengen
42a8f1671d Bump versions preparing for -macros and -executor release 2023-04-27 11:54:22 +02:00
xoviat
0d82ebea29 stm32/rtc: fix datetime and add f4 test 2023-04-25 17:35:01 -05:00
ceekdee
f729d2d060 Deprecate original LoRa drivers. Update rust-lorawan releases. 2023-04-25 13:51:19 -05:00
ceekdee
02c86bca52 Add external LoRa physical layer functionality. 2023-04-21 01:20:46 -05:00
bors[bot]
41e90e22e2
Merge #1370
1370: stm32/i2c: fix races when using dma. r=Dirbaio a=xoviat

This change addresses two races:

1. It removes the `chunks_transferred` state variable that is modified inside the interrupt. Analysis of the code reveals that the only time the waker can be woken is when `chunks_transferred` is incremented. Therefore, waking is enough to signal the `poll_fn` that the `chunks_transferred` has incremented. Moving to `remaining_len` clarifies the code, since there is no need to track how many chunks are remaining.
2. It moves the start of the transfer until after the waker is registered, which could theoretically occur if the clock speed is very low, but probably never would even if this wasn't fixed.

There is another race that I noticed: between writes the waker may not yet be registered. In that case, the code would simply be stuck and the `poll_fn` would never be woken. There is no way to resolve this without broadening the scope of the analysis, and this will likely never occur. 

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-04-19 21:36:04 +00:00
xoviat
64b80c2e4d stm32/i2c: ignore wakes without interrupt 2023-04-19 16:16:44 -05:00
xoviat
e24421a393 stm32/rtc: impl. functions on trait 2023-04-18 20:38:51 -05:00
xoviat
4de4039417 stm32/rtc: build more chips 2023-04-18 20:38:28 -05:00
xoviat
f589247c1f stm32/rtc: cleanup and consolidate 2023-04-18 20:38:18 -05:00
anton smeenk
3260f6b2af stm32/spi: add new_txonly_nosck constructor, for neopixels, with an example in the stm32g0 directory. 2023-04-18 20:59:25 +02:00
Dario Nieuwenhuis
2080d8bb6d stm32/spi: add support for all word sizes.
Co-Authored-By: anton smeenk <asmeenk@planet.nl>
2023-04-18 20:56:23 +02:00
Dario Nieuwenhuis
fbd6eeb748
Merge pull request #1348 from embassy-rs/h5-spi
stm32/dma: refactor
2023-04-18 17:03:24 +02:00
Dario Nieuwenhuis
efc70debb3 stm32/dma: add double buffered mode for DMA, update DCMI. 2023-04-18 16:41:24 +02:00
Dario Nieuwenhuis
173c65b543 stm32/dma: refactor. 2023-04-18 16:37:35 +02:00
Mathias
bba8b0ded5 Missing semi-colon 2023-04-18 16:03:55 +02:00
Mathias
095f5ef279 Add MAX_ERASE_SIZE const in build script, and use it in flash-wide implementation of embedded-storage traits 2023-04-18 15:49:33 +02:00
Mathias
1c68c62ebd Implement embedded-storage traits for full flash struct 2023-04-18 13:48:37 +02:00
xoviat
f5216624bb stm32/i2c: fix races when using dma.
fixes #1341.
2023-04-17 15:24:24 -05:00
Dario Nieuwenhuis
0dfa192992 stm32/sdmmc: remove "inner" layer. 2023-04-17 19:23:18 +02:00
Dario Nieuwenhuis
e14fa11fc3 stm32/sdmmc: remove unneeded pointer casts. 2023-04-17 17:52:02 +02:00
Dario Nieuwenhuis
df7ef1d98f stm32/sdmmc: remove cfg_if. 2023-04-17 17:52:02 +02:00
bors[bot]
6acc361109
Merge #1371 #1374
1371: RTC r=Dirbaio a=xoviat

This adds RTC for most of the stm32 chips. Nearly all of the work was not done by me, but I took it the last bit by disabling the chips that weren't working. I think it would be easier to enable them in future PRs if requested.

1374: stm32: remove TIMX singleton when used on timer driver r=Dirbaio a=xoviat

After multiple ways of looking at this, this is the best solution I could think of.

Co-authored-by: Mathias <mk@blackbird.online>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-04-17 01:29:05 +00:00
xoviat
27ec29e2c5 stm32/rtc: remove unused import 2023-04-16 19:32:15 -05:00
xoviat
90c1422381 stm32/rtc: remove chrono datetime and add converters 2023-04-16 19:30:42 -05:00
xoviat
9e1ddeac86 stm32: fix defective example 2023-04-16 18:32:55 -05:00
xoviat
776e001b5b stm32: remove TIMX singleton when used on timer driver
fixes #1316.
2023-04-16 17:47:25 -05:00
xoviat
e9ede443bc stm32/rtc: disable nonworking versions 2023-04-16 11:14:17 -05:00
xoviat
8da9c07a65 stm32/rtc: disable nonworking versions 2023-04-16 11:06:05 -05:00
xoviat
bd6bb2d248 Merge branch 'embassy-stm32/rtc' of https://github.com/MathiasKoch/embassy into rtc 2023-04-16 10:06:00 -05:00
bors[bot]
1fdce6e52a
Merge #1360 #1361
1360: stm32/rcc: add i2s pll on some f4 micros r=Dirbaio a=xoviat

Adds the i2s pll on some f4 micros. 

1361: Executor: Replace unnecessary atomics in runqueue r=Dirbaio a=GrantM11235

Only the head pointer needs to be atomic. The `RunQueueItem` pointers are only loaded and stored, and never concurrently

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2023-04-15 10:38:28 +00:00
xoviat
f395ec44e8 stm32/rcc: add pllsai clock 2023-04-14 21:28:27 -05:00
Dario Nieuwenhuis
224eaaf797 stm32/sdmmc: switch to AFIT. 2023-04-15 00:58:58 +02:00
Dario Nieuwenhuis
f681b9d4e5 Remove the _todo_embedded_hal_serial impls. EH will probably not have these serial traits. 2023-04-15 00:58:58 +02:00
xoviat
650589ab3f stm32/rcc: add plli2s to Clocks and cfg directives 2023-04-14 16:30:36 -05:00
Dario Nieuwenhuis
577f060d24 Release embassy-sync v0.2.0 2023-04-13 23:40:49 +02:00
xoviat
c1d5f86871 stm32/rcc: fix warnings 2023-04-12 18:11:55 -05:00
xoviat
0289630fe4 stm32/rcc: add i2s pll on some f4 micros 2023-04-12 18:04:44 -05:00
Sebastian Goll
4863f88d02 Make Hertz constructors const
This allows them to be used in constant values.
2023-04-13 00:06:14 +02:00
Sebastian Goll
f3699e67b9 Fix typo in derivation of PLLP divisor 2023-04-12 02:07:31 +02:00
Dario Nieuwenhuis
9a677ab618 common/peripheral: do not require mut in PeripheralRef clone_unchecked. 2023-04-11 23:09:02 +02:00
Dario Nieuwenhuis
f5df567619 stm32/test: add C0 hil tests. 2023-04-11 14:16:32 +02:00
Dario Nieuwenhuis
1f25d2ba83
Merge pull request #1347 from embassy-rs/h5-spi
stm32h5: add spi support, fix DMA hang, add HIL tests.
2023-04-10 21:27:44 +02:00
Dario Nieuwenhuis
cae683cd41 stm32: update pac. 2023-04-10 21:12:48 +02:00
Glenn Dirkx
6760258ec3 fix I2C controller problems after NACK 2023-04-10 16:20:47 +02:00
Dario Nieuwenhuis
4ef8e008e8 stm32/spi: add v4/v5 support (for H5). 2023-04-10 15:25:11 +02:00
Dario Nieuwenhuis
44b7fe45e2 stm32/gpdma: fix race condition when resetting channel when done. 2023-04-10 15:11:07 +02:00
Dario Nieuwenhuis
f38899728c stm32: add h5 flavor. 2023-04-07 02:28:36 +02:00
Dario Nieuwenhuis
8469a2409c stm32/otg: add U5 support. 2023-04-07 02:28:36 +02:00
Dario Nieuwenhuis
dee1d51ad3 stm32: remove subghz feature.
It's available only on WL. if you're using a WL, you want subghz for sure.
2023-04-07 02:28:36 +02:00
bors[bot]
da8258b767
Merge #1330
1330: stm32/pwm: add complementary pwm r=Dirbaio a=xoviat

This implements complementary PWM with dead time on many supported targets. The specific dead-time programming functions are passed through directly to the user, which is a bit ugly but the best compromise I could reach for now.

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-04-06 21:33:17 +00:00
Dario Nieuwenhuis
be37eee13d Update embedded-hal crates. 2023-04-06 22:41:50 +02:00
bors[bot]
89279dcdc9
Merge #1333
1333: STM32: Adc V1 r=Dirbaio a=GrantM11235

Based on #947

Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2023-04-06 17:16:50 +00:00
Dario Nieuwenhuis
611d023829 stm32: add H5 support. 2023-04-06 18:59:37 +02:00
Dario Nieuwenhuis
9f28d80977 stm32/usb: add support for 32bit usbram. 2023-04-06 18:59:37 +02:00
Eric Yanush
8d7abeb06f Round out the async fns for can 2023-04-06 08:21:44 -06:00
Eric Yanush
9876571887 Strip out debug messages... oops 2023-04-06 08:21:44 -06:00
Eric Yanush
289762c0ef Add initial setup of async can for STM32 2023-04-06 08:21:44 -06:00
xoviat
9f1dac3f5d stm32/pwm: add complementary pwm example 2023-04-05 18:07:07 -05:00
xoviat
7677268319 stm32/pwm: cleanup and fix complementary pwm 2023-04-05 17:50:23 -05:00
Grant Miller
0ef419bee4 Change ADC1 to ADC 2023-04-05 16:52:32 -05:00
Grant Miller
92e96bd601 Fix typo 2023-04-05 16:38:06 -05:00
Grant Miller
20e7b5e296 InternalChannel 2023-04-05 16:11:21 -05:00
Grant Miller
37d8f2e512 Properly enable and reset adc 2023-04-05 15:28:42 -05:00
Grant Miller
f588105429 wip 2023-04-05 15:01:31 -05:00
Matthew W. Samsonoff
511a951246 Differentiate between read and read_internal for STM32F0 ADC
The internal channels (vbat, vref, and temperature) are not real pins and do
not have the `set_as_analog` method. They must be read using the
`read_internal` method.
2023-04-05 14:34:24 -05:00
Matthew W. Samsonoff
a0b6096610 Put ADC input pin into analog mode 2023-04-05 14:34:24 -05:00
Matthew W. Samsonoff
5d9ae3dbdb Add implementation of STM32 v1 ADC 2023-04-05 14:34:24 -05:00
Rasmus Melchior Jacobsen
95b31cf2db Remove Drop on Flash and FlashLayout and propage lifetime to region types
This allows the user to "split" the FlashRegions struct into each region
2023-04-05 10:27:13 +02:00
xoviat
991b22b6a1 stm32/pwm: add complementary pwm 2023-04-04 19:35:25 -05:00
Rasmus Melchior Jacobsen
3deb65bc87 Merge branch 'master' into flash-regions 2023-04-04 23:16:01 +02:00
bors[bot]
143105eeb6
Merge #1313
1313: (embassy-stm32): rework bufferedUart to get rid of PeripheralMutex r=Dirbaio a=MathiasKoch

New implementation is very similar to the implementation of embassy-nrf & embassy-rp. 

Also adds embedded-hal traits to bufferedUart.

**NB**: Still needs testing on actual hardware

Co-authored-by: Mathias <mk@blackbird.online>
2023-04-04 15:14:07 +00:00
Mathieu Dupont
1349dabe1a add compilation time exclusion for stm32f410 2023-04-03 17:55:05 +02:00
Mathieu Dupont
4ce1c5f27d Add MCO support for L4 and F4 families 2023-04-03 16:41:25 +02:00
Rasmus Melchior Jacobsen
bfebf7a436 Fix formatting of sector erase log 2023-04-03 08:02:43 +02:00
Dario Nieuwenhuis
94890e544e Update stm32-metapac. 2023-04-03 02:01:06 +02:00
Rasmus Melchior Jacobsen
dd88775871 Ensure that flash locking is defered to after write 2023-04-01 18:10:20 +02:00
Rasmus Melchior Jacobsen
e11eebfa57 Ensure that ranges are validated with the region size 2023-04-01 17:26:32 +02:00
Rasmus Melchior Jacobsen
268e29b153 Let the FlashRegion for region types be public 2023-04-01 16:59:21 +02:00
Mathias
472dc6b7d1 Fix interrupt handling so it is similar to before the rework, and fix examples 2023-03-31 15:57:35 +02:00
Rasmus Melchior Jacobsen
50b0fb1a37 Let get_flash_regions be public 2023-03-31 15:47:45 +02:00
Mathias
cfbe93c280 Rework bufferedUart to get rid of PeripheralMutex in a similar fashion as nrf & rp. Also adds embedded-hal traits to bufferedUart 2023-03-31 10:43:30 +02:00
Rasmus Melchior Jacobsen
f3dcb5eb22 Wrap write/erase operations in cs 2023-03-30 15:13:44 +02:00
Rasmus Melchior Jacobsen
a78e10e003 Add defmt support to new flash types 2023-03-30 09:17:14 +02:00
Rasmus Melchior Jacobsen
02caec9482 Skip unknown banks 2023-03-30 09:07:23 +02:00
Rasmus Melchior Jacobsen
760d4a72cb Ensure that embedded_storage traits are actually implemented 2023-03-30 09:05:13 +02:00
Rasmus Melchior Jacobsen
e7129371d0 Let sector computation be shared across families 2023-03-30 08:32:36 +02:00
Rasmus Melchior Jacobsen
e3c4e00be0 Align families 2023-03-30 06:01:56 +02:00
Rasmus Melchior Jacobsen
91d8afd371 Add AltFlashLayout for supported F4 chips 2023-03-30 05:27:57 +02:00
Rasmus Melchior Jacobsen
89129babf9 Merge remote-tracking branch 'upstream/master' into flash-regions 2023-03-30 04:53:07 +02:00
Rasmus Melchior Jacobsen
def576ac46 Remove FlashRegion trait and rename Settings to FlashRegion 2023-03-30 04:24:41 +02:00
Rasmus Melchior Jacobsen
ef1890e911 Remove flash operations from FlashRegion trait and move to common module 2023-03-29 15:45:18 +02:00
bors[bot]
754bb802ba
Merge #1294
1294: Add support for `QSPI` in `stm32` r=Dirbaio a=Mirror0

Implemented with help of Tomasz Grześ <tomasz.grzes@gmail.com>.

Tested only on stm32f777zi.

Co-authored-by: Mateusz Butkiewicz <mateusz@github.butkiewicz.dev>
2023-03-29 13:42:29 +00:00
Rasmus Melchior Jacobsen
68c260edeb Use stm32-metapac v2 2023-03-29 15:03:48 +02:00
Rasmus Melchior Jacobsen
fc8c83e00a Fix h7 compile error 2023-03-29 14:50:19 +02:00
Mateusz Butkiewicz
87898501a2 feat(stm32:qspi): convert some u8 to enum variants 2023-03-29 14:28:25 +02:00
Rasmus Melchior Jacobsen
a0d089536a Merge branch 'flash-regions' of https://github.com/rmja/embassy into flash-regions 2023-03-29 14:10:33 +02:00
Rasmus Melchior Jacobsen
15e1747220 Fix build of not implemented family 2023-03-29 14:10:16 +02:00
Rasmus Melchior Jacobsen
0bbc3a3d81
Merge branch 'master' into flash-regions 2023-03-29 13:59:17 +02:00
Rasmus Melchior Jacobsen
5a12fd6c75 Add unimplemented family section 2023-03-29 13:57:33 +02:00
Rasmus Melchior Jacobsen
b7dfc8de10 Let flash module be conditionally included 2023-03-29 13:52:52 +02:00
Rasmus Melchior Jacobsen
ddbd509865 Move as much logic from families to shared module as possible 2023-03-29 13:37:45 +02:00
Rasmus Melchior Jacobsen
69944675a3 Expose get_sector in favor of is_eraseable_range 2023-03-29 12:49:13 +02:00
Rasmus Melchior Jacobsen
4ee3d15519 Keep peripheral lifetime when calling into_regions() 2023-03-29 12:10:24 +02:00
Rasmus Melchior Jacobsen
6806bb9692 Expose flash region settings as an array 2023-03-29 11:52:18 +02:00
Rasmus Melchior Jacobsen
d6ce1c4325 Support running tests in embassy-stm32 and move impl from common back to stm32 2023-03-29 11:31:45 +02:00
bors[bot]
7a841b58d1
Merge #1307
1307: (embassy-stm32): add embedded-io blocking Read + Write for BufferedUart r=MathiasKoch a=MathiasKoch



Co-authored-by: Mathias <mk@blackbird.online>
2023-03-28 12:35:07 +00:00
Mathias
14f6bc88ea Remove unnecessary lifetime 2023-03-28 14:34:36 +02:00
Mathias
2d7f35cf57 Add embedded-io blocking Read + Write for BufferedUart 2023-03-28 14:28:44 +02:00
Mateusz Butkiewicz
6a802c4708 feat(stm32:qspi): add support for QSPI in stm32
Implemented with help of Tomasz Grześ <tomasz.grzes@gmail.com>.
2023-03-27 13:20:00 +02:00
Dario Nieuwenhuis
a33774ec51 Update stm32-metapac 2023-03-27 12:36:31 +02:00
Rasmus Melchior Jacobsen
e9a5b31fa8 Implement drop for FlashRegions 2023-03-25 17:00:52 +01:00
Rasmus Melchior Jacobsen
e8fc7a66a3 Ensure flash module and FlashRegion trait is always defined 2023-03-25 16:32:32 +01:00
Rasmus Melchior Jacobsen
bc69eb596e Add is_eraseable_range and split write into consecutive parts 2023-03-25 16:04:45 +01:00
Rasmus Melchior Jacobsen
73ccc04231 Change region type name 2023-03-25 13:47:28 +01:00
Rasmus Melchior Jacobsen
47d5f127bb Align L family 2023-03-25 13:30:24 +01:00
Rasmus Melchior Jacobsen
47e07584ca Align H7 family 2023-03-25 13:03:00 +01:00
Rasmus Melchior Jacobsen
c848bd9c9c Align with removal of MemoryRegionKind::Otp 2023-03-25 13:02:42 +01:00
Rasmus Melchior Jacobsen
a8567f0617 Align F7 family 2023-03-25 06:26:00 +01:00
Rasmus Melchior Jacobsen
7edd72f8f5 Align F3 family 2023-03-25 06:07:57 +01:00
Rasmus Melchior Jacobsen
6c73b23f38 Align F4 family 2023-03-25 05:59:40 +01:00
Rasmus Melchior Jacobsen
6b44027eab Add FlashRegion trait and implement embedded_storage traits for each region 2023-03-25 05:58:40 +01:00
Rasmus Melchior Jacobsen
cccceb88f2 Generate flash regions during build 2023-03-25 05:57:15 +01:00
Dario Nieuwenhuis
0b49b588a2 stm32: use stm32-metapac from crates.io, remove stm32-data submodule. 2023-03-20 02:38:12 +01:00
Eric Yanush
13f0c64a8c Fix APB clock calculation for several STM32 families 2023-03-16 21:21:39 -06:00
Dario Nieuwenhuis
43462947ed stm32: remove unused embedded-storage-async. 2023-03-14 17:27:40 +01:00
Davide Della Giustina
c0e40b887b
Apply fix 2023-03-01 20:57:13 +00:00
Dario Nieuwenhuis
351e4407ef
Merge pull request #1252 from pattop/stm32_spi_fifo_fix
stm32/spi: fix occasional data corruption
2023-03-01 03:08:05 +01:00
Patrick Oppenlander
aabc275186 stm32/spi: fix occasional data corruption
Need to clear the rx fifo before enabling rx dma.
2023-03-01 12:24:22 +11:00
Davide Della Giustina
3c601bf8d2
PacketQueue::init() does not need to be unsafe 2023-02-28 18:04:43 +00:00
Davide Della Giustina
485bb76e46
Implemented suggestions from @Dirbaio 2023-02-28 17:39:02 +00:00
Davide Della Giustina
c1e93c0904
PacketQueue::new() uses ::init() when in nightly 2023-02-28 14:34:26 +00:00
Davide Della Giustina
90f2939bf6
Added PacketQueue::init() 2023-02-28 14:22:54 +00:00
Grant Miller
7be4337de9 Add #[must_use] to all futures 2023-02-24 13:01:41 -06:00
bors[bot]
3255e0a172
Merge #1228
1228: stm32/sdmmc: Implement proper clock configuration r=chemicstry a=chemicstry

This implements proper clock configuration for sdmmc based on chip family, because `RccPeripheral::frequency()` is almost always incorrect. This can't be fixed in PAC, because sdmmc uses two clock domains, one for memory bus and one for sd card. `RccPeripheral::frequency()` usually returns the memory bus clock, but SDIO clock calculations need sd card domain clock. Moreover, chips have multiple clock source selection bits, which makes this even more complicated. I'm not sure if it's worth implementing all this logic in `RccPeripheral::frequency()` instead of cfg's in sdmmc.

Some chips (Lx, U5, H7) require RCC updates to expose required clocks. I didn't want to mash everything in a single PR so left a TODO comment. I also left a `T::frequency()` fallback, which seemed to work in H7 case even though the clock is most certainly incorrect.

In addition, added support for clock divider bypass for sdmmc_v1, which allows reaching a maximum clock of 48 MHz. The peripheral theoretically supports up to 50 MHz, but for that ST recommends setting pll48 frequency to 50 MHz 🤔

Co-authored-by: chemicstry <chemicstry@gmail.com>
2023-02-23 16:22:31 +00:00
chemicstry
73ef85b765 stm32/sdmmc: Fix compile errors 2023-02-23 18:00:55 +02:00
bors[bot]
f0f92909c1
Merge #1227
1227: stm32/dma: fix spurious transfer complete interrupts r=Dirbaio a=pattop

DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.

Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.


Co-authored-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>
2023-02-23 15:44:43 +00:00
chemicstry
896764bb85 stm32/sdmmc: Refactor TypeId into a macro 2023-02-23 17:38:52 +02:00
chemicstry
42462681bd stm32/sdmmc: Implement proper clock configuration 2023-02-23 16:57:21 +02:00
Patrick Oppenlander
4e884ee2d2 stm32/dma: fix spurious transfer complete interrupts
DMA interrupts must be acknowledged by writing to the DMA_{L,H}IFCR
register.

Writing to the CR register is unnecessary as the channel (EN bit) is
disabled by hardware on completion of the transfer.
2023-02-23 10:12:48 +11:00
chemicstry
a53f525f51 stm32/sdmmc: Fix SDIOv1 writes 2023-02-18 01:37:06 +02:00
Mathias
5e74926907 feature-gate variants without vals defined 2023-02-13 15:46:49 +01:00
Mathias
218b44652c Rebase on master 2023-02-13 14:55:15 +01:00
Dario Nieuwenhuis
363054de98 stm32: doc all chips. 2023-02-13 03:02:12 +01:00
Dario Nieuwenhuis
1e36c91bf8 stm32: fix fmc-related build failures on some F4's 2023-02-13 02:22:06 +01:00
Christian Enderle
d21643c060 fix "prescaler none" which incorrectly set "prescaler divided by 3" 2023-02-12 11:36:57 +01:00
Lucas Granberg
2b6654541d rustfmt 2023-02-09 13:01:44 +02:00
Lucas Granberg
43d018b67f Use rng_v2 cfg instead of chip specific for seed error recover hack 2023-02-09 12:44:20 +02:00
Lucas Granberg
bab4277a86 hack for STM32WL, rcc reset in case of seed error
The STM32WL series has a more complicated rng device that gets stuck
when there is a seed error.
2023-02-08 17:57:37 +02:00
Lucas Granberg
da6b1e8399 Reset rng in case of clock or seed error 2023-02-08 17:52:49 +02:00
bors[bot]
4a224efe75
Merge #1200
1200: feat(stm32): Add 16 data bit fmc ctor r=Dirbaio a=rmja

This has been validated with the Is42s16400j sdram on stm32f429.

Co-authored-by: Rasmus Melchior Jacobsen <rmja@laesoe.org>
2023-02-07 22:24:15 +00:00
bors[bot]
c4a2c62096
Merge #1199
1199: STM32 SPI: Set clk-pin pull-up/-down to match spi clock polarity r=Dirbaio a=jr-oss

Fixes #1094 

There are some proposed solutions in #1094 

> Keep the DMA transaction open across calls to read/write
        This may be problematic if the user changes bus settings between calls, and also the reference manual says the chip should not be placed into low power mode while SPI is enabled

As already described, this is problematic and against reference manual recommendation

>    Set the CLK (and maybe MOSI) pins as pull-down on setup (or pull-up, depending on config - and this would need to be updated if the user modified the config)
        This is less good than driving the pin to the correct value, but may be better than nothing

That is also my preferred solution. See below citation from reference manual.

>    Document this and require users fix it themselves (add a pull-up/down resistor - or configure the pins as pull-up/pull-down before passing them into SPI setup)

Setting internal pull-up/-down won't work, because `sck.set_as_af()` will change the gpio pull mode to none: https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/gpio.rs#L552-L555

>    Dig around in the reference manual and determine if there is a better way to start/stop a DMA transaction while keeping active control of the clock the whole time

I haven't found a better way

------
From ST reference manual RM0394 (L4) 
(Same note in RM0399 (H7) / RM0038 (L1) / RM0316 /F3)):

    40.4.6
    Communication formats
    ...
    The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
    pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).


Co-authored-by: Ralf <jr-oss@gmx.net>
2023-02-07 22:06:25 +00:00
Rasmus Melchior Jacobsen
7b11e339bd feat(fmc): Add 16 data bit ctor 2023-02-07 16:06:59 +01:00
Rasmus Melchior Jacobsen
1b6aae9dde Also exclude fsmc_v1x3 2023-02-07 15:06:16 +01:00
Rasmus Melchior Jacobsen
494a76a0f1 React to updated fsmc versions 2023-02-07 14:14:47 +01:00
Rasmus Melchior Jacobsen
218f8e0490 fix(stm32): Align FMC with new versions from stm32-data 2023-02-07 12:17:37 +01:00
bors[bot]
c8a7b74bc2
Merge #1192 #1193
1192: stm32/usart: implement stop_bits configuration r=Dirbaio a=pattop



1193: stm32/usart: fix LPUART clock multiplier r=Dirbaio a=pattop

According to RM0351 Rev 9 (L4) and RM0399 Rev 3 (H7):

baud = (256 * clock) / LPUARTDIV


Co-authored-by: Patrick Oppenlander <patrick.oppenlander@gmail.com>
2023-02-06 13:39:37 +00:00
Ralf
e3174d7a99 STM32 SPI: Set clk-pin pull-up/-down to match spi clock polarity
RM0394:

    40.4.6
    Communication formats
    ...
    The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
    pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
2023-02-06 13:23:35 +01:00
Patrick Oppenlander
fda36fd81b stm32/usart: fix LPUART clock multiplier
According to RM0351 Rev 9 (L4) and RM0399 Rev 3 (H7):

baud = (256 * clock) / LPUARTDIV
2023-02-06 11:22:41 +11:00
Patrick Oppenlander
64ebb9b7fe stm32/usart: implement stop_bits configuration 2023-02-06 09:44:15 +11:00
Josh Mcguigan
0bb6000e5c stm32 gpio implement degrade to AnyPin 2023-02-02 21:42:42 -08:00
Dario Nieuwenhuis
ca10fe7135 usb: docs 2023-01-31 22:27:19 +01:00
Christian Enderle
5e3c33b777 Fix rcc prescaler for wb55 HCLK1
- fix prescaler not divided which incorrectly set prescaler divided by 3
2023-01-21 14:39:25 +01:00
Dario Nieuwenhuis
0412d1922c fix embedded-sdmmc integration.
- Rename feature to `embedded-sdmmc`.
- Move embedded-sdmmc fork repo to the embassy-rs org.
- Remove unused features in the fork
- Fix impl in embassy-stm32
- Add to CI so it doesn't break again.
2023-01-21 00:32:34 +01:00
Dario Nieuwenhuis
f604153f05 stm32/rcc: print actual freqs on boot. 2023-01-20 16:31:04 +01:00
bors[bot]
f0ae1f9133
Merge #1159
1159: stm32 usb otg bug fixes r=Dirbaio a=chemicstry

This fixes a couple of usb otg bugs that surfaced with `usb_ethernet` example from nrf:
- Properly implemented `Endpoint::wait_enabled()`
- Return `EndpointError::Disabled` when neccessary in `Endpoint::write()`


Co-authored-by: chemicstry <chemicstry@gmail.com>
2023-01-18 11:30:44 +00:00
huntc
6ab4ecaf83 Stop sampling when exiting the Saadc methods
Prior to this commit, the onDrop function was being dropped immediately and not on exiting the Saadc sampling methods.
2023-01-18 14:51:46 +11:00
chemicstry
b1203bf036 stm32/usb_otg: fix core formatter 2023-01-18 03:06:32 +02:00
chemicstry
f07e59b24a stm32/usb_otg: prevent writes on disabled endpoint 2023-01-18 02:31:28 +02:00
chemicstry
d2f2b451d0 stm32/usb_otg: implement endpoint wait_enabled 2023-01-18 02:29:49 +02:00
Dario Nieuwenhuis
2a349afea7 stm32: add stm32c0 support. 2023-01-17 21:28:16 +01:00
bors[bot]
aea5a0fd96
Merge #1140
1140: feat(stm32): Let uart implement embedded-io Write trait r=Dirbaio a=rmja



Co-authored-by: Rasmus Melchior Jacobsen <rmja@laesoe.org>
2023-01-14 19:45:28 +00:00
Rasmus Melchior Jacobsen
16590732f8 Update mod.rs 2023-01-14 07:13:29 +01:00
Rasmus Melchior Jacobsen
816b214403 Only implement Write 2023-01-14 07:12:43 +01:00
Dario Nieuwenhuis
041531c829 stm32/rcc: fix u5 pll, add hsi48. 2023-01-11 17:57:22 +01:00
chemicstry
0feecd5cde stm32: add USB OTG support.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-01-11 17:56:47 +01:00
Dario Nieuwenhuis
065a0a1ee7 Update stm32-data. 2023-01-11 17:51:30 +01:00
chemicstry
ce842fe28c Refactor embassy-usb address handling to allow reordering of status resoponse 2023-01-11 17:47:12 +01:00
Rasmus Melchior Jacobsen
4c4b47f78a feat(stm32): Add embedded-io traits for UartRx and UartTx 2023-01-06 14:24:29 +01:00
Rasmus Melchior Jacobsen
5aa59e9737 feat(stm32): Let uart implement embedded-io Read/Write 2023-01-04 12:57:19 +01:00
Dario Nieuwenhuis
1f033d509a net: split driver trait to a separate crate. 2022-12-26 04:49:08 +01:00
Dario Nieuwenhuis
10c9cc31b1 Remove unnecessary use of atomic-polyfill.
Only use it when CAS is actually needed.
2022-12-23 20:46:49 +01:00
Dario Nieuwenhuis
cd9a65ba39 stm32/usb: use separate irq flags.
- Fixes race condition that could cause losing irqs (because `if flags != 0` was clearing all)
- Doesn't need CAS, which is nice for thumbv6.
2022-12-23 20:45:51 +01:00
Rasmus Melchior Jacobsen
47a0769fc2 Let repeated clock byte be singular pointer and not array pointer 2022-12-23 15:49:22 +01:00
Rasmus Melchior Jacobsen
e9a2c4a9e3 Let start_write_repeated accept pointer instead of slice 2022-12-23 15:40:09 +01:00
Rasmus Melchior Jacobsen
662bb5797f fix(stm32): Ensure that gpio speed is VeryHigh for all spi versions
This fixes #1095
2022-12-23 09:34:42 +01:00
Rasmus Melchior Jacobsen
2457fcaa35 fix(stm32): Align with updated dma::write_repeated signature 2022-12-23 09:33:34 +01:00
Rasmus Melchior Jacobsen
da9ee83756 fix(stm32): Fix write buffer lifetime for repeated writes 2022-12-23 09:32:18 +01:00
Dario Nieuwenhuis
5eae295c8a stm32: rename feature net to embassy-net.
The eth code is always built and available, but has no own API (other
than the embassy-net Device impl) to rx/tx packets. We could add this
API in the future, so the feature only means "embassy-net support".
2022-12-13 16:43:25 +01:00
Dario Nieuwenhuis
3005ee0178 stm32/eth_v2: update to new embassy-net trait, remove PeripheralMutex. 2022-12-13 16:43:25 +01:00
Dario Nieuwenhuis
8f30652109 stm32/eth_v1: update to new embassy-net trait, remove PeripheralMutex. 2022-12-13 16:43:25 +01:00
Vincent Stakenburg
236d104844 embassy-stm32: add rs485 driver enable to uart 2022-12-09 14:26:09 +01:00
chemicstry
7bda01ec24 Fix comment 2022-12-06 23:31:58 +02:00
chemicstry
ef2b83cc03 Reset sdmmc clock on card init 2022-12-06 16:36:07 +02:00
bors[bot]
9f854110f2
Merge #1082 #1083
1082: stm32: Add basic support for DMA priority settings r=lulf a=matoushybl

This adds very basic support for specifying priority for DMA interrupts. Unfortunately, the patch now doesn't allow for specifying different priorities for DMA1/DMA2, or BDMA1/BDMA2, which I didn't know how to support.

1083: stm32: Fix H7 unaligned erase r=lulf a=matoushybl

This PR simplifies erasing sectors on the H7, which was buggy.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-12-01 13:49:59 +00:00
bors[bot]
d8ea297d6a
Merge #1088
1088: stm32: Enable fifo for buffered uart r=lulf a=matoushybl

This PR enables fifo for buffered uart where it is available. This should hopfully get rid of some overrun errors. I tried it in my application where it worked, but more intensive testing is probably required.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-12-01 13:34:52 +00:00
Matous Hybl
e1d7d8d841 stm32: Enable fifo for buffered uart 2022-11-30 22:17:51 +01:00
Guillaume MICHEL
e0ea5dfdb2 embassy-stm32: Allow SPI with DMA to implement blocking embbeded-hal traits 2022-11-30 09:26:16 +01:00
Matous Hybl
4cc0463123 stm32: Add basic support for DMA priority settings 2022-11-28 21:22:39 +01:00
Matous Hybl
2a35a09444 stm32: Fix H7 unaligned erase 2022-11-28 21:15:24 +01:00
Gabriel Smith
3ca14ba4e9 usb-driver: Remove unncessary lifetime 2022-11-27 16:28:24 -05:00
Dario Nieuwenhuis
1e2fb0459d Switch to async-fn-in-trait 2022-11-25 21:02:06 +01:00
Jaxter Kim
551b54ddcb stm32g0: Fix ADC for channels above 14 2022-11-15 12:56:47 +01:00
bors[bot]
d05979c708
Merge #1052 #1053
1052: stm32: Fix watchdog division by zero for 256 prescaler, add watchdog … r=lulf a=matoushybl

…example for H7

The problem is that `2u8.powi(8) == 0`, which causes division by zero.

1053: Disable MMC interrupts r=lulf a=matoushybl

MMC interrupts can cause firmware hangup - refer to: https://github.com/stm32-rs/stm32h7xx-hal/issues/275 for more information

Fixes #594 

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-11-11 08:04:16 +00:00
Matous Hybl
99682d313b Disable MMC interrupts
MMC interrupts can cause firmware hangup - refer to: https://github.com/stm32-rs/stm32h7xx-hal/issues/275 for more information
2022-11-10 17:21:42 +01:00
Matous Hybl
cbc97758e3 stm32: Fix watchdog division by zero for 256 prescaler, add watchdog example for H7 2022-11-10 15:56:28 +01:00
Guillaume MICHEL
1365ce6ab8 embassy-stm32: Fix bug when Uart::read future is dropped and DMA request was not stopped
fixes issue #1045

regression was introduced with PR #1031
2022-11-07 17:46:32 +01:00
bors[bot]
1f246d0e37
Merge #1034
1034: stm32/usart: Fix bug where USART idle flag could end a `read` prematuraly r=Dirbaio a=guillaume-michel

on STM32, when setting USART `detect_previous_overrun = true`, the idle flag is not cleared and could result in premature end of the `read` method.

This PR fixes that.

Co-authored-by: Guillaume MICHEL <guillaume@squaremind.io>
2022-10-28 11:22:53 +00:00
Guillaume MICHEL
49e1091309 embassy-stm32: Fix bug where USART idle flag could end a read prematuraly 2022-10-28 10:49:59 +02:00
Guillaume MICHEL
79b49c6fae embassy-stm32: remove duplicated code for USART general configuration 2022-10-28 09:32:05 +02:00
Guillaume MICHEL
f053bf742c embassy-stm32: Add support for hardware flow control for BufferedUart 2022-10-28 09:04:36 +02:00
Guillaume MICHEL
9423987ac5 embassy-stm32: Add hardware flow control constructor for UartRx and UartTx 2022-10-28 09:04:36 +02:00
Grant Miller
171b764d82 Refactor: Use PeripheralRef 2022-10-26 18:36:04 -05:00
Grant Miller
08c8022583 Refactor: Reorder _version cfgs 2022-10-26 18:04:52 -05:00
Grant Miller
4f2dcca34b Refactor: Fix v4 RccPeripheral bounds 2022-10-26 17:59:44 -05:00
Grant Miller
9c30d565b9 Refactor: Factor out Adc struct declaration 2022-10-26 17:51:12 -05:00
Grant Miller
f363f6ce92 Refactor: Don't return references to pointers 2022-10-26 17:35:06 -05:00
Grant Miller
6bf24b4d1a Refactor: Remove unused Common trait 2022-10-26 17:35:01 -05:00
Grant Miller
88bbc238b7 Set resolution directly 2022-10-26 17:07:58 -05:00
Grant Miller
2cfe2439c9 Refactor: Impl From for SampleTime and Resolution 2022-10-26 17:07:58 -05:00
Grant Miller
7b38b95e10 Refactor: Factor out Resolution 2022-10-26 17:07:58 -05:00
Grant Miller
5142674786 Fix pre-existing SampleTime typos 2022-10-26 17:07:50 -05:00
Grant Miller
a5b1d2237f Refactor: Factor out SampleTime 2022-10-26 17:06:44 -05:00
bors[bot]
7f499f3edc
Merge #1024
1024: stm32/adc: Remove voltage and temperature conversions r=Dirbaio a=GrantM11235

The current conversion utilities are confusing and a bit of a footgun. (Two out of the three examples got it wrong! They didn't measure vref at all, so all the conversions are completely wrong if vcca isn't 3.3v)

I think we should eventually have some sort of conversion utilities in the HAL, but for now I think it is best to just remove it and let the users do their own math.

cc `@chemicstry` 

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-10-26 19:44:06 +00:00
bors[bot]
01e23bf9dd
Merge #1025
1025: Implement I2C timeouts, second attempt r=Dirbaio a=chemicstry

This is an alterrnative to #1022 as discussed there.

Timeouts are implemented using suggested `check_timeout: impl Fn() -> Result<(), Error>` function, which does not depend on `embassy-time` by default and is a noop for regular I2C.

This also adds `time` feature like in `embassy-nrf` to enable `embassy-time` dependencies. While at it, I also gated some other peripherals that depend on `embassy-time`, notably `usb` and (partially) `subghz`.

`TimeoutI2c` is currently only implemented for i2cv1, because i2cv2 has additional complications:
- Async methods still use a lot of busy waiting code in between DMA transfers, so simple `with_timeout()` will not work and it will have to use both types of timeouts. It could probably be rewritten to replace busy waits with IRQs, but that's outside the scope of this PR.
- I2C definition `I2c<'d, T, TXDMA, RXDMA>` is different from i2cv1 `I2c<'d, T>` making it hard to share single `TimeoutI2c` wrapper. A couple of options here:
  - Duplicate `TimeoutI2c` code
  - Add dummy `TXDMA`, `RXDMA` types to i2cv1 considering that in the future it should also support DMA

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-10-26 19:34:43 +00:00
bors[bot]
e5097a8866
Merge #959
959: Generic, executor-agnostic queue implementation r=ivmarkov a=ivmarkov

Hopefully relatively well documented.

Implementation relies on a fixed-size `SortedLinkedList` from `heapless`. (By default, for up to 128 timer schedules, but we can lower this number to - say - 64.)

As discussed earlier, on queue overflow, the `WakerRegistration` approach is utilized, whereas the waker that is ordered first in the queue is awoken to make room for the incoming one (which might be the waker that would be awoken after all!). Wakers are compared with `Waker::will_wake`, so the queue should actually not fill up that easily, if at all.

I've left provisions for the user to manually instantiate the queue using a dedicated macro - `generic_queue!` so that users willing to adjust the queue size, or users (like me) who have to use the queue in a complex "on-top-of-RTOS-but-the-timer-driver-calling-back-from-ISR" scenario can customize the mutex that protects the queue.

The one thing I'm not completely happy with is the need to call `{ embassy_time::queue::initialize() }` early on before any futures using embassy-time are polled, which is currently on the shoulders of the user. I'm open to any ideas where we can get rid of this and do it on the first call to `_embassy_time_schedule_wake`, without introducing very complex combinations of critical sections, atomics and whatnot.




Co-authored-by: ivmarkov <ivan.markov@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-10-26 19:14:12 +00:00
Guillaume MICHEL
9cac649fcf stm32: Add support for read_until_idle on UART 2022-10-26 19:06:18 +02:00
Dario Nieuwenhuis
eeb072d9cb Update Rust nightly. 2022-10-26 16:47:29 +02:00
Mathias
66611a80ca Introduce shared new_inner for uart instantiation 2022-10-26 11:51:37 +02:00
Mathias
d1eee52625 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/uart-flowcontrol 2022-10-26 11:47:00 +02:00
chemicstry
52c03cf0a4 Add more docs 2022-10-24 22:48:40 +03:00
chemicstry
ac61e0ee9f fmt 2022-10-24 22:39:13 +03:00
chemicstry
33f75419e5 Unify i2cv1 definition with i2cv2 2022-10-24 22:34:10 +03:00
chemicstry
6062978d58 Remove weird async timeouts 2022-10-24 22:22:20 +03:00
chemicstry
ca8afacfd0 Implement TimeoutI2c for i2cv2 2022-10-24 22:11:15 +03:00
chemicstry
9ad7e85288 Merge branch 'i2c_timeout2_v2' into i2c_timeout2 2022-10-24 21:50:29 +03:00
chemicstry
9b209ffe1c Add docs 2022-10-24 12:39:47 +03:00
chemicstry
5f02bee388 Gate TimeoutI2c behind i2cv1 2022-10-24 12:34:55 +03:00
chemicstry
1bed02296c i2cv2 timeouts 2022-10-24 12:33:17 +03:00
Grant Miller
545cc9326b stm32/adc: Remove voltage and temperature conversions 2022-10-24 04:00:29 -05:00
chemicstry
d99841fea9 Implement time feature 2022-10-24 11:38:15 +03:00
ivmarkov
e3cf4255c6 Help compiler with type inference 2022-10-24 11:31:54 +03:00
chemicstry
4ce4131f8b Implement i2cv1 timeout 2022-10-24 11:30:04 +03:00
ivmarkov
f78c706b89 Address review feedback 2022-10-24 11:10:59 +03:00
ivmarkov
4d5550070f Change time Driver contract to never fire the alarm synchronously 2022-10-24 09:17:43 +03:00
bors[bot]
d9c773f475
Merge #1014
1014: Add memory barriers to H7 flash driver to mitigate PGSERR errors r=lulf a=matoushybl

The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.

Without the barrier, the PG bit is not set, when the writes are being done, resulting in an error.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-10-19 07:29:12 +00:00
Matous Hybl
9d2641f2f5 Enable defmt in embassy-hal-common 2022-10-18 22:48:43 +02:00
Matous Hybl
6c5d81ada5 Add memory barriers to H7 flash driver to mitigate PGSERR errors
The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.
2022-10-18 22:42:02 +02:00
Mathias
86113e199f Remove unused feature gate 2022-10-11 10:35:43 +02:00
Mathias
9223b67306 Fix RTC for v2l0 & v2l1 2022-10-11 10:28:28 +02:00
Mathias
aff265a7f5 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/rtc 2022-10-11 09:19:55 +02:00
Mathias
79cee74151 Fix stm32wl55jc-cm4 RTC 2022-10-11 09:19:47 +02:00
bors[bot]
ef533e6df4
Merge #1004
1004: Fix internal channels for adc v2 r=lulf a=chemicstry

Internal channel reading was broken on adc_v2, because `Adc::read()` requires gpio pin trait, which was not implemented by `VrefInt`, `Temperature`, `Vbat`. The required configuration bits `tsvrefe`, `vbate` were not enabled either. This PR makes it a bit closer to how adc_v4 works.

While at it, I also changed adc_v2 to use `RccPeripheral` instead of permanently enabling all ADCs.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-10-10 06:28:41 +00:00
chemicstry
322cfafed3 Fix adc_v4 compilation 2022-10-07 14:53:03 +03:00
chemicstry
df7174ecb0 Fix internal channel reading on adc_v2 2022-10-07 14:31:55 +03:00
chrysn
6718ca3a94 all Cargo.toml: Add license to all crate Cargo.toml files
Closes: https://github.com/embassy-rs/embassy/issues/1002
2022-10-07 12:41:56 +02:00
chemicstry
9dca368c3d Use RccPeripheral for adc_v2 2022-10-07 13:29:56 +03:00
bors[bot]
aabc02506b
Merge #992
992: (embassy-stm32): remove flash lock/unlock public API from stm32 flash r=lulf a=MathiasKoch

Instead, perform the unlocking and locking automatically on erase and write operations.

This makes the `embedded-storage` abstraction actually useable in libraries, while still keeping the flash peripheral locked the majority of the time.

Co-authored-by: Mathias <mk@blackbird.online>
2022-09-30 11:32:27 +00:00
Mathias
62c0b18f10 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/rtc 2022-09-30 06:15:12 +02:00
Mathias
a283c47557 Implement embedded-hal-nb for uart 2022-09-30 06:04:19 +02:00
Mathias
a7fdeac560 Remove flash lock/unlock public API from stm32 flash, and perform the unlocking and locking automatically on erase and write operations 2022-09-30 06:00:46 +02:00
Mathias
38faae26e5 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/uart-flowcontrol 2022-09-29 12:58:38 +02:00
Mathias
a77e2c3512 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/uart-eh1 2022-09-29 12:58:01 +02:00
Ulf Lilleengen
72c2e985bb Update embedded-hal versions and explicitly pin 2022-09-29 11:27:46 +02:00
Mathias
f9c62d4f1d Add flowcontrol to UART 2022-09-29 09:12:17 +02:00
Mathias
dc90006982 Remove code duplication on nb_read 2022-09-29 07:58:11 +02:00
Mathias
a83560c6b1 Implement RTC peripheral for all stm32 families with rtc 2022-09-29 07:49:32 +02:00
Mathias
823bd714fb Add E-H1 uart blocking & nb implementation 2022-09-28 05:19:43 +02:00
Dario Nieuwenhuis
17d8d11f73 usb: make HALs depend only on embassy-usb-driver. 2022-09-27 13:16:49 +02:00
Guillaume MICHEL
daf2744716 Rework STM32 BufferedUart internals so we can split into Rx and Tx like embassy-nrf 2022-09-26 15:32:29 +02:00
Dario Nieuwenhuis
7f7c14b7bc usb: split driver trait to separate crate. 2022-09-26 12:29:27 +02:00
bors[bot]
a9efbf18c6
Merge #960
960: Add non blocking Bxcan constructor r=Dirbaio a=andyblarblar

This PR adds a non-blocking constructor to the Bxcan Can wrapper struct. This allows for the creation of the Can periferal without blocking for a sync with the Can bus.

Co-authored-by: Andrew Ealovega <Andrew@Ealovega.dev>
2022-09-26 09:39:55 +00:00
Dario Nieuwenhuis
10d1ad2343 Replace futures::future::join -> embassy_futures::join::join. 2022-09-22 16:48:35 +02:00
Dario Nieuwenhuis
a0487380da Replace futures::future::poll_fn -> core::future::poll_fn. 2022-09-22 16:42:49 +02:00
Dario Nieuwenhuis
897b72c872 Update Rust nightly.
Removes feature(generic_associated_types)
2022-09-22 16:38:14 +02:00
Andrew Ealovega
5914d80968 Add non blocking Bxcan constructor.
Signed-off-by: Andrew Ealovega <Andrew@Ealovega.dev>
2022-09-21 22:29:57 -04:00
Vincent Stakenburg
c4d5c047d7 make State::new() const, consistent with others 2022-09-15 12:34:17 +02:00
bors[bot]
22c32b5d5c
Merge #939
939: time: add more tick rates, use 1mhz as default. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-09-04 22:13:34 +00:00
bors[bot]
6264fe39a5
Merge #839
839: Misc LoRaWAN improvements r=lulf a=timokroeger

Trying too get `embassy-lora` running on a [LoRa-E5 Dev Board](https://wiki.seeedstudio.com/LoRa_E5_Dev_Board/).
I can see the join message arriving in the The Things Network console but the device does not receive the accept message yet.
Opening this PR anyway because I think there are some nice things to decouple the lora crate from the nucleo board.

`@lulf` Could you test if this PR breaks your LoRa setup? Marking as draft for the time being.

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-09-04 07:17:23 +00:00
Dario Nieuwenhuis
5327b9c289 time: add more tick rates, use 1mhz as default. 2022-09-02 00:59:34 +02:00
Dario Nieuwenhuis
8ba421f324 Do not use cfg_if for embedded-hal-async feature gates.
Old code used `cfg_if!` because rustc still parses code inside disabled cfg's, and Rust stable at that time couldn't parse the new GAT where-clause location. This is not the case anymore.
2022-08-31 03:11:21 +02:00
Timo Kröger
308ca4b8e3 Use pub(crate) visibility for internal SPI
SubGhz provides a public interface for the radio connected to internal SPI
`#[allow(dead_code)]` is required for CI to succeed
2022-08-26 15:44:58 +02:00
Timo Kröger
84240d49ea stm32wl: Fix RCC
* `MSIRGSEL = 1` was required for MSI accept the updated MSI range
* Reorder enable and clock switching to properly handle the jump from
the default 4MHz MSI to a higher MSI freuquency
2022-08-26 15:44:58 +02:00
Timo Kröger
61c666212f stm32wl: Do not require external SPI pins for SUBGHZ
For the Seeed Studio Lora-E5 those pins conflict with the radio frontend control GPIOS (PA4 and PA5).
2022-08-26 15:42:25 +02:00
Dario Nieuwenhuis
21072bee48 split embassy-util into embassy-futures, embassy-sync. 2022-08-22 22:18:13 +02:00
Vincent Stakenburg
51359e7d24 fix lpuart implementation when there isn't one present 2022-08-19 15:27:11 +02:00
Vincent Stakenburg
a833e02363 implement support for LPUART 2022-08-19 12:05:19 +02:00
Dario Nieuwenhuis
5daa173ce4 Split embassy-time from embassy-executor. 2022-08-18 01:22:30 +02:00
Dario Nieuwenhuis
fc6e1e06b3 Remove HAL initialization from #[embassy::main] macro. 2022-08-17 22:16:46 +02:00
Dario Nieuwenhuis
67edea4168 Update to critical-section 1.0, atomic-polyfill 1.0 2022-08-17 19:01:56 +02:00
Dario Nieuwenhuis
2649f13dc7 stm32/rcc: fix unnecessary parentheses 2022-08-17 15:03:23 +02:00
Dario Nieuwenhuis
72cd015c1a stm32/sdmmc: remove cast no longer allowed on latest nightly due to nonexhaustive enum. 2022-08-17 14:44:18 +02:00
chemicstry
936473b68a Make sda/scl pullups separate as in nRF HAL 2022-08-10 12:36:15 +03:00
chemicstry
6498324b58 Implement I2C pullup configuration 2022-08-09 22:13:35 +03:00
chemicstry
206b7fd8ed Use RccPeripheral for DAC and add a hackfix for H7 2022-08-04 03:31:47 +03:00
chemicstry
5f01e56728 Merge v1, v2 DAC and update register definitions 2022-08-04 03:02:57 +03:00
Dario Nieuwenhuis
a0f1b0ee01 Split embassy crate into embassy-executor, embassy-util. 2022-07-29 23:40:36 +02:00
chemicstry
42434c75bc Make vref units explicit 2022-07-27 14:13:59 +03:00
chemicstry
b1f0d6320e Improve set_vref docs 2022-07-27 01:30:32 +03:00
chemicstry
046778fc53 Improve ADC configuration options 2022-07-27 01:17:26 +03:00
bors[bot]
84cffc751a
Merge #876
876: Add defmt support to embassy-embedded-hal errors r=Dirbaio a=matoushybl

`defmt::unwrap!()` should now work with shared buses. I tested it only with I2C as I don't have SPI in the target project.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-07-24 20:15:57 +00:00
Matous Hybl
c38755c5b7 Add defmt support to embassy-embedded-hal errors 2022-07-24 22:10:50 +02:00
Dario Nieuwenhuis
b5ff7c5d60 rename PwmPin::new_chX, update examples. 2022-07-23 16:16:29 +02:00
Ben Gamari
042e11960e embassy-stm32/pwm: Generalize channel selection
550da471be previously refactored the STM32
PWM logic in such a way to preclude use of non-contiguous channels (e.g.
channel 2 but not channel 1). Refactor it yet again to yet again allow
this sort of usage.
2022-07-23 15:57:13 +02:00
Dario Nieuwenhuis
19d1ef0e29 stm32/gpio: Add Peripheral<Self> bound to Pin. 2022-07-23 14:28:42 +02:00
Dario Nieuwenhuis
4901c34d9c Rename Unborrowed -> PeripheralRef, Unborrow -> Peripheral 2022-07-23 14:00:19 +02:00
Dario Nieuwenhuis
8a9d2f59af Update embassy-stm32 2022-07-23 02:40:13 +02:00
Dario Nieuwenhuis
be6408e202 Rename unsafe_impl_unborrow to impl_unborrow 2022-07-23 01:33:22 +02:00
bors[bot]
9d388d357a
Merge #866
866: F4 flash fixes r=Dirbaio a=chemicstry

This discontinuous flash sector layout is too cursed and I left some mistakes in last PR. Erasing last sector did not work and it wasn't possible to erase between memory banks for 1MB dual-bank devices. So I changed the erase function to iterate over memory addresses (which is continuous) instead of sector numbers.

It should also be possible to implement erase across memory banks for H7, but it requires special handling for write too. I don't have an H7 to test now so left it as is.

I wasn't sure how to add tests to `embassy-stm32` and it seems that there are none, except for `subghz`, but no test runner? Anyway, I tested the `get_sector` on playground: https://play.rust-lang.org/?version=stable&mode=debug&edition=2021&gist=13b59339fe6c70a3249e6183e81f869e

Also fixed erase alignment requirements on `Flash::blocking_erase()`, as it previously only checked alignment on size, but not on offsets.

P.S. the diff is a bit messed up, I recommend looking at files directly

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-15 06:19:05 +00:00
chemicstry
f0027c9fe0 Require erase address to be aligned to page size 2022-07-14 21:21:46 +03:00
chemicstry
5a265661bb Fix erasing across banks 2022-07-14 20:58:01 +03:00
chemicstry
039acda3a8 Fix writing to last sector of F4 flash 2022-07-14 19:41:39 +03:00
chemicstry
53e40860c1 Move all gpio logic to Flex 2022-07-13 02:45:37 +03:00
chemicstry
a335589f34 Change get_set_level to get_output_level 2022-07-13 02:25:09 +03:00
chemicstry
329955f718 Use Into conversions instead of matches 2022-07-13 02:08:31 +03:00
chemicstry
98dcce81ca Add more convenience GPIO functions 2022-07-13 01:43:22 +03:00
chemicstry
2df665da8a Revert "Make advanced timer trait not require general purpose timer trait as the timers are too different."
This reverts commit 4988dfe981.
2022-07-12 15:11:57 +03:00
bors[bot]
2adee4af38
Merge #858
858: embassy-stm32: Simplify time r=Dirbaio a=GrantM11235

- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-07-11 02:51:06 +00:00
Grant Miller
5ecbe5c918 embassy-stm32: Simplify time
- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait
2022-07-10 21:46:45 -05:00
bors[bot]
99f4fd33b4
Merge #859
859: Add F4 flash driver r=Dirbaio a=chemicstry

Pending on https://github.com/embassy-rs/stm32-data/pull/152

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-11 01:37:19 +00:00
chemicstry
3271ba36e4 Fix cfg flags 2022-07-11 04:07:28 +03:00
chemicstry
734c38eb9c Add F4 flash driver 2022-07-11 03:57:46 +03:00
bors[bot]
9753f76794
Merge #810
810: Takes care of power for nRF USB devices r=Dirbaio a=huntc

Modifies the usb-serial example to illustrate how to setup USB for situations where the USB power can be detected and removed.

Gaps:

~~* No support for the nrf-softdevices as yet, although this should be possible via another constructor.~~
* No support for the nrf5340, although this should be possible via USBREG.

The change is tested and appears to work. Some notes:

* There's an existing field named self_powered as a UsbDevice field. It doesn't ever appear to get set. I'm wondering if this field is intended to signal that a device has the nRF VBUS power situation or not. I'm not presently using it.
* The new PowerDetected event is generated on the bus initially in situations where just new is used i.e. without power management, including on STM. We can therefore rely on this event always being generated.

Old description:

~~EnabledUsbDevice is a wrapper around the `UsbDevice` where its enablement is also subject to external events, such as `POWER` events for nRF. It is introduced generically to support other platforms should they also require external signaling for enablement.~~

Co-authored-by: huntc <huntchr@gmail.com>
2022-07-11 00:01:41 +00:00
bors[bot]
c6a11db39e
Merge #854
854: Implement IWDG timeout calculation r=Dirbaio a=chemicstry

Allow specifying `IndependentWatchdog` timeout as `Duration` instead of prescaler value.

Since IWDG is clocked from LSI, which differs between families, I standardized HSI/LSI definitions in RCC and used that.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-10 21:45:34 +00:00
chemicstry
5a208d28d0 Fix g0 rcc build 2022-07-11 00:37:00 +03:00
bors[bot]
93e7d53e39
Merge #851
851: Gpio dynamic flex r=Dirbaio a=AntoineMugnier

Add Flex GPIO type for embassy-stm32 as it is the case for  embassy-nrf.


Co-authored-by: amugniere@gmail.com <antoine.mugnier@depixus.com>
2022-07-10 21:22:46 +00:00
chemicstry
d7d1e46a5f Use u32 instead of Duration for IWDG 2022-07-11 00:00:33 +03:00
amugniere@gmail.com
323b0d1a5c Have removed ANOTHER redondant ErrorType trait impl 2022-07-10 22:01:48 +02:00
amugniere@gmail.com
1eca026ebd Have removed redondant ErrorType trait impl 2022-07-10 21:36:04 +02:00
amugniere@gmail.com
e4a36e1d98 rustfmt on previously edited files 2022-07-10 21:08:12 +02:00
amugniere@gmail.com
53388d4576 have adapted access to pin() and port() methods of Sealed::Pin in exti.rs according to previous changes on Input struct 2022-07-10 20:55:04 +02:00
chemicstry
3bf1e1d4aa Fix f2, wl compilation 2022-07-10 21:46:14 +03:00
chemicstry
f43545f36e Fix warnings 2022-07-10 21:16:54 +03:00
chemicstry
85054a7233 Fix typo 2022-07-10 21:15:38 +03:00
chemicstry
1fd5022e72 Refactor IWDG to use LSI frequency from RCC 2022-07-10 20:59:36 +03:00
chemicstry
bd01e90bfa Implement IWDG timeout calculation 2022-07-10 20:38:30 +03:00
bors[bot]
5f43c1d37e
Merge #850
850: Shared buses with SetConfig r=Dirbaio a=kalkyl

Addresses issue #830 

Co-authored-by: Henrik Alsér <henrik@mindbite.se>
2022-07-10 00:03:44 +00:00
Henrik Alsér
baae64d911 Add embassy-embedded-hal nightly feature 2022-07-09 23:41:02 +02:00
amugniere@gmail.com
fa3e1ab68a correction of the access to flex pin attribute in gpio_v2 2022-07-09 14:06:47 +02:00
Henrik Alsér
880b71a1e8 impl SetConfig for stm32 i2c and SPI 2022-07-09 02:28:05 +02:00
amugniere@gmail.com
39702d7624 set_as_input_output() and set_as_output() : Have added comments and made functions public 2022-07-08 21:46:16 +02:00
Henrik Alsér
43aec9083c Cleanup 2022-07-08 08:03:38 +02:00
Dario Nieuwenhuis
01ef03f446 stm32/i2c: impl ErrorType for all. 2022-07-07 15:46:30 +02:00
Henrik Alsér
399e7a4791 NoDma 2022-07-07 15:46:30 +02:00
Henrik Alsér
be731b222e Cleanup 2022-07-07 15:46:30 +02:00
Henrik Alsér
0fe818f4f8 v1 fix 2022-07-07 15:46:30 +02:00
Henrik Alsér
1ed5b387f9 v2 fix 2022-07-07 15:46:30 +02:00
Henrik Alsér
02812754ec rustfmt 2022-07-07 15:46:30 +02:00
Henrik Alsér
2460d21fa4 Add EH 1.0 impls for stm32 i2c 2022-07-07 15:46:30 +02:00
huntc
4a8f117f25 Puts in the machinery to handle power detected/removed 2022-07-07 10:08:57 +10:00
amugniere@gmail.com
4e54d09ab1 Have added OutputOpenDrain with Flex 2022-07-04 22:38:05 +02:00
amugniere@gmail.com
13b259d7cd Have added Flex to eh01 and eh2 2022-07-04 22:19:02 +02:00
amugniere@gmail.com
359fc4d124 Flex GPIO implementation : Output 2022-06-30 23:03:15 +02:00
amugniere@gmail.com
f05082b9a3 have reverted changed in mod eh1 from previous commit 2022-06-30 22:55:57 +02:00
amugniere@gmail.com
9b3c5af92a Flex GPIO implementation : Input 2022-06-30 22:50:53 +02:00
Vincent Stakenburg
d1d07cd9e3 fix case when chip has multiple iwdg 2022-06-28 13:22:43 +02:00
Vincent Stakenburg
f2ad9c2d9d rebase and fix unborrow 2022-06-28 12:51:08 +02:00
Vincent Stakenburg
74bbf5aa02 address review 2022-06-28 12:46:17 +02:00
Vincent Stakenburg
5cf3fbece4 initial independent watchdog implementation 2022-06-28 12:46:17 +02:00
Dario Nieuwenhuis
42bc510eff Remove STM32L485 "ghost chips" 2022-06-27 02:47:15 +02:00
Dario Nieuwenhuis
a855889f70 Update stm32-data 2022-06-27 02:10:01 +02:00
Dario Nieuwenhuis
948bb93dc2 docs: Add $COMMIT to git srclinks. 2022-06-26 23:55:38 +02:00
Dario Nieuwenhuis
397722c328 stm32: fix f100 build. 2022-06-26 23:52:38 +02:00
bors[bot]
84628d36cf
Merge #826
826: Bump bxcan version r=chemicstry a=chemicstry



Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-06-22 23:48:45 +00:00
chemicstry
3cdd8c1aeb Fix PWM for advanced timers 2022-06-23 02:27:39 +03:00
chemicstry
31177d994f Fix example 2022-06-23 02:01:23 +03:00
chemicstry
2d2f9e39b9 Bump bxcan version 2022-06-23 01:42:21 +03:00
Dario Nieuwenhuis
1f746e0939 Remove the authors field from Cargo.tomls
It currently contains whoever was first to write some code for the crate,
even if many more people have contributed to it later.

The field is "sort of" deprecated, it was made optional recently:
https://rust-lang.github.io/rfcs/3052-optional-authors-field.html

Due the the reasons listed there I believe removing it is better than
setting it to generic fluff like "The Embassy contributors".
2022-06-18 02:16:40 +02:00
Dario Nieuwenhuis
88e36a70bd
Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
Daniel Bevenius
9031b8f80a Fix doc comments for BpskPacketParams 2022-06-16 07:34:59 +02:00
Daniel Bevenius
d0edd171f8 Fix typo in LoRaPacketParams::new doc 2022-06-16 06:22:03 +02:00
Ulf Lilleengen
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
Ulf Lilleengen
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
Dario Nieuwenhuis
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
Dario Nieuwenhuis
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
Dario Nieuwenhuis
db344c2bda
common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
Ulf Lilleengen
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
Dario Nieuwenhuis
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
Dario Nieuwenhuis
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
chemicstry
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
Will Glynn
34a8a64bf5 stm32: make tick rate configurable
The stm32 time drivers support arbitrary tick rates but the associated
Cargo features do not. Enabling any time driver presently enables
`embassy/time-tick-32768hz`; instead, enable only `embassy/time`.

This is a breaking change: users must now choose a tick rate. The
previous behavior is available by enabling the
`embassy/time-tick-32768hz` feature, but now users may also choose
`embassy/time-tick-1000hz` or `embassy/time-tick-1mhz` instead.
2022-05-30 20:13:25 -05:00
bors[bot]
70e4418df9
Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00
Dario Nieuwenhuis
6320e30adf Update embedded-hal-async to 0.1.0-alpha.1 2022-05-29 22:34:08 +02:00
Will Glynn
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00
chemicstry
1d951a54be Reimplement BufRead for BufferedUart 2022-05-26 14:02:55 +03:00
Dario Nieuwenhuis
a5aea995a8 WIP embassy-net v2 2022-05-25 19:56:22 +02:00
Dario Nieuwenhuis
d0fe9af458
Merge pull request #771 from embassy-rs/net-split
net: add split() to tcpsocket
2022-05-19 07:13:24 +02:00
Dario Nieuwenhuis
e3b8e35498 Make embassy-net nightly-only.
It's useless without async traits, so juggling the `nightly` feature
around is not worth the pain.
2022-05-19 06:15:01 +02:00
bors[bot]
7743b8e1ae
Merge #776
776: Automatically set ADC clock prescaler on v2 ADC to respect max frequency r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-05-19 04:00:23 +00:00
Dario Nieuwenhuis
47ceee47d5 Update embedded-io to 0.3 2022-05-19 00:36:18 +02:00
Matous Hybl
53f65d8b09 Automatically set ADC clock prescaler on v2 ADC to respect max frequency 2022-05-18 18:34:36 +02:00
Ralf
c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00