Commit graph

2404 commits

Author SHA1 Message Date
Dario Nieuwenhuis
77841a4676 stm32/dma: panic on DMA error. 2022-03-09 03:19:05 +01:00
bors[bot]
13247897b0
Merge #640
640: Skip EasyDMA slice location check for empty slices and copy data if necessary r=Dirbaio a=TilBlechschmidt

As discussed, this PR makes the following changes:
- Ignore pointer location of zero-length slices (fixes #631)
- Change default functions so they copy the tx buffer if it does not reside in RAM
- Introduce new variants for `write`, `transfer`, and their blocking versions which fails instead of copying
- Add documentation about the motivation behind all these variants
<img width="984" alt="image" src="https://user-images.githubusercontent.com/5037967/155415788-c2cd1055-9289-4004-959d-be3b1934a439.png">


Remaining TODOs:

- [x] Change copying behaviour for other peripherals
    - [x] TWI
    - [x] UART
- [x] Add module-level documentation regarding EasyDMA and `_from_ram` method variants

`@Dirbaio` it probably makes sense for you to review it now before I "copy" over the changes to the other two peripherals.

Co-authored-by: Til Blechschmidt <til@blechschmidt.de>
2022-03-09 01:47:52 +00:00
bors[bot]
3047098c55
Merge #648 #656
648: Fix nRF Saadc continuous sampling r=Dirbaio a=huntc

Starting the sampling task prior to starting the SAADC peripheral can lead to unexpected buffer behaviour with multiple channels. We now provide an init callback at the point where the SAADC has started for the first time. This callback can be used to kick off sampling via PPI.

We also need to trigger the SAADC to start sampling the next buffer when the previous one is ended so that we do not drop samples - the major benefit of double buffering.

Given these additional tasks, we now simplify the API by passing in the TIMER and two PPI channels.

As a bonus, we provide an async `calibrate` method as it is recommended to use before starting up the sampling.

The example has been updated to illustrate these new features along with the simplified API.

The changes here have been tested on my nRF52840-DK.

656: stm32: Refactor DMA interrupts r=Dirbaio a=GrantM11235

Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.

Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.

Co-authored-by: huntc <huntchr@gmail.com>
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-03-09 00:43:17 +00:00
Grant Miller
fe6d7ef5fe Update tests 2022-03-08 17:35:37 -06:00
Grant Miller
ed84d753c7 Update examples 2022-03-08 17:12:50 -06:00
Grant Miller
8f7bb570ae Ignore BDMA1 in H7 2022-03-08 16:46:42 -06:00
Grant Miller
6a09ae7f92 Update stm32-data 2022-03-08 16:31:14 -06:00
Grant Miller
8c45c98e41 stm32: Refactor DMA interrupts
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.

Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
2022-03-08 14:18:31 -06:00
Til Blechschmidt
63030bf998
Move EasyDMA documentation to module level 2022-03-08 17:49:15 +01:00
Til Blechschmidt
7540b44050
Fix inverted boolean condition 2022-03-08 16:29:42 +01:00
huntc
3990f09b29 Simplifies the API by taking in the TIMER and PPI channels 2022-03-07 14:51:17 +11:00
huntc
98bdac51fe Improve nRF Saadc sampling
Starting the sampling task prior to starting the SAADC peripheral can lead to unexpected buffer behaviour with multiple channels. We now provide an init callback at the point where the SAADC has started for the first time. This callback can be used to kick off sampling via PPI.

We also need to trigger the SAADC to start sampling the next buffer when the previous one is ended so that we do not drop samples - the major benefit of double buffering.

As a bonus we provide a calibrate method as it is recommended to use before starting up the sampling.

The example has been updated to illustrate these new features.
2022-03-07 14:51:17 +11:00
bors[bot]
9735c38592
Merge #655
655: common/serial/usb: fix hang when write buffer gets full and then the bus resets. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-06 23:33:02 +00:00
Dario Nieuwenhuis
8acec146e0 common/serial/usb: fix hang when write buffer gets full and then the bus resets.
Fixes #654
2022-03-07 00:32:31 +01:00
Dario Nieuwenhuis
88d9599a63 common/usb/serial: add some trace logging. 2022-03-07 00:32:31 +01:00
bors[bot]
24b6478a7c
Merge #650
650: `bxcan` improvements r=Dirbaio a=timokroeger

* Do not use wildcard reexport for `bxcan`
* `cfgs` to fix `bxcan` implementation for devices with "CAN1" but no "CAN2" peripheral

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
2022-03-05 17:00:59 +00:00
Timo Kröger
372b71890d [can] Typo fix: l7 -> f7 2022-03-05 09:46:06 +01:00
Timo Kröger
d6d25e6470 [can] cfgs for naming inconsistencies
Approach is similar to USB OTG.
STM32L49x and STML4Ax have CAN1 and CAN2.
All others STM32L4xx do only have CAN1.
STM32F72x and STM32F73x are the only F7 devices with only CAN1.
2022-03-05 09:46:06 +01:00
Timo Kröger
6929350552 [can] Update macrotable comment
The chip description are corrected in:
https://github.com/embassy-rs/stm32-data/pull/123
2022-03-05 09:46:06 +01:00
Timo Kröger
4c30543938 [can] Do not use wildcard reexport for bxcan 2022-03-05 09:46:06 +01:00
bors[bot]
9ebf7eee6d
Merge #652 #653
652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff

This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.

I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.

653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio



Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-04 17:07:04 +00:00
Dario Nieuwenhuis
609975f821 rustfmt 2022-03-04 18:04:12 +01:00
Matthew W. Samsonoff
877fbeb223 Update stm32-data submodule 2022-03-04 18:03:55 +01:00
Matthew W. Samsonoff
047ff9a2f2 Use new stm32-data registers and fix AHB clock calculation
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
2022-03-04 18:03:55 +01:00
Dario Nieuwenhuis
265cd1115b stm32: allow unused macrotables. 2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
44096358a2 docs: add metadata.embassy_docs to cargo tomls. 2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
7b2a255872 stm32-metapac: add doc(html_no_source).
The source files are unreadable because they're not fmt'd, and
they take up a LOT of space when generating docs for all 1200 chips
because they don't deduplicate.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
53d9a0b516 stm32: exclude spammy files from docs by prefixing with _.
These files end up containing chip-specific info, so they deduplicate
really badly when building docs for all 1200 chips.

The doc generator removes files starting with `_`.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
94b232cf88 docs: prevent inline doc spam for reexports. 2022-03-04 18:03:41 +01:00
Til Blechschmidt
993428e2d4
Refactor _from_ram methods to use more readable copy operation 2022-03-02 22:48:58 +01:00
Til Blechschmidt
3f2d9cfe0a
Change TWIM methods to copy slice if required and add non-copying variants 2022-03-02 22:45:38 +01:00
Til Blechschmidt
2c402ecf16
Change UARTE methods to copy slice if required and add non-copying variants 2022-03-02 22:40:40 +01:00
bors[bot]
35636953b2
Merge #636
636: stm32: Add support for using TIM12 and TIM15 as time driver r=Dirbaio a=matoushybl

I am not sure what the effect of reducing the number of alarms will be, but these are the only timers I have available on my board.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-02-28 18:25:13 +00:00
Matous Hybl
0172ca5b81 stm32: Add support for using TIM12 and TIM15 as time driver 2022-02-28 19:20:22 +01:00
bors[bot]
b9a8d649cf
Merge #649
649: stm32: Register access for timers now doesn't require self r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-02-28 15:55:29 +00:00
Matous Hybl
a88c5e716e stm32: Register access for timers now doesn't require self 2022-02-28 16:20:42 +01:00
bors[bot]
141e007acf
Merge #646
646: Debloat stm32-metapac r=Dirbaio a=Dirbaio

- Remove usage of `peripheral_counts!` macrotables.
- Remove `dbgmcu!` macrotable.
- Move the remaining macrotables to embassy-stm32 build.rs. This brings metapac decompressed size from ~250mb to ~100mb
- Deduplicate files with identical metadata. This brings decompressed size from ~100mb to ~70mb, compressed from ~10mb to ~4mb, which is finally small enough to publish on crates.io!

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-26 02:42:26 +00:00
Dario Nieuwenhuis
451bb48464 stm32-metapac: remove all macrotables, deduplicate metadata files. 2022-02-26 03:23:09 +01:00
Dario Nieuwenhuis
dd828a7a92 stm32: move macrotables to embassy-stm32 build.rs 2022-02-26 03:23:09 +01:00
Dario Nieuwenhuis
e6299549a0 stm32/i2c: use one static per instance instead of an array. 2022-02-26 01:23:17 +01:00
Dario Nieuwenhuis
8d46d31824 stm32/dbgmcu: do not use macrotable. 2022-02-26 01:20:42 +01:00
bors[bot]
d381b8e2b6
Merge #645
645: stm32 usart: Fix RX interrupt flag handling r=lulf a=timokroeger

* On v1 interrupts cannot be cleared individually.
  Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
  Handle them all in one go intstead of re-entering the ISR for each one so that
  we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
  from the buffer before receiving the next byte.

Tested on v1 hardware, lets see if v2 still succeeds on CI.

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
2022-02-25 14:28:44 +00:00
Timo Kröger
48f700b35c stm32 usart: Fix RX interrupt flag handling
* On v1 interrupts cannot be cleared individually.
  Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
  Handle them all in one go intstead of re-entering the ISR for each one so that
  we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
  from the buffer before receiving the next byte.
2022-02-25 14:32:39 +01:00
bors[bot]
6da4b66364
Merge #644
644: stm32 misc fixes r=Dirbaio a=Dirbaio

- Fix build when no DBGMCU is present (wl55 cm0 core)
- Fix multicore 2nd core having the wrong NVIC.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-25 00:47:12 +00:00
Dario Nieuwenhuis
f6bbb987c8 stm32: update stm32-data, fixes multicore nvic 2022-02-25 01:16:40 +01:00
Dario Nieuwenhuis
0ad7a3aa6f stm32: fix chips without dbgmcu (wl55 cm0 core) 2022-02-25 01:16:23 +01:00
bors[bot]
5163de6094
Merge #643
643: stm32: build fixes for troublesome chips r=Dirbaio a=Dirbaio

See individual commits.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-24 05:29:33 +00:00
Dario Nieuwenhuis
14afe0f6e4 ci: add troublesome stm32 chips 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
ea5cd19c30 stm32: fix build for h7ab 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
1ff80f8438 stm32/mco: fix on h7ab 2022-02-24 06:28:29 +01:00