bors[bot] 855c0d1423 Merge #1376 ... 1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file. Co-authored-by: xoviat <xoviat@users.noreply.github.com>		2023-05-01 19:32:06 +00:00
..
.cargo	Add env DEFMT_LOG=trace to all examples.	2022-06-18 01:59:12 +02:00
src	stm32/rtc: fix datetime and add f4 test	2023-04-25 17:35:01 -05:00
build.rs	stm32/test: add C0 hil tests.	2023-04-11 14:16:32 +02:00
Cargo.toml	Merge #1376	2023-05-01 19:32:06 +00:00
gen_test.py	stm32/sdmmc: add hil test for f4.	2023-04-17 21:49:34 +02:00
link_ram.x	tests/stm32: make __sdata=__edata so that cortex-m-rt doesn't try to copy it from "flash".	2022-01-05 13:30:08 +01:00
teleprobe.sh	stm32/usart: expose all functionality as inherent methods.	2022-01-19 17:59:55 +01:00