From 0a36bfbf921038e8eb7d4294ec8543903c933d90 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Mon, 9 Jul 2018 22:48:28 -0300
Subject: [PATCH] Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm (#239)
---
ChocolArm64/Instruction/AInstEmitSimdMove.cs | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
index 95fe594994..d67946a977 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
@@ -339,9 +339,12 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size);
- EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ EmitVectorInsertTmp(Context, Index, Op.Size);
}
+ Context.EmitLdvectmp();
+ Context.EmitStvec(Op.Rd);
+
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
@@ -363,9 +366,12 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem, Op.Size);
- EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ EmitVectorInsertTmp(Context, Index, Op.Size);
}
+ Context.EmitLdvectmp();
+ Context.EmitStvec(Op.Rd);
+
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
@@ -387,9 +393,12 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size);
- EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ EmitVectorInsertTmp(Context, Index, Op.Size);
}
+ Context.EmitLdvectmp();
+ Context.EmitStvec(Op.Rd);
+
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);