From 5be6ec63648eec8ad108c3b4bd681e5397afb646 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Wed, 13 Jan 2021 21:07:50 -0300 Subject: [PATCH] Fix shader LOP3 predicate write condition (#1910) * Fix LOP3 predicate write condition * Bump shader cache version --- Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs | 2 +- Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs | 4 ---- Ryujinx.Graphics.Shader/Instructions/InstEmitAlu.cs | 12 ++++++------ 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs b/Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs index 366c93df2b..20e1c9f847 100644 --- a/Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs +++ b/Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs @@ -34,7 +34,7 @@ namespace Ryujinx.Graphics.Gpu.Shader /// /// Version of the codegen (to be changed when codegen or guest format change). /// - private const ulong ShaderCodeGenVersion = 1901; + private const ulong ShaderCodeGenVersion = 1910; /// /// Creates a new instance of the shader cache. diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs index 45399de0d1..c774523ba7 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs @@ -9,8 +9,6 @@ namespace Ryujinx.Graphics.Shader.Decoders public LogicalOperation LogicalOp { get; } - public ConditionalOperation CondOp { get; } - public Register Predicate48 { get; } public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLop(emitter, address, opCode); @@ -22,8 +20,6 @@ namespace Ryujinx.Graphics.Shader.Decoders LogicalOp = (LogicalOperation)opCode.Extract(41, 2); - CondOp = (ConditionalOperation)opCode.Extract(44, 2); - Predicate48 = new Register(opCode.Extract(48, 3), RegisterType.Predicate); } } diff --git a/Ryujinx.Graphics.Shader/Instructions/InstEmitAlu.cs b/Ryujinx.Graphics.Shader/Instructions/InstEmitAlu.cs index 64ac0eb780..37c17ecc40 100644 --- a/Ryujinx.Graphics.Shader/Instructions/InstEmitAlu.cs +++ b/Ryujinx.Graphics.Shader/Instructions/InstEmitAlu.cs @@ -459,7 +459,7 @@ namespace Ryujinx.Graphics.Shader.Instructions case LogicalOperation.ExclusiveOr: res = context.BitwiseExclusiveOr(srcA, srcB); break; } - EmitLopPredWrite(context, op, res); + EmitLopPredWrite(context, op, res, (ConditionalOperation)context.CurrOp.RawOpCode.Extract(44, 2)); Operand dest = GetDest(context); @@ -486,7 +486,7 @@ namespace Ryujinx.Graphics.Shader.Instructions if (regVariant) { - EmitLopPredWrite(context, op, res); + EmitLopPredWrite(context, op, res, (ConditionalOperation)context.CurrOp.RawOpCode.Extract(36, 2)); } Operand dest = GetDest(context); @@ -917,21 +917,21 @@ namespace Ryujinx.Graphics.Shader.Instructions return res; } - private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result) + private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result, ConditionalOperation condOp) { if (op is OpCodeLop opLop && !opLop.Predicate48.IsPT) { Operand pRes; - if (opLop.CondOp == ConditionalOperation.False) + if (condOp == ConditionalOperation.False) { pRes = Const(IrConsts.False); } - else if (opLop.CondOp == ConditionalOperation.True) + else if (condOp == ConditionalOperation.True) { pRes = Const(IrConsts.True); } - else if (opLop.CondOp == ConditionalOperation.Zero) + else if (condOp == ConditionalOperation.Zero) { pRes = context.ICompareEqual(result, Const(0)); }