forked from Mirror/Ryujinx
45ce540b9b
* ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake.13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)* ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
228 lines
No EOL
3.6 KiB
C#
228 lines
No EOL
3.6 KiB
C#
namespace ARMeilleure.CodeGen.X86
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{
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enum X86Instruction
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{
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None,
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Add,
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Addpd,
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Addps,
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Addsd,
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Addss,
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Aesdec,
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Aesdeclast,
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Aesenc,
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Aesenclast,
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Aesimc,
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And,
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Andnpd,
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Andnps,
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Andpd,
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Andps,
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Blendvpd,
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Blendvps,
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Bsr,
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Bswap,
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Call,
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Cmovcc,
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Cmp,
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Cmppd,
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Cmpps,
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Cmpsd,
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Cmpss,
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Cmpxchg,
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Cmpxchg16b,
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Cmpxchg8,
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Comisd,
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Comiss,
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Crc32,
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Crc32_16,
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Crc32_8,
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Cvtdq2pd,
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Cvtdq2ps,
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Cvtpd2dq,
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Cvtpd2ps,
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Cvtps2dq,
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Cvtps2pd,
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Cvtsd2si,
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Cvtsd2ss,
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Cvtsi2sd,
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Cvtsi2ss,
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Cvtss2sd,
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Cvtss2si,
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Div,
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Divpd,
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Divps,
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Divsd,
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Divss,
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Gf2p8affineqb,
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Haddpd,
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Haddps,
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Idiv,
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Imul,
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Imul128,
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Insertps,
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Jmp,
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Ldmxcsr,
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Lea,
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Maxpd,
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Maxps,
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Maxsd,
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Maxss,
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Minpd,
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Minps,
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Minsd,
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Minss,
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Mov,
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Mov16,
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Mov8,
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Movd,
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Movdqu,
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Movhlps,
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Movlhps,
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Movq,
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Movsd,
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Movss,
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Movsx16,
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Movsx32,
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Movsx8,
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Movzx16,
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Movzx8,
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Mul128,
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Mulpd,
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Mulps,
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Mulsd,
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Mulss,
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Neg,
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Not,
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Or,
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Paddb,
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Paddd,
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Paddq,
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Paddw,
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Palignr,
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Pand,
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Pandn,
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Pavgb,
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Pavgw,
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Pblendvb,
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Pclmulqdq,
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Pcmpeqb,
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Pcmpeqd,
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Pcmpeqq,
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Pcmpeqw,
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Pcmpgtb,
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Pcmpgtd,
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Pcmpgtq,
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Pcmpgtw,
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Pextrb,
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Pextrd,
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Pextrq,
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Pextrw,
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Pinsrb,
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Pinsrd,
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Pinsrq,
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Pinsrw,
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Pmaxsb,
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Pmaxsd,
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Pmaxsw,
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Pmaxub,
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Pmaxud,
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Pmaxuw,
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Pminsb,
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Pminsd,
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Pminsw,
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Pminub,
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Pminud,
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Pminuw,
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Pmovsxbw,
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Pmovsxdq,
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Pmovsxwd,
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Pmovzxbw,
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Pmovzxdq,
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Pmovzxwd,
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Pmulld,
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Pmullw,
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Pop,
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Popcnt,
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Por,
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Pshufb,
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Pshufd,
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Pslld,
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Pslldq,
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Psllq,
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Psllw,
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Psrad,
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Psraw,
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Psrld,
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Psrlq,
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Psrldq,
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Psrlw,
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Psubb,
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Psubd,
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Psubq,
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Psubw,
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Punpckhbw,
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Punpckhdq,
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Punpckhqdq,
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Punpckhwd,
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Punpcklbw,
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Punpckldq,
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Punpcklqdq,
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Punpcklwd,
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Push,
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Pxor,
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Rcpps,
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Rcpss,
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Ror,
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Roundpd,
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Roundps,
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Roundsd,
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Roundss,
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Rsqrtps,
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Rsqrtss,
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Sar,
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Setcc,
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Sha256Msg1,
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Sha256Msg2,
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Sha256Rnds2,
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Shl,
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Shr,
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Shufpd,
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Shufps,
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Sqrtpd,
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Sqrtps,
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Sqrtsd,
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Sqrtss,
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Stmxcsr,
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Sub,
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Subpd,
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Subps,
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Subsd,
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Subss,
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Test,
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Unpckhpd,
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Unpckhps,
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Unpcklpd,
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Unpcklps,
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Vblendvpd,
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Vblendvps,
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Vcvtph2ps,
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Vcvtps2ph,
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Vfmadd231ps,
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Vfmadd231sd,
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Vfmadd231ss,
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Vfmsub231sd,
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Vfmsub231ss,
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Vfnmadd231ps,
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Vfnmadd231sd,
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Vfnmadd231ss,
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Vfnmsub231sd,
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Vfnmsub231ss,
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Vpblendvb,
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Xor,
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Xorpd,
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Xorps,
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Count
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}
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} |