diff --git a/Directory.Packages.props b/Directory.Packages.props
index cde8974df1..1b0b906f8c 100644
--- a/Directory.Packages.props
+++ b/Directory.Packages.props
@@ -49,6 +49,7 @@
+
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/MemoryPermission.cs b/Ryujinx.Tests.Unicorn/MemoryPermission.cs
index a14c4e9cf1..044b3176bb 100644
--- a/Ryujinx.Tests.Unicorn/MemoryPermission.cs
+++ b/Ryujinx.Tests.Unicorn/MemoryPermission.cs
@@ -1,11 +1,14 @@
+using System;
+
namespace Ryujinx.Tests.Unicorn
{
+ [Flags]
public enum MemoryPermission
{
- NONE = 0,
- READ = 1,
- WRITE = 2,
- EXEC = 4,
- ALL = 7,
+ None = 0,
+ Read = 1,
+ Write = 2,
+ Exec = 4,
+ All = 7,
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Arch.cs b/Ryujinx.Tests.Unicorn/Native/Const/Arch.cs
deleted file mode 100644
index f614d091b7..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Arch.cs
+++ /dev/null
@@ -1,20 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Arch
- {
- ARM = 1,
- ARM64 = 2,
- MIPS = 3,
- X86 = 4,
- PPC = 5,
- SPARC = 6,
- M68K = 7,
- RISCV = 8,
- S390X = 9,
- TRICORE = 10,
- MAX = 11,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Arm.cs b/Ryujinx.Tests.Unicorn/Native/Const/Arm.cs
deleted file mode 100644
index 4b7b3d6f31..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Arm.cs
+++ /dev/null
@@ -1,200 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Arm
- {
-
- // ARM CPU
-
- CPU_ARM_926 = 0,
- CPU_ARM_946 = 1,
- CPU_ARM_1026 = 2,
- CPU_ARM_1136_R2 = 3,
- CPU_ARM_1136 = 4,
- CPU_ARM_1176 = 5,
- CPU_ARM_11MPCORE = 6,
- CPU_ARM_CORTEX_M0 = 7,
- CPU_ARM_CORTEX_M3 = 8,
- CPU_ARM_CORTEX_M4 = 9,
- CPU_ARM_CORTEX_M7 = 10,
- CPU_ARM_CORTEX_M33 = 11,
- CPU_ARM_CORTEX_R5 = 12,
- CPU_ARM_CORTEX_R5F = 13,
- CPU_ARM_CORTEX_A7 = 14,
- CPU_ARM_CORTEX_A8 = 15,
- CPU_ARM_CORTEX_A9 = 16,
- CPU_ARM_CORTEX_A15 = 17,
- CPU_ARM_TI925T = 18,
- CPU_ARM_SA1100 = 19,
- CPU_ARM_SA1110 = 20,
- CPU_ARM_PXA250 = 21,
- CPU_ARM_PXA255 = 22,
- CPU_ARM_PXA260 = 23,
- CPU_ARM_PXA261 = 24,
- CPU_ARM_PXA262 = 25,
- CPU_ARM_PXA270 = 26,
- CPU_ARM_PXA270A0 = 27,
- CPU_ARM_PXA270A1 = 28,
- CPU_ARM_PXA270B0 = 29,
- CPU_ARM_PXA270B1 = 30,
- CPU_ARM_PXA270C0 = 31,
- CPU_ARM_PXA270C5 = 32,
- CPU_ARM_MAX = 33,
- CPU_ARM_ENDING = 34,
-
- // ARM registers
-
- REG_INVALID = 0,
- REG_APSR = 1,
- REG_APSR_NZCV = 2,
- REG_CPSR = 3,
- REG_FPEXC = 4,
- REG_FPINST = 5,
- REG_FPSCR = 6,
- REG_FPSCR_NZCV = 7,
- REG_FPSID = 8,
- REG_ITSTATE = 9,
- REG_LR = 10,
- REG_PC = 11,
- REG_SP = 12,
- REG_SPSR = 13,
- REG_D0 = 14,
- REG_D1 = 15,
- REG_D2 = 16,
- REG_D3 = 17,
- REG_D4 = 18,
- REG_D5 = 19,
- REG_D6 = 20,
- REG_D7 = 21,
- REG_D8 = 22,
- REG_D9 = 23,
- REG_D10 = 24,
- REG_D11 = 25,
- REG_D12 = 26,
- REG_D13 = 27,
- REG_D14 = 28,
- REG_D15 = 29,
- REG_D16 = 30,
- REG_D17 = 31,
- REG_D18 = 32,
- REG_D19 = 33,
- REG_D20 = 34,
- REG_D21 = 35,
- REG_D22 = 36,
- REG_D23 = 37,
- REG_D24 = 38,
- REG_D25 = 39,
- REG_D26 = 40,
- REG_D27 = 41,
- REG_D28 = 42,
- REG_D29 = 43,
- REG_D30 = 44,
- REG_D31 = 45,
- REG_FPINST2 = 46,
- REG_MVFR0 = 47,
- REG_MVFR1 = 48,
- REG_MVFR2 = 49,
- REG_Q0 = 50,
- REG_Q1 = 51,
- REG_Q2 = 52,
- REG_Q3 = 53,
- REG_Q4 = 54,
- REG_Q5 = 55,
- REG_Q6 = 56,
- REG_Q7 = 57,
- REG_Q8 = 58,
- REG_Q9 = 59,
- REG_Q10 = 60,
- REG_Q11 = 61,
- REG_Q12 = 62,
- REG_Q13 = 63,
- REG_Q14 = 64,
- REG_Q15 = 65,
- REG_R0 = 66,
- REG_R1 = 67,
- REG_R2 = 68,
- REG_R3 = 69,
- REG_R4 = 70,
- REG_R5 = 71,
- REG_R6 = 72,
- REG_R7 = 73,
- REG_R8 = 74,
- REG_R9 = 75,
- REG_R10 = 76,
- REG_R11 = 77,
- REG_R12 = 78,
- REG_S0 = 79,
- REG_S1 = 80,
- REG_S2 = 81,
- REG_S3 = 82,
- REG_S4 = 83,
- REG_S5 = 84,
- REG_S6 = 85,
- REG_S7 = 86,
- REG_S8 = 87,
- REG_S9 = 88,
- REG_S10 = 89,
- REG_S11 = 90,
- REG_S12 = 91,
- REG_S13 = 92,
- REG_S14 = 93,
- REG_S15 = 94,
- REG_S16 = 95,
- REG_S17 = 96,
- REG_S18 = 97,
- REG_S19 = 98,
- REG_S20 = 99,
- REG_S21 = 100,
- REG_S22 = 101,
- REG_S23 = 102,
- REG_S24 = 103,
- REG_S25 = 104,
- REG_S26 = 105,
- REG_S27 = 106,
- REG_S28 = 107,
- REG_S29 = 108,
- REG_S30 = 109,
- REG_S31 = 110,
- REG_C1_C0_2 = 111,
- REG_C13_C0_2 = 112,
- REG_C13_C0_3 = 113,
- REG_IPSR = 114,
- REG_MSP = 115,
- REG_PSP = 116,
- REG_CONTROL = 117,
- REG_IAPSR = 118,
- REG_EAPSR = 119,
- REG_XPSR = 120,
- REG_EPSR = 121,
- REG_IEPSR = 122,
- REG_PRIMASK = 123,
- REG_BASEPRI = 124,
- REG_BASEPRI_MAX = 125,
- REG_FAULTMASK = 126,
- REG_APSR_NZCVQ = 127,
- REG_APSR_G = 128,
- REG_APSR_NZCVQG = 129,
- REG_IAPSR_NZCVQ = 130,
- REG_IAPSR_G = 131,
- REG_IAPSR_NZCVQG = 132,
- REG_EAPSR_NZCVQ = 133,
- REG_EAPSR_G = 134,
- REG_EAPSR_NZCVQG = 135,
- REG_XPSR_NZCVQ = 136,
- REG_XPSR_G = 137,
- REG_XPSR_NZCVQG = 138,
- REG_CP_REG = 139,
- REG_ENDING = 140,
-
- // alias registers
- REG_R13 = 12,
- REG_R14 = 10,
- REG_R15 = 11,
- REG_SB = 75,
- REG_SL = 76,
- REG_FP = 77,
- REG_IP = 78,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Arm64.cs b/Ryujinx.Tests.Unicorn/Native/Const/Arm64.cs
deleted file mode 100644
index 11344557b7..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Arm64.cs
+++ /dev/null
@@ -1,341 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Arm64
- {
-
- // ARM64 CPU
-
- CPU_ARM64_A57 = 0,
- CPU_ARM64_A53 = 1,
- CPU_ARM64_A72 = 2,
- CPU_ARM64_MAX = 3,
- CPU_ARM64_ENDING = 4,
-
- // ARM64 registers
-
- REG_INVALID = 0,
- REG_X29 = 1,
- REG_X30 = 2,
- REG_NZCV = 3,
- REG_SP = 4,
- REG_WSP = 5,
- REG_WZR = 6,
- REG_XZR = 7,
- REG_B0 = 8,
- REG_B1 = 9,
- REG_B2 = 10,
- REG_B3 = 11,
- REG_B4 = 12,
- REG_B5 = 13,
- REG_B6 = 14,
- REG_B7 = 15,
- REG_B8 = 16,
- REG_B9 = 17,
- REG_B10 = 18,
- REG_B11 = 19,
- REG_B12 = 20,
- REG_B13 = 21,
- REG_B14 = 22,
- REG_B15 = 23,
- REG_B16 = 24,
- REG_B17 = 25,
- REG_B18 = 26,
- REG_B19 = 27,
- REG_B20 = 28,
- REG_B21 = 29,
- REG_B22 = 30,
- REG_B23 = 31,
- REG_B24 = 32,
- REG_B25 = 33,
- REG_B26 = 34,
- REG_B27 = 35,
- REG_B28 = 36,
- REG_B29 = 37,
- REG_B30 = 38,
- REG_B31 = 39,
- REG_D0 = 40,
- REG_D1 = 41,
- REG_D2 = 42,
- REG_D3 = 43,
- REG_D4 = 44,
- REG_D5 = 45,
- REG_D6 = 46,
- REG_D7 = 47,
- REG_D8 = 48,
- REG_D9 = 49,
- REG_D10 = 50,
- REG_D11 = 51,
- REG_D12 = 52,
- REG_D13 = 53,
- REG_D14 = 54,
- REG_D15 = 55,
- REG_D16 = 56,
- REG_D17 = 57,
- REG_D18 = 58,
- REG_D19 = 59,
- REG_D20 = 60,
- REG_D21 = 61,
- REG_D22 = 62,
- REG_D23 = 63,
- REG_D24 = 64,
- REG_D25 = 65,
- REG_D26 = 66,
- REG_D27 = 67,
- REG_D28 = 68,
- REG_D29 = 69,
- REG_D30 = 70,
- REG_D31 = 71,
- REG_H0 = 72,
- REG_H1 = 73,
- REG_H2 = 74,
- REG_H3 = 75,
- REG_H4 = 76,
- REG_H5 = 77,
- REG_H6 = 78,
- REG_H7 = 79,
- REG_H8 = 80,
- REG_H9 = 81,
- REG_H10 = 82,
- REG_H11 = 83,
- REG_H12 = 84,
- REG_H13 = 85,
- REG_H14 = 86,
- REG_H15 = 87,
- REG_H16 = 88,
- REG_H17 = 89,
- REG_H18 = 90,
- REG_H19 = 91,
- REG_H20 = 92,
- REG_H21 = 93,
- REG_H22 = 94,
- REG_H23 = 95,
- REG_H24 = 96,
- REG_H25 = 97,
- REG_H26 = 98,
- REG_H27 = 99,
- REG_H28 = 100,
- REG_H29 = 101,
- REG_H30 = 102,
- REG_H31 = 103,
- REG_Q0 = 104,
- REG_Q1 = 105,
- REG_Q2 = 106,
- REG_Q3 = 107,
- REG_Q4 = 108,
- REG_Q5 = 109,
- REG_Q6 = 110,
- REG_Q7 = 111,
- REG_Q8 = 112,
- REG_Q9 = 113,
- REG_Q10 = 114,
- REG_Q11 = 115,
- REG_Q12 = 116,
- REG_Q13 = 117,
- REG_Q14 = 118,
- REG_Q15 = 119,
- REG_Q16 = 120,
- REG_Q17 = 121,
- REG_Q18 = 122,
- REG_Q19 = 123,
- REG_Q20 = 124,
- REG_Q21 = 125,
- REG_Q22 = 126,
- REG_Q23 = 127,
- REG_Q24 = 128,
- REG_Q25 = 129,
- REG_Q26 = 130,
- REG_Q27 = 131,
- REG_Q28 = 132,
- REG_Q29 = 133,
- REG_Q30 = 134,
- REG_Q31 = 135,
- REG_S0 = 136,
- REG_S1 = 137,
- REG_S2 = 138,
- REG_S3 = 139,
- REG_S4 = 140,
- REG_S5 = 141,
- REG_S6 = 142,
- REG_S7 = 143,
- REG_S8 = 144,
- REG_S9 = 145,
- REG_S10 = 146,
- REG_S11 = 147,
- REG_S12 = 148,
- REG_S13 = 149,
- REG_S14 = 150,
- REG_S15 = 151,
- REG_S16 = 152,
- REG_S17 = 153,
- REG_S18 = 154,
- REG_S19 = 155,
- REG_S20 = 156,
- REG_S21 = 157,
- REG_S22 = 158,
- REG_S23 = 159,
- REG_S24 = 160,
- REG_S25 = 161,
- REG_S26 = 162,
- REG_S27 = 163,
- REG_S28 = 164,
- REG_S29 = 165,
- REG_S30 = 166,
- REG_S31 = 167,
- REG_W0 = 168,
- REG_W1 = 169,
- REG_W2 = 170,
- REG_W3 = 171,
- REG_W4 = 172,
- REG_W5 = 173,
- REG_W6 = 174,
- REG_W7 = 175,
- REG_W8 = 176,
- REG_W9 = 177,
- REG_W10 = 178,
- REG_W11 = 179,
- REG_W12 = 180,
- REG_W13 = 181,
- REG_W14 = 182,
- REG_W15 = 183,
- REG_W16 = 184,
- REG_W17 = 185,
- REG_W18 = 186,
- REG_W19 = 187,
- REG_W20 = 188,
- REG_W21 = 189,
- REG_W22 = 190,
- REG_W23 = 191,
- REG_W24 = 192,
- REG_W25 = 193,
- REG_W26 = 194,
- REG_W27 = 195,
- REG_W28 = 196,
- REG_W29 = 197,
- REG_W30 = 198,
- REG_X0 = 199,
- REG_X1 = 200,
- REG_X2 = 201,
- REG_X3 = 202,
- REG_X4 = 203,
- REG_X5 = 204,
- REG_X6 = 205,
- REG_X7 = 206,
- REG_X8 = 207,
- REG_X9 = 208,
- REG_X10 = 209,
- REG_X11 = 210,
- REG_X12 = 211,
- REG_X13 = 212,
- REG_X14 = 213,
- REG_X15 = 214,
- REG_X16 = 215,
- REG_X17 = 216,
- REG_X18 = 217,
- REG_X19 = 218,
- REG_X20 = 219,
- REG_X21 = 220,
- REG_X22 = 221,
- REG_X23 = 222,
- REG_X24 = 223,
- REG_X25 = 224,
- REG_X26 = 225,
- REG_X27 = 226,
- REG_X28 = 227,
- REG_V0 = 228,
- REG_V1 = 229,
- REG_V2 = 230,
- REG_V3 = 231,
- REG_V4 = 232,
- REG_V5 = 233,
- REG_V6 = 234,
- REG_V7 = 235,
- REG_V8 = 236,
- REG_V9 = 237,
- REG_V10 = 238,
- REG_V11 = 239,
- REG_V12 = 240,
- REG_V13 = 241,
- REG_V14 = 242,
- REG_V15 = 243,
- REG_V16 = 244,
- REG_V17 = 245,
- REG_V18 = 246,
- REG_V19 = 247,
- REG_V20 = 248,
- REG_V21 = 249,
- REG_V22 = 250,
- REG_V23 = 251,
- REG_V24 = 252,
- REG_V25 = 253,
- REG_V26 = 254,
- REG_V27 = 255,
- REG_V28 = 256,
- REG_V29 = 257,
- REG_V30 = 258,
- REG_V31 = 259,
-
- // pseudo registers
- REG_PC = 260,
- REG_CPACR_EL1 = 261,
-
- // thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
- REG_TPIDR_EL0 = 262,
- REG_TPIDRRO_EL0 = 263,
- REG_TPIDR_EL1 = 264,
- REG_PSTATE = 265,
-
- // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
- REG_ELR_EL0 = 266,
- REG_ELR_EL1 = 267,
- REG_ELR_EL2 = 268,
- REG_ELR_EL3 = 269,
-
- // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
- REG_SP_EL0 = 270,
- REG_SP_EL1 = 271,
- REG_SP_EL2 = 272,
- REG_SP_EL3 = 273,
-
- // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
- REG_TTBR0_EL1 = 274,
- REG_TTBR1_EL1 = 275,
- REG_ESR_EL0 = 276,
- REG_ESR_EL1 = 277,
- REG_ESR_EL2 = 278,
- REG_ESR_EL3 = 279,
- REG_FAR_EL0 = 280,
- REG_FAR_EL1 = 281,
- REG_FAR_EL2 = 282,
- REG_FAR_EL3 = 283,
- REG_PAR_EL1 = 284,
- REG_MAIR_EL1 = 285,
- REG_VBAR_EL0 = 286,
- REG_VBAR_EL1 = 287,
- REG_VBAR_EL2 = 288,
- REG_VBAR_EL3 = 289,
- REG_CP_REG = 290,
-
- // floating point control and status registers
- REG_FPCR = 291,
- REG_FPSR = 292,
- REG_ENDING = 293,
-
- // alias registers
- REG_IP0 = 215,
- REG_IP1 = 216,
- REG_FP = 1,
- REG_LR = 2,
-
- // ARM64 instructions
-
- INS_INVALID = 0,
- INS_MRS = 1,
- INS_MSR = 2,
- INS_SYS = 3,
- INS_SYSL = 4,
- INS_ENDING = 5,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Common.cs b/Ryujinx.Tests.Unicorn/Native/Const/Common.cs
deleted file mode 100644
index e4b59a489d..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Common.cs
+++ /dev/null
@@ -1,44 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Common
- {
- API_MAJOR = 2,
-
- API_MINOR = 0,
-
- API_PATCH = 0,
- API_EXTRA = 255,
- VERSION_MAJOR = 2,
-
- VERSION_MINOR = 0,
-
- VERSION_PATCH = 0,
- VERSION_EXTRA = 255,
- SECOND_SCALE = 1000000,
- MILISECOND_SCALE = 1000,
- QUERY_MODE = 1,
- QUERY_PAGE_SIZE = 2,
- QUERY_ARCH = 3,
- QUERY_TIMEOUT = 4,
-
- CTL_IO_NONE = 0,
- CTL_IO_WRITE = 1,
- CTL_IO_READ = 2,
- CTL_IO_READ_WRITE = 3,
-
- CTL_UC_MODE = 0,
- CTL_UC_PAGE_SIZE = 1,
- CTL_UC_ARCH = 2,
- CTL_UC_TIMEOUT = 3,
- CTL_UC_USE_EXITS = 4,
- CTL_UC_EXITS_CNT = 5,
- CTL_UC_EXITS = 6,
- CTL_CPU_MODEL = 7,
- CTL_TB_REQUEST_CACHE = 8,
- CTL_TB_REMOVE_CACHE = 9,
- CTL_TB_FLUSH = 10,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Error.cs b/Ryujinx.Tests.Unicorn/Native/Const/Error.cs
deleted file mode 100644
index 9cedb0fccc..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Error.cs
+++ /dev/null
@@ -1,31 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Error
- {
- OK = 0,
- NOMEM = 1,
- ARCH = 2,
- HANDLE = 3,
- MODE = 4,
- VERSION = 5,
- READ_UNMAPPED = 6,
- WRITE_UNMAPPED = 7,
- FETCH_UNMAPPED = 8,
- HOOK = 9,
- INSN_INVALID = 10,
- MAP = 11,
- WRITE_PROT = 12,
- READ_PROT = 13,
- FETCH_PROT = 14,
- ARG = 15,
- READ_UNALIGNED = 16,
- WRITE_UNALIGNED = 17,
- FETCH_UNALIGNED = 18,
- HOOK_EXIST = 19,
- RESOURCE = 20,
- EXCEPTION = 21,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Hook.cs b/Ryujinx.Tests.Unicorn/Native/Const/Hook.cs
deleted file mode 100644
index a6b9dca6ed..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Hook.cs
+++ /dev/null
@@ -1,33 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Hook
- {
- INTR = 1,
- INSN = 2,
- CODE = 4,
- BLOCK = 8,
- MEM_READ_UNMAPPED = 16,
- MEM_WRITE_UNMAPPED = 32,
- MEM_FETCH_UNMAPPED = 64,
- MEM_READ_PROT = 128,
- MEM_WRITE_PROT = 256,
- MEM_FETCH_PROT = 512,
- MEM_READ = 1024,
- MEM_WRITE = 2048,
- MEM_FETCH = 4096,
- MEM_READ_AFTER = 8192,
- INSN_INVALID = 16384,
- EDGE_GENERATED = 32768,
- TCG_OPCODE = 65536,
- MEM_UNMAPPED = 112,
- MEM_PROT = 896,
- MEM_READ_INVALID = 144,
- MEM_WRITE_INVALID = 288,
- MEM_FETCH_INVALID = 576,
- MEM_INVALID = 1008,
- MEM_VALID = 7168,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Memory.cs b/Ryujinx.Tests.Unicorn/Native/Const/Memory.cs
deleted file mode 100644
index a7d60e6115..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Memory.cs
+++ /dev/null
@@ -1,19 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Memory
- {
- READ = 16,
- WRITE = 17,
- FETCH = 18,
- READ_UNMAPPED = 19,
- WRITE_UNMAPPED = 20,
- FETCH_UNMAPPED = 21,
- WRITE_PROT = 22,
- READ_PROT = 23,
- FETCH_PROT = 24,
- READ_AFTER = 25,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Mode.cs b/Ryujinx.Tests.Unicorn/Native/Const/Mode.cs
deleted file mode 100644
index 804d01a97b..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Mode.cs
+++ /dev/null
@@ -1,35 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Mode
- {
- LITTLE_ENDIAN = 0,
- BIG_ENDIAN = 1073741824,
- ARM = 0,
- THUMB = 16,
- MCLASS = 32,
- V8 = 64,
- ARMBE8 = 1024,
- ARM926 = 128,
- ARM946 = 256,
- ARM1176 = 512,
- MICRO = 16,
- MIPS3 = 32,
- MIPS32R6 = 64,
- MIPS32 = 4,
- MIPS64 = 8,
- MODE_16 = 2,
- MODE_32 = 4,
- MODE_64 = 8,
- PPC32 = 4,
- PPC64 = 8,
- QPX = 16,
- SPARC32 = 4,
- SPARC64 = 8,
- V9 = 16,
- RISCV32 = 4,
- RISCV64 = 8,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Permission.cs b/Ryujinx.Tests.Unicorn/Native/Const/Permission.cs
deleted file mode 100644
index 19ddc4f270..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/Permission.cs
+++ /dev/null
@@ -1,14 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum Permission
- {
- NONE = 0,
- READ = 1,
- WRITE = 2,
- EXEC = 4,
- ALL = 7,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/TCG.cs b/Ryujinx.Tests.Unicorn/Native/Const/TCG.cs
deleted file mode 100644
index f38785db70..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Const/TCG.cs
+++ /dev/null
@@ -1,12 +0,0 @@
-// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
-
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native.Const
-{
- public enum TCG
- {
- OP_SUB = 0,
- OP_FLAG_CMP = 1,
- OP_FLAG_DIRECT = 2,
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Interface.cs b/Ryujinx.Tests.Unicorn/Native/Interface.cs
deleted file mode 100644
index 4e34ee8b38..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/Interface.cs
+++ /dev/null
@@ -1,101 +0,0 @@
-using Ryujinx.Tests.Unicorn.Native.Const;
-using System;
-using System.Diagnostics.CodeAnalysis;
-using System.IO;
-using System.Reflection;
-using System.Runtime.CompilerServices;
-using System.Runtime.InteropServices;
-
-namespace Ryujinx.Tests.Unicorn.Native
-{
- public static partial class Interface
- {
- public static bool IsUnicornAvailable { get; private set; } = true;
-
- private static IntPtr ImportResolver(string libraryName, Assembly assembly, DllImportSearchPath? searchPath)
- {
- if (libraryName == "unicorn")
- {
- string loadPath = $"{Path.GetDirectoryName(assembly.Location)}/";
- loadPath += OperatingSystem.IsWindows() ? $"{libraryName}.dll" : $"lib{libraryName}.so";
-
- if (!NativeLibrary.TryLoad(loadPath, out IntPtr libraryPtr))
- {
- IsUnicornAvailable = false;
- Console.Error.WriteLine($"ERROR: Could not find unicorn at: {loadPath}");
- }
-
- return libraryPtr;
- }
-
- // Otherwise, fallback to default import resolver.
- return IntPtr.Zero;
- }
-
- static Interface()
- {
- NativeLibrary.SetDllImportResolver(Assembly.GetExecutingAssembly(), ImportResolver);
- }
-
- public static void Checked(Error error)
- {
- if (error != Error.OK)
- {
- throw new UnicornException(error);
- }
- }
-
- public static void MarshalArrayOf<[DynamicallyAccessedMembers(DynamicallyAccessedMemberTypes.PublicConstructors | DynamicallyAccessedMemberTypes.NonPublicConstructors)] T>(IntPtr input, int length, out T[] output)
- {
- int size = Marshal.SizeOf();
-
- output = new T[length];
-
- for (int i = 0; i < length; i++)
- {
- IntPtr item = new IntPtr(input.ToInt64() + i * size);
-
- output[i] = Marshal.PtrToStructure(item);
- }
- }
-
- [LibraryImport("unicorn")]
- public static partial uint uc_version(out uint major, out uint minor);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_open(Arch arch, Mode mode, out IntPtr uc);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_close(IntPtr uc);
-
- [LibraryImport("unicorn")]
- public static partial IntPtr uc_strerror(Error err);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_reg_write(IntPtr uc, int regid, byte[] value);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_reg_read(IntPtr uc, int regid, byte[] value);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_mem_write(IntPtr uc, ulong address, byte[] bytes, ulong size);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_mem_read(IntPtr uc, ulong address, byte[] bytes, ulong size);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_emu_start(IntPtr uc, ulong begin, ulong until, ulong timeout, ulong count);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_mem_map(IntPtr uc, ulong address, ulong size, uint perms);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_mem_unmap(IntPtr uc, ulong address, ulong size);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_mem_protect(IntPtr uc, ulong address, ulong size, uint perms);
-
- [LibraryImport("unicorn")]
- public static partial Error uc_mem_regions(IntPtr uc, out IntPtr regions, out uint count);
- }
-}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornMemoryRegion.cs b/Ryujinx.Tests.Unicorn/Native/UnicornMemoryRegion.cs
deleted file mode 100644
index 7ee34a74a5..0000000000
--- a/Ryujinx.Tests.Unicorn/Native/UnicornMemoryRegion.cs
+++ /dev/null
@@ -1,13 +0,0 @@
-using System;
-using System.Runtime.InteropServices;
-
-namespace Ryujinx.Tests.Unicorn.Native
-{
- [StructLayout(LayoutKind.Sequential)]
- public struct UnicornMemoryRegion
- {
- public UInt64 begin; // begin address of the region (inclusive)
- public UInt64 end; // end address of the region (inclusive)
- public UInt32 perms; // memory permissions of the region
- }
-}
diff --git a/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj b/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj
index b3ee86d376..d925546fed 100644
--- a/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj
+++ b/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj
@@ -10,4 +10,8 @@
false
+
+
+
+
diff --git a/Ryujinx.Tests.Unicorn/UnicornAArch32.cs b/Ryujinx.Tests.Unicorn/UnicornAArch32.cs
index 3b8c1699e8..a095e66412 100644
--- a/Ryujinx.Tests.Unicorn/UnicornAArch32.cs
+++ b/Ryujinx.Tests.Unicorn/UnicornAArch32.cs
@@ -1,62 +1,45 @@
-using Ryujinx.Tests.Unicorn.Native;
-using Ryujinx.Tests.Unicorn.Native.Const;
-using System;
+using System;
+using UnicornEngine.Const;
namespace Ryujinx.Tests.Unicorn
{
public class UnicornAArch32 : IDisposable
{
- internal readonly IntPtr uc;
- private bool _isDisposed = false;
+ internal readonly UnicornEngine.Unicorn uc;
+ private bool _isDisposed;
- public IndexedProperty R
- {
- get
- {
- return new IndexedProperty(
- (int i) => GetX(i),
- (int i, uint value) => SetX(i, value));
- }
- }
+ public IndexedProperty R => new(GetX, SetX);
- public IndexedProperty Q
- {
- get
- {
- return new IndexedProperty(
- (int i) => GetQ(i),
- (int i, SimdValue value) => SetQ(i, value));
- }
- }
+ public IndexedProperty Q => new(GetQ, SetQ);
public uint LR
{
- get => GetRegister(Arm.REG_LR);
- set => SetRegister(Arm.REG_LR, value);
+ get => GetRegister(Arm.UC_ARM_REG_LR);
+ set => SetRegister(Arm.UC_ARM_REG_LR, value);
}
public uint SP
{
- get => GetRegister(Arm.REG_SP);
- set => SetRegister(Arm.REG_SP, value);
+ get => GetRegister(Arm.UC_ARM_REG_SP);
+ set => SetRegister(Arm.UC_ARM_REG_SP, value);
}
public uint PC
{
- get => GetRegister(Arm.REG_PC) & 0xfffffffeu;
- set => SetRegister(Arm.REG_PC, (value & 0xfffffffeu) | (ThumbFlag ? 1u : 0u));
+ get => GetRegister(Arm.UC_ARM_REG_PC) & 0xfffffffeu;
+ set => SetRegister(Arm.UC_ARM_REG_PC, (value & 0xfffffffeu) | (ThumbFlag ? 1u : 0u));
}
public uint CPSR
{
- get => GetRegister(Arm.REG_CPSR);
- set => SetRegister(Arm.REG_CPSR, value);
+ get => GetRegister(Arm.UC_ARM_REG_CPSR);
+ set => SetRegister(Arm.UC_ARM_REG_CPSR, value);
}
public int Fpscr
{
- get => (int)GetRegister(Arm.REG_FPSCR) | ((int)GetRegister(Arm.REG_FPSCR_NZCV));
- set => SetRegister(Arm.REG_FPSCR, (uint)value);
+ get => (int)GetRegister(Arm.UC_ARM_REG_FPSCR) | ((int)GetRegister(Arm.UC_ARM_REG_FPSCR_NZCV));
+ set => SetRegister(Arm.UC_ARM_REG_FPSCR, (uint)value);
}
public bool QFlag
@@ -95,16 +78,16 @@ namespace Ryujinx.Tests.Unicorn
set
{
CPSR = (CPSR & ~0x00000020u) | (value ? 0x00000020u : 0u);
- SetRegister(Arm.REG_PC, (GetRegister(Arm.REG_PC) & 0xfffffffeu) | (value ? 1u : 0u));
+ SetRegister(Arm.UC_ARM_REG_PC, (GetRegister(Arm.UC_ARM_REG_PC) & 0xfffffffeu) | (value ? 1u : 0u));
}
}
public UnicornAArch32()
{
- Interface.Checked(Interface.uc_open(Arch.ARM, Mode.LITTLE_ENDIAN, out uc));
+ uc = new UnicornEngine.Unicorn(Common.UC_ARCH_ARM, Common.UC_MODE_LITTLE_ENDIAN);
- SetRegister(Arm.REG_C1_C0_2, GetRegister(Arm.REG_C1_C0_2) | 0xf00000);
- SetRegister(Arm.REG_FPEXC, 0x40000000);
+ SetRegister(Arm.UC_ARM_REG_C1_C0_2, GetRegister(Arm.UC_ARM_REG_C1_C0_2) | 0xf00000);
+ SetRegister(Arm.UC_ARM_REG_FPEXC, 0x40000000);
}
~UnicornAArch32()
@@ -122,14 +105,15 @@ namespace Ryujinx.Tests.Unicorn
{
if (!_isDisposed)
{
- Interface.Checked(Interface.uc_close(uc));
+ uc.Close();
_isDisposed = true;
}
}
public void RunForCount(ulong count)
{
- Interface.Checked(Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
+ // FIXME: untilAddr should be 0xFFFFFFFFFFFFFFFFu
+ uc.EmuStart(this.PC, -1, 0, (long)count);
}
public void Step()
@@ -137,44 +121,44 @@ namespace Ryujinx.Tests.Unicorn
RunForCount(1);
}
- private static Arm[] XRegisters = new Arm[16]
+ private static int[] XRegisters =
{
- Arm.REG_R0,
- Arm.REG_R1,
- Arm.REG_R2,
- Arm.REG_R3,
- Arm.REG_R4,
- Arm.REG_R5,
- Arm.REG_R6,
- Arm.REG_R7,
- Arm.REG_R8,
- Arm.REG_R9,
- Arm.REG_R10,
- Arm.REG_R11,
- Arm.REG_R12,
- Arm.REG_R13,
- Arm.REG_R14,
- Arm.REG_R15,
+ Arm.UC_ARM_REG_R0,
+ Arm.UC_ARM_REG_R1,
+ Arm.UC_ARM_REG_R2,
+ Arm.UC_ARM_REG_R3,
+ Arm.UC_ARM_REG_R4,
+ Arm.UC_ARM_REG_R5,
+ Arm.UC_ARM_REG_R6,
+ Arm.UC_ARM_REG_R7,
+ Arm.UC_ARM_REG_R8,
+ Arm.UC_ARM_REG_R9,
+ Arm.UC_ARM_REG_R10,
+ Arm.UC_ARM_REG_R11,
+ Arm.UC_ARM_REG_R12,
+ Arm.UC_ARM_REG_R13,
+ Arm.UC_ARM_REG_R14,
+ Arm.UC_ARM_REG_R15,
};
- private static Arm[] QRegisters = new Arm[16]
+ private static int[] QRegisters =
{
- Arm.REG_Q0,
- Arm.REG_Q1,
- Arm.REG_Q2,
- Arm.REG_Q3,
- Arm.REG_Q4,
- Arm.REG_Q5,
- Arm.REG_Q6,
- Arm.REG_Q7,
- Arm.REG_Q8,
- Arm.REG_Q9,
- Arm.REG_Q10,
- Arm.REG_Q11,
- Arm.REG_Q12,
- Arm.REG_Q13,
- Arm.REG_Q14,
- Arm.REG_Q15
+ Arm.UC_ARM_REG_Q0,
+ Arm.UC_ARM_REG_Q1,
+ Arm.UC_ARM_REG_Q2,
+ Arm.UC_ARM_REG_Q3,
+ Arm.UC_ARM_REG_Q4,
+ Arm.UC_ARM_REG_Q5,
+ Arm.UC_ARM_REG_Q6,
+ Arm.UC_ARM_REG_Q7,
+ Arm.UC_ARM_REG_Q8,
+ Arm.UC_ARM_REG_Q9,
+ Arm.UC_ARM_REG_Q10,
+ Arm.UC_ARM_REG_Q11,
+ Arm.UC_ARM_REG_Q12,
+ Arm.UC_ARM_REG_Q13,
+ Arm.UC_ARM_REG_Q14,
+ Arm.UC_ARM_REG_Q15
};
public uint GetX(int index)
@@ -205,7 +189,7 @@ namespace Ryujinx.Tests.Unicorn
}
// Getting quadword registers from Unicorn A32 seems to be broken, so we combine its 2 doubleword registers instead.
- return GetVector((Arm)((int)Arm.REG_D0 + index * 2));
+ return GetVector(Arm.UC_ARM_REG_D0 + index * 2);
}
public void SetQ(int index, SimdValue value)
@@ -215,96 +199,85 @@ namespace Ryujinx.Tests.Unicorn
throw new ArgumentOutOfRangeException(nameof(index));
}
- SetVector((Arm)((int)Arm.REG_D0 + index * 2), value);
+ SetVector(Arm.UC_ARM_REG_D0 + index * 2, value);
}
- public uint GetRegister(Arm register)
+ public uint GetRegister(int register)
{
byte[] data = new byte[4];
- Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
+ uc.RegRead(register, data);
- return (uint)BitConverter.ToInt32(data, 0);
+ return BitConverter.ToUInt32(data, 0);
}
- public void SetRegister(Arm register, uint value)
+ public void SetRegister(int register, uint value)
{
byte[] data = BitConverter.GetBytes(value);
- Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
+ uc.RegWrite(register, data);
}
- public SimdValue GetVector(Arm register)
+ public SimdValue GetVector(int register)
{
byte[] data = new byte[8];
- Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
+ uc.RegRead(register, data);
ulong lo = BitConverter.ToUInt64(data, 0);
- Interface.Checked(Interface.uc_reg_read(uc, (int)register + 1, data));
+ uc.RegRead(register + 1, data);
ulong hi = BitConverter.ToUInt64(data, 0);
return new SimdValue(lo, hi);
}
- private void SetVector(Arm register, SimdValue value)
+ private void SetVector(int register, SimdValue value)
{
byte[] data = BitConverter.GetBytes(value.GetUInt64(0));
- Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
+ uc.RegWrite(register, data);
data = BitConverter.GetBytes(value.GetUInt64(1));
- Interface.Checked(Interface.uc_reg_write(uc, (int)register + 1, data));
+ uc.RegWrite(register + 1, data);
}
public byte[] MemoryRead(ulong address, ulong size)
{
byte[] value = new byte[size];
- Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
+ uc.MemRead((long)address, value);
return value;
}
public byte MemoryRead8(ulong address) => MemoryRead(address, 1)[0];
- public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
- public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
- public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
+ public ushort MemoryRead16(ulong address) => BitConverter.ToUInt16(MemoryRead(address, 2), 0);
+ public uint MemoryRead32(ulong address) => BitConverter.ToUInt32(MemoryRead(address, 4), 0);
+ public ulong MemoryRead64(ulong address) => BitConverter.ToUInt64(MemoryRead(address, 8), 0);
public void MemoryWrite(ulong address, byte[] value)
{
- Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
+ uc.MemWrite((long)address, value);
}
- public void MemoryWrite8(ulong address, byte value) => MemoryWrite(address, new byte[] { value });
- public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite8(ulong address, byte value) => MemoryWrite(address, new[] { value });
+ public void MemoryWrite16(ulong address, short value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite16(ulong address, ushort value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite32(ulong address, int value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite32(ulong address, uint value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite64(ulong address, long value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite64(ulong address, ulong value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
{
- Interface.Checked(Interface.uc_mem_map(uc, address, size, (uint)permissions));
+ uc.MemMap((long)address, (long)size, (int)permissions);
}
public void MemoryUnmap(ulong address, ulong size)
{
- Interface.Checked(Interface.uc_mem_unmap(uc, address, size));
+ uc.MemUnmap((long)address, (long)size);
}
public void MemoryProtect(ulong address, ulong size, MemoryPermission permissions)
{
- Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
- }
-
- public static bool IsAvailable()
- {
- try
- {
- Interface.uc_version(out _, out _);
- }
- catch (DllNotFoundException) { }
-
- return Interface.IsUnicornAvailable;
+ uc.MemProtect((long)address, (long)size, (int)permissions);
}
}
}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/UnicornAArch64.cs b/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
index 1784e7dffe..16dfd93bd0 100644
--- a/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
+++ b/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
@@ -1,68 +1,51 @@
-using Ryujinx.Tests.Unicorn.Native;
-using Ryujinx.Tests.Unicorn.Native.Const;
using System;
+using UnicornEngine.Const;
namespace Ryujinx.Tests.Unicorn
{
public class UnicornAArch64 : IDisposable
{
- internal readonly IntPtr uc;
- private bool _isDisposed = false;
+ internal readonly UnicornEngine.Unicorn uc;
+ private bool _isDisposed;
- public IndexedProperty X
- {
- get
- {
- return new IndexedProperty(
- (int i) => GetX(i),
- (int i, ulong value) => SetX(i, value));
- }
- }
+ public IndexedProperty X => new(GetX, SetX);
- public IndexedProperty Q
- {
- get
- {
- return new IndexedProperty(
- (int i) => GetQ(i),
- (int i, SimdValue value) => SetQ(i, value));
- }
- }
+ public IndexedProperty Q => new(GetQ, SetQ);
public ulong LR
{
- get => GetRegister(Arm64.REG_LR);
- set => SetRegister(Arm64.REG_LR, value);
+ get => GetRegister(Arm64.UC_ARM64_REG_LR);
+ set => SetRegister(Arm64.UC_ARM64_REG_LR, value);
}
public ulong SP
{
- get => GetRegister(Arm64.REG_SP);
- set => SetRegister(Arm64.REG_SP, value);
+ get => GetRegister(Arm64.UC_ARM64_REG_SP);
+ set => SetRegister(Arm64.UC_ARM64_REG_SP, value);
}
public ulong PC
{
- get => GetRegister(Arm64.REG_PC);
- set => SetRegister(Arm64.REG_PC, value);
+ get => GetRegister(Arm64.UC_ARM64_REG_PC);
+ set => SetRegister(Arm64.UC_ARM64_REG_PC, value);
}
public uint Pstate
{
- get => (uint)GetRegister(Arm64.REG_PSTATE);
- set => SetRegister(Arm64.REG_PSTATE, (uint)value);
+ get => (uint)GetRegister(Arm64.UC_ARM64_REG_PSTATE);
+ set => SetRegister(Arm64.UC_ARM64_REG_PSTATE, value);
}
public int Fpcr
{
- get => (int)GetRegister(Arm64.REG_FPCR);
- set => SetRegister(Arm64.REG_FPCR, (uint)value);
+ get => (int)GetRegister(Arm64.UC_ARM64_REG_FPCR);
+ set => SetRegister(Arm64.UC_ARM64_REG_FPCR, (uint)value);
}
public int Fpsr
{
- get => (int)GetRegister(Arm64.REG_FPSR);
- set => SetRegister(Arm64.REG_FPSR, (uint)value);
+ get => (int)GetRegister(Arm64.UC_ARM64_REG_FPSR);
+ set => SetRegister(Arm64.UC_ARM64_REG_FPSR, (uint)value);
}
public bool OverflowFlag
@@ -91,9 +74,9 @@ namespace Ryujinx.Tests.Unicorn
public UnicornAArch64()
{
- Interface.Checked(Interface.uc_open(Arch.ARM64, Mode.LITTLE_ENDIAN, out uc));
+ uc = new UnicornEngine.Unicorn(Common.UC_ARCH_ARM64, Common.UC_MODE_LITTLE_ENDIAN);
- SetRegister(Arm64.REG_CPACR_EL1, 0x00300000);
+ SetRegister(Arm64.UC_ARM64_REG_CPACR_EL1, 0x00300000);
}
~UnicornAArch64()
@@ -111,14 +94,15 @@ namespace Ryujinx.Tests.Unicorn
{
if (!_isDisposed)
{
- Interface.Checked(Interface.uc_close(uc));
+ uc.Close();
_isDisposed = true;
}
}
public void RunForCount(ulong count)
{
- Interface.Checked(Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
+ // FIXME: untilAddr should be 0xFFFFFFFFFFFFFFFFul
+ uc.EmuStart((long)this.PC, -1, 0, (long)count);
}
public void Step()
@@ -126,75 +110,75 @@ namespace Ryujinx.Tests.Unicorn
RunForCount(1);
}
- private static Arm64[] XRegisters = new Arm64[31]
+ private static int[] XRegisters =
{
- Arm64.REG_X0,
- Arm64.REG_X1,
- Arm64.REG_X2,
- Arm64.REG_X3,
- Arm64.REG_X4,
- Arm64.REG_X5,
- Arm64.REG_X6,
- Arm64.REG_X7,
- Arm64.REG_X8,
- Arm64.REG_X9,
- Arm64.REG_X10,
- Arm64.REG_X11,
- Arm64.REG_X12,
- Arm64.REG_X13,
- Arm64.REG_X14,
- Arm64.REG_X15,
- Arm64.REG_X16,
- Arm64.REG_X17,
- Arm64.REG_X18,
- Arm64.REG_X19,
- Arm64.REG_X20,
- Arm64.REG_X21,
- Arm64.REG_X22,
- Arm64.REG_X23,
- Arm64.REG_X24,
- Arm64.REG_X25,
- Arm64.REG_X26,
- Arm64.REG_X27,
- Arm64.REG_X28,
- Arm64.REG_X29,
- Arm64.REG_X30,
+ Arm64.UC_ARM64_REG_X0,
+ Arm64.UC_ARM64_REG_X1,
+ Arm64.UC_ARM64_REG_X2,
+ Arm64.UC_ARM64_REG_X3,
+ Arm64.UC_ARM64_REG_X4,
+ Arm64.UC_ARM64_REG_X5,
+ Arm64.UC_ARM64_REG_X6,
+ Arm64.UC_ARM64_REG_X7,
+ Arm64.UC_ARM64_REG_X8,
+ Arm64.UC_ARM64_REG_X9,
+ Arm64.UC_ARM64_REG_X10,
+ Arm64.UC_ARM64_REG_X11,
+ Arm64.UC_ARM64_REG_X12,
+ Arm64.UC_ARM64_REG_X13,
+ Arm64.UC_ARM64_REG_X14,
+ Arm64.UC_ARM64_REG_X15,
+ Arm64.UC_ARM64_REG_X16,
+ Arm64.UC_ARM64_REG_X17,
+ Arm64.UC_ARM64_REG_X18,
+ Arm64.UC_ARM64_REG_X19,
+ Arm64.UC_ARM64_REG_X20,
+ Arm64.UC_ARM64_REG_X21,
+ Arm64.UC_ARM64_REG_X22,
+ Arm64.UC_ARM64_REG_X23,
+ Arm64.UC_ARM64_REG_X24,
+ Arm64.UC_ARM64_REG_X25,
+ Arm64.UC_ARM64_REG_X26,
+ Arm64.UC_ARM64_REG_X27,
+ Arm64.UC_ARM64_REG_X28,
+ Arm64.UC_ARM64_REG_X29,
+ Arm64.UC_ARM64_REG_X30,
};
- private static Arm64[] QRegisters = new Arm64[32]
+ private static int[] QRegisters =
{
- Arm64.REG_Q0,
- Arm64.REG_Q1,
- Arm64.REG_Q2,
- Arm64.REG_Q3,
- Arm64.REG_Q4,
- Arm64.REG_Q5,
- Arm64.REG_Q6,
- Arm64.REG_Q7,
- Arm64.REG_Q8,
- Arm64.REG_Q9,
- Arm64.REG_Q10,
- Arm64.REG_Q11,
- Arm64.REG_Q12,
- Arm64.REG_Q13,
- Arm64.REG_Q14,
- Arm64.REG_Q15,
- Arm64.REG_Q16,
- Arm64.REG_Q17,
- Arm64.REG_Q18,
- Arm64.REG_Q19,
- Arm64.REG_Q20,
- Arm64.REG_Q21,
- Arm64.REG_Q22,
- Arm64.REG_Q23,
- Arm64.REG_Q24,
- Arm64.REG_Q25,
- Arm64.REG_Q26,
- Arm64.REG_Q27,
- Arm64.REG_Q28,
- Arm64.REG_Q29,
- Arm64.REG_Q30,
- Arm64.REG_Q31,
+ Arm64.UC_ARM64_REG_Q0,
+ Arm64.UC_ARM64_REG_Q1,
+ Arm64.UC_ARM64_REG_Q2,
+ Arm64.UC_ARM64_REG_Q3,
+ Arm64.UC_ARM64_REG_Q4,
+ Arm64.UC_ARM64_REG_Q5,
+ Arm64.UC_ARM64_REG_Q6,
+ Arm64.UC_ARM64_REG_Q7,
+ Arm64.UC_ARM64_REG_Q8,
+ Arm64.UC_ARM64_REG_Q9,
+ Arm64.UC_ARM64_REG_Q10,
+ Arm64.UC_ARM64_REG_Q11,
+ Arm64.UC_ARM64_REG_Q12,
+ Arm64.UC_ARM64_REG_Q13,
+ Arm64.UC_ARM64_REG_Q14,
+ Arm64.UC_ARM64_REG_Q15,
+ Arm64.UC_ARM64_REG_Q16,
+ Arm64.UC_ARM64_REG_Q17,
+ Arm64.UC_ARM64_REG_Q18,
+ Arm64.UC_ARM64_REG_Q19,
+ Arm64.UC_ARM64_REG_Q20,
+ Arm64.UC_ARM64_REG_Q21,
+ Arm64.UC_ARM64_REG_Q22,
+ Arm64.UC_ARM64_REG_Q23,
+ Arm64.UC_ARM64_REG_Q24,
+ Arm64.UC_ARM64_REG_Q25,
+ Arm64.UC_ARM64_REG_Q26,
+ Arm64.UC_ARM64_REG_Q27,
+ Arm64.UC_ARM64_REG_Q28,
+ Arm64.UC_ARM64_REG_Q29,
+ Arm64.UC_ARM64_REG_Q30,
+ Arm64.UC_ARM64_REG_Q31,
};
public ulong GetX(int index)
@@ -237,89 +221,78 @@ namespace Ryujinx.Tests.Unicorn
SetVector(QRegisters[index], value);
}
- private ulong GetRegister(Arm64 register)
+ private ulong GetRegister(int register)
{
byte[] data = new byte[8];
- Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
+ uc.RegRead(register, data);
- return (ulong)BitConverter.ToInt64(data, 0);
+ return BitConverter.ToUInt64(data, 0);
}
- private void SetRegister(Arm64 register, ulong value)
+ private void SetRegister(int register, ulong value)
{
byte[] data = BitConverter.GetBytes(value);
- Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
+ uc.RegWrite(register, data);
}
- private SimdValue GetVector(Arm64 register)
+ private SimdValue GetVector(int register)
{
byte[] data = new byte[16];
- Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
+ uc.RegRead(register, data);
return new SimdValue(data);
}
- private void SetVector(Arm64 register, SimdValue value)
+ private void SetVector(int register, SimdValue value)
{
byte[] data = value.ToArray();
- Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
+ uc.RegWrite(register, data);
}
public byte[] MemoryRead(ulong address, ulong size)
{
byte[] value = new byte[size];
- Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
+ uc.MemRead((long)address, value);
return value;
}
public byte MemoryRead8 (ulong address) => MemoryRead(address, 1)[0];
- public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
- public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
- public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
+ public ushort MemoryRead16(ulong address) => BitConverter.ToUInt16(MemoryRead(address, 2), 0);
+ public uint MemoryRead32(ulong address) => BitConverter.ToUInt32(MemoryRead(address, 4), 0);
+ public ulong MemoryRead64(ulong address) => BitConverter.ToUInt64(MemoryRead(address, 8), 0);
public void MemoryWrite(ulong address, byte[] value)
{
- Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
+ uc.MemWrite((long)address, value);
}
- public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new byte[]{value});
- public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
- public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new[]{ value });
+ public void MemoryWrite16(ulong address, short value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite16(ulong address, ushort value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite32(ulong address, int value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite32(ulong address, uint value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite64(ulong address, long value) => MemoryWrite(address, BitConverter.GetBytes(value));
+ public void MemoryWrite64(ulong address, ulong value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
{
- Interface.Checked(Interface.uc_mem_map(uc, address, size, (uint)permissions));
+ uc.MemMap((long)address, (long)size, (int)permissions);
}
public void MemoryUnmap(ulong address, ulong size)
{
- Interface.Checked(Interface.uc_mem_unmap(uc, address, size));
+ uc.MemUnmap((long)address, (long)size);
}
public void MemoryProtect(ulong address, ulong size, MemoryPermission permissions)
{
- Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
- }
-
- public static bool IsAvailable()
- {
- try
- {
- Interface.uc_version(out _, out _);
- }
- catch (DllNotFoundException) { }
-
- return Interface.IsUnicornAvailable;
+ uc.MemProtect((long)address, (long)size, (int)permissions);
}
}
}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/UnicornException.cs b/Ryujinx.Tests.Unicorn/UnicornException.cs
deleted file mode 100644
index b5c5f980eb..0000000000
--- a/Ryujinx.Tests.Unicorn/UnicornException.cs
+++ /dev/null
@@ -1,24 +0,0 @@
-using Ryujinx.Tests.Unicorn.Native.Const;
-using System;
-using System.Runtime.InteropServices;
-
-namespace Ryujinx.Tests.Unicorn
-{
- public class UnicornException : Exception
- {
- public readonly Error Error;
-
- internal UnicornException(Error error)
- {
- Error = error;
- }
-
- public override string Message
- {
- get
- {
- return Marshal.PtrToStringAnsi(Native.Interface.uc_strerror(Error));
- }
- }
- }
-}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/libs/README.md b/Ryujinx.Tests.Unicorn/libs/README.md
deleted file mode 100644
index d05291e5cb..0000000000
--- a/Ryujinx.Tests.Unicorn/libs/README.md
+++ /dev/null
@@ -1,20 +0,0 @@
-# Unicorn
-
-Unicorn is a CPU simulator with bindings in many languages, including
-C#/.NET.
-It is used by the Ryujinx test suite for comparative testing with its built-in
-CPU simulator, Armeilleure.
-
-## Windows
-
-On Windows, Unicorn is shipped as a pre-compiled dynamic library (`.dll`), licenced under the GPLv2.
-
-The source code for `windows/unicorn.dll` is available at: https://github.com/unicorn-engine/unicorn/tree/df3aa0fccbce9e1420e82110cbae5951755a0698
-
-## Linux
-
-On Windows, Unicorn is shipped as a pre-compiled shared object (`.so`), licenced under the GPLv2.
-
-The source code for `linux/unicorn.so` is available at: https://github.com/unicorn-engine/unicorn/tree/df3aa0fccbce9e1420e82110cbae5951755a0698
-
-See https://github.com/Ryujinx/Ryujinx/pull/1433 for details.
diff --git a/Ryujinx.Tests.Unicorn/libs/linux/libunicorn.so b/Ryujinx.Tests.Unicorn/libs/linux/libunicorn.so
deleted file mode 100644
index 8d0948af99..0000000000
Binary files a/Ryujinx.Tests.Unicorn/libs/linux/libunicorn.so and /dev/null differ
diff --git a/Ryujinx.Tests.Unicorn/libs/windows/unicorn.dll b/Ryujinx.Tests.Unicorn/libs/windows/unicorn.dll
deleted file mode 100644
index 1c84586e41..0000000000
Binary files a/Ryujinx.Tests.Unicorn/libs/windows/unicorn.dll and /dev/null differ
diff --git a/Ryujinx.Tests.Unicorn/unicorn_const_generator.py b/Ryujinx.Tests.Unicorn/unicorn_const_generator.py
deleted file mode 100644
index 813485fd27..0000000000
--- a/Ryujinx.Tests.Unicorn/unicorn_const_generator.py
+++ /dev/null
@@ -1,199 +0,0 @@
-#!/usr/bin/env python3
-# Unicorn Engine
-# By Dang Hoang Vu, 2013
-# Modified for Ryujinx from: https://github.com/unicorn-engine/unicorn/blob/6c1cbef6ac505d355033aef1176b684d02e1eb3a/bindings/const_generator.py
-from __future__ import print_function
-import sys, re, os
-
-include = [ 'arm.h', 'arm64.h', 'unicorn.h' ]
-split_common = [ 'ARCH', 'MODE', 'ERR', 'MEM', 'TCG', 'HOOK', 'PROT' ]
-
-template = {
- 'dotnet': {
- 'header': "// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT\n\n// ReSharper disable InconsistentNaming\nnamespace Ryujinx.Tests.Unicorn.Native.Const\n{\n public enum %s\n {\n",
- 'footer': " }\n}\n",
- 'line_format': ' %s = %s,\n',
- 'out_file': os.path.join(os.path.dirname(__file__), 'Native', 'Const', '%s.cs'),
- # prefixes for constant filenames of all archs - case sensitive
- 'arm.h': 'Arm',
- 'arm64.h': 'Arm64',
- 'unicorn.h': 'Common',
- # prefixes for filenames of split_common values - case sensitive
- 'ARCH': 'Arch',
- 'MODE': 'Mode',
- 'ERR': 'Error',
- 'MEM': 'Memory',
- 'TCG': 'TCG',
- 'HOOK': 'Hook',
- 'PROT': 'Permission',
- 'comment_open': ' //',
- 'comment_close': '',
- }
-}
-
-# markup for comments to be added to autogen files
-MARKUP = '//>'
-
-def gen(unicorn_repo_path):
- global include
- include_dir = os.path.join(unicorn_repo_path, 'include', 'unicorn')
- templ = template["dotnet"]
- for target in include:
- prefix = templ[target]
- outfile = open(templ['out_file'] %(prefix), 'wb') # open as binary prevents windows newlines
- outfile.write((templ['header'] % (prefix)).encode("utf-8"))
- if target == 'unicorn.h':
- prefix = ''
- for cat in split_common:
- with open(templ['out_file'] %(templ[cat]), 'wb') as file:
- file.write((templ['header'] %(templ[cat])).encode("utf-8"))
- with open(os.path.join(include_dir, target)) as f:
- lines = f.readlines()
-
- previous = {}
- count = 0
- skip = 0
- in_comment = False
-
- for lno, line in enumerate(lines):
- if "/*" in line:
- in_comment = True
- if "*/" in line:
- in_comment = False
- if in_comment:
- continue
- if skip > 0:
- # Due to clang-format, values may come up in the next line
- skip -= 1
- continue
- line = line.strip()
-
- if line.startswith(MARKUP): # markup for comments
- outfile.write(("\n%s%s%s\n" %(templ['comment_open'], \
- line.replace(MARKUP, ''), templ['comment_close'])).encode("utf-8"))
- continue
-
- if line == '' or line.startswith('//'):
- continue
-
- tmp = line.strip().split(',')
- if len(tmp) >= 2 and tmp[0] != "#define" and not tmp[0].startswith("UC_"):
- continue
- for t in tmp:
- t = t.strip()
- if not t or t.startswith('//'): continue
- f = re.split('\s+', t)
-
- # parse #define UC_TARGET (num)
- define = False
- if f[0] == '#define' and len(f) >= 3:
- define = True
- f.pop(0)
- f.insert(1, '=')
- if f[0].startswith("UC_" + prefix.upper()) or f[0].startswith("UC_CPU"):
- if len(f) > 1 and f[1] not in ('//', '='):
- print("WARNING: Unable to convert %s" % f)
- print(" Line =", line)
- continue
- elif len(f) > 1 and f[1] == '=':
- # Like:
- # UC_A =
- # (1 << 2)
- # #define UC_B \
- # (UC_A | UC_C)
- # Let's search the next line
- if len(f) == 2:
- if lno == len(lines) - 1:
- print("WARNING: Unable to convert %s" % f)
- print(" Line =", line)
- continue
- skip += 1
- next_line = lines[lno + 1]
- next_line_tmp = next_line.strip().split(",")
- rhs = next_line_tmp[0]
- elif f[-1] == "\\":
- idx = 0
- rhs = ""
- while True:
- idx += 1
- if lno + idx == len(lines):
- print("WARNING: Unable to convert %s" % f)
- print(" Line =", line)
- continue
- skip += 1
- next_line = lines[lno + idx]
- next_line_f = re.split('\s+', next_line.strip())
- if next_line_f[-1] == "\\":
- rhs += "".join(next_line_f[:-1])
- else:
- rhs += next_line.strip()
- break
- else:
- rhs = ''.join(f[2:])
- else:
- rhs = str(count)
-
-
- lhs = f[0].strip()
- #print(f'lhs: {lhs} rhs: {rhs} f:{f}')
- # evaluate bitshifts in constants e.g. "UC_X86 = 1 << 1"
- match = re.match(r'(?P\s*\d+\s*<<\s*\d+\s*)', rhs)
- if match:
- rhs = str(eval(match.group(1)))
- else:
- # evaluate references to other constants e.g. "UC_ARM_REG_X = UC_ARM_REG_SP"
- match = re.match(r'^([^\d]\w+)$', rhs)
- if match:
- rhs = previous[match.group(1)]
-
- if not rhs.isdigit():
- for k, v in previous.items():
- rhs = re.sub(r'\b%s\b' % k, v, rhs)
- rhs = str(eval(rhs))
-
- lhs_strip = re.sub(r'^UC_', '', lhs)
- count = int(rhs) + 1
-
- if target == "unicorn.h":
- matched_cat = False
- for cat in split_common:
- if lhs_strip.startswith(f"{cat}_"):
- with open(templ['out_file'] %(templ[cat]), 'ab') as cat_file:
- cat_lhs_strip = lhs_strip
- if not lhs_strip.lstrip(f"{cat}_").isnumeric():
- cat_lhs_strip = lhs_strip.replace(f"{cat}_", "", 1)
- cat_file.write(
- (templ['line_format'] % (cat_lhs_strip, rhs)).encode("utf-8"))
- matched_cat = True
- break
- if matched_cat:
- previous[lhs] = str(rhs)
- continue
-
- if (count == 1):
- outfile.write(("\n").encode("utf-8"))
-
- if lhs_strip.startswith(f"{prefix.upper()}_") and not lhs_strip.replace(f"{prefix.upper()}_", "", 1).isnumeric():
- lhs_strip = lhs_strip.replace(f"{prefix.upper()}_", "", 1)
-
- outfile.write((templ['line_format'] % (lhs_strip, rhs)).encode("utf-8"))
- previous[lhs] = str(rhs)
-
- outfile.write((templ['footer']).encode("utf-8"))
- outfile.close()
-
- if target == "unicorn.h":
- for cat in split_common:
- with open(templ['out_file'] %(templ[cat]), 'ab') as cat_file:
- cat_file.write(templ['footer'].encode('utf-8'))
-
-if __name__ == "__main__":
- if len(sys.argv) < 2:
- print("Usage:", sys.argv[0], " ")
- sys.exit(1)
- unicorn_repo_path = sys.argv[1]
- if os.path.isdir(unicorn_repo_path):
- print("Generating constants for dotnet")
- gen(unicorn_repo_path)
- else:
- print("Couldn't find unicorn repo at:", unicorn_repo_path)
diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs
index b64f74668e..979b313b04 100644
--- a/Ryujinx.Tests/Cpu/CpuTest.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest.cs
@@ -6,7 +6,6 @@ using Ryujinx.Cpu.Jit;
using Ryujinx.Memory;
using Ryujinx.Tests.Unicorn;
using System;
-
using MemoryPermission = Ryujinx.Tests.Unicorn.MemoryPermission;
namespace Ryujinx.Tests.Cpu
@@ -33,18 +32,10 @@ namespace Ryujinx.Tests.Cpu
private CpuContext _cpuContext;
- private static bool _unicornAvailable;
private UnicornAArch64 _unicornEmu;
private bool _usingMemory;
- [OneTimeSetUp]
- public void OneTimeSetup()
- {
- _unicornAvailable = UnicornAArch64.IsAvailable();
- Assume.That(_unicornAvailable, "Unicorn is not available");
- }
-
[SetUp]
public void Setup()
{
@@ -65,23 +56,17 @@ namespace Ryujinx.Tests.Cpu
Optimizations.AllowLcqInFunctionTable = false;
Optimizations.UseUnmanagedDispatchLoop = false;
- if (_unicornAvailable)
- {
- _unicornEmu = new UnicornAArch64();
- _unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.READ | MemoryPermission.EXEC);
- _unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.READ | MemoryPermission.WRITE);
- _unicornEmu.PC = CodeBaseAddress;
- }
+ _unicornEmu = new UnicornAArch64();
+ _unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Exec);
+ _unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Write);
+ _unicornEmu.PC = CodeBaseAddress;
}
[TearDown]
public void Teardown()
{
- if (_unicornAvailable)
- {
- _unicornEmu.Dispose();
- _unicornEmu = null;
- }
+ _unicornEmu.Dispose();
+ _unicornEmu = null;
_memory.DecrementReferenceCount();
_context.Dispose();
@@ -105,10 +90,7 @@ namespace Ryujinx.Tests.Cpu
{
_memory.Write(_currAddress, opcode);
- if (_unicornAvailable)
- {
- _unicornEmu.MemoryWrite32(_currAddress, opcode);
- }
+ _unicornEmu.MemoryWrite32(_currAddress, opcode);
_currAddress += 4;
}
@@ -158,38 +140,35 @@ namespace Ryujinx.Tests.Cpu
_context.Fpcr = (FPCR)fpcr;
_context.Fpsr = (FPSR)fpsr;
- if (_unicornAvailable)
- {
- _unicornEmu.X[0] = x0;
- _unicornEmu.X[1] = x1;
- _unicornEmu.X[2] = x2;
- _unicornEmu.X[3] = x3;
- _unicornEmu.SP = x31;
+ _unicornEmu.X[0] = x0;
+ _unicornEmu.X[1] = x1;
+ _unicornEmu.X[2] = x2;
+ _unicornEmu.X[3] = x3;
+ _unicornEmu.SP = x31;
- _unicornEmu.Q[0] = V128ToSimdValue(v0);
- _unicornEmu.Q[1] = V128ToSimdValue(v1);
- _unicornEmu.Q[2] = V128ToSimdValue(v2);
- _unicornEmu.Q[3] = V128ToSimdValue(v3);
- _unicornEmu.Q[4] = V128ToSimdValue(v4);
- _unicornEmu.Q[5] = V128ToSimdValue(v5);
- _unicornEmu.Q[30] = V128ToSimdValue(v30);
- _unicornEmu.Q[31] = V128ToSimdValue(v31);
+ _unicornEmu.Q[0] = V128ToSimdValue(v0);
+ _unicornEmu.Q[1] = V128ToSimdValue(v1);
+ _unicornEmu.Q[2] = V128ToSimdValue(v2);
+ _unicornEmu.Q[3] = V128ToSimdValue(v3);
+ _unicornEmu.Q[4] = V128ToSimdValue(v4);
+ _unicornEmu.Q[5] = V128ToSimdValue(v5);
+ _unicornEmu.Q[30] = V128ToSimdValue(v30);
+ _unicornEmu.Q[31] = V128ToSimdValue(v31);
- _unicornEmu.OverflowFlag = overflow;
- _unicornEmu.CarryFlag = carry;
- _unicornEmu.ZeroFlag = zero;
- _unicornEmu.NegativeFlag = negative;
+ _unicornEmu.OverflowFlag = overflow;
+ _unicornEmu.CarryFlag = carry;
+ _unicornEmu.ZeroFlag = zero;
+ _unicornEmu.NegativeFlag = negative;
- _unicornEmu.Fpcr = fpcr;
- _unicornEmu.Fpsr = fpsr;
- }
+ _unicornEmu.Fpcr = fpcr;
+ _unicornEmu.Fpsr = fpsr;
}
protected void ExecuteOpcodes(bool runUnicorn = true)
{
_cpuContext.Execute(_context, CodeBaseAddress);
- if (_unicornAvailable && runUnicorn)
+ if (runUnicorn)
{
_unicornEmu.RunForCount((_currAddress - CodeBaseAddress - 4) / 4);
}
@@ -239,10 +218,7 @@ namespace Ryujinx.Tests.Cpu
{
_memory.Write(DataBaseAddress + offset, data);
- if (_unicornAvailable)
- {
- _unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
- }
+ _unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
_usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
}
@@ -251,10 +227,7 @@ namespace Ryujinx.Tests.Cpu
{
_memory.Write(DataBaseAddress + offset, data);
- if (_unicornAvailable)
- {
- _unicornEmu.MemoryWrite8(DataBaseAddress + offset, data);
- }
+ _unicornEmu.MemoryWrite8(DataBaseAddress + offset, data);
_usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
}
@@ -331,11 +304,6 @@ namespace Ryujinx.Tests.Cpu
FpSkips fpSkips = FpSkips.None,
FpTolerances fpTolerances = FpTolerances.None)
{
- if (!_unicornAvailable)
- {
- return;
- }
-
if (IgnoreAllExcept_FpsrQc)
{
fpsrMask &= Fpsr.Qc;
diff --git a/Ryujinx.Tests/Cpu/CpuTest32.cs b/Ryujinx.Tests/Cpu/CpuTest32.cs
index 46ae3c7717..47dc9f8a85 100644
--- a/Ryujinx.Tests/Cpu/CpuTest32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest32.cs
@@ -6,7 +6,6 @@ using Ryujinx.Cpu.Jit;
using Ryujinx.Memory;
using Ryujinx.Tests.Unicorn;
using System;
-
using MemoryPermission = Ryujinx.Tests.Unicorn.MemoryPermission;
namespace Ryujinx.Tests.Cpu
@@ -27,19 +26,10 @@ namespace Ryujinx.Tests.Cpu
private ExecutionContext _context;
private CpuContext _cpuContext;
-
- private static bool _unicornAvailable;
private UnicornAArch32 _unicornEmu;
private bool _usingMemory;
- [OneTimeSetUp]
- public void OneTimeSetup()
- {
- _unicornAvailable = UnicornAArch32.IsAvailable();
- Assume.That(_unicornAvailable, "Unicorn is not available");
- }
-
[SetUp]
public void Setup()
{
@@ -61,23 +51,17 @@ namespace Ryujinx.Tests.Cpu
Optimizations.AllowLcqInFunctionTable = false;
Optimizations.UseUnmanagedDispatchLoop = false;
- if (_unicornAvailable)
- {
- _unicornEmu = new UnicornAArch32();
- _unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.READ | MemoryPermission.EXEC);
- _unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.READ | MemoryPermission.WRITE);
- _unicornEmu.PC = CodeBaseAddress;
- }
+ _unicornEmu = new UnicornAArch32();
+ _unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Exec);
+ _unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Write);
+ _unicornEmu.PC = CodeBaseAddress;
}
[TearDown]
public void Teardown()
{
- if (_unicornAvailable)
- {
- _unicornEmu.Dispose();
- _unicornEmu = null;
- }
+ _unicornEmu.Dispose();
+ _unicornEmu = null;
_memory.DecrementReferenceCount();
_context.Dispose();
@@ -101,10 +85,7 @@ namespace Ryujinx.Tests.Cpu
{
_memory.Write(_currAddress, opcode);
- if (_unicornAvailable)
- {
- _unicornEmu.MemoryWrite32(_currAddress, opcode);
- }
+ _unicornEmu.MemoryWrite32(_currAddress, opcode);
_currAddress += 4;
}
@@ -113,10 +94,7 @@ namespace Ryujinx.Tests.Cpu
{
_memory.Write(_currAddress, opcode);
- if (_unicornAvailable)
- {
- _unicornEmu.MemoryWrite16(_currAddress, opcode);
- }
+ _unicornEmu.MemoryWrite16(_currAddress, opcode);
_currAddress += 2;
}
@@ -169,40 +147,37 @@ namespace Ryujinx.Tests.Cpu
_context.SetPstateFlag(PState.TFlag, thumb);
- if (_unicornAvailable)
- {
- _unicornEmu.R[0] = r0;
- _unicornEmu.R[1] = r1;
- _unicornEmu.R[2] = r2;
- _unicornEmu.R[3] = r3;
- _unicornEmu.SP = sp;
+ _unicornEmu.R[0] = r0;
+ _unicornEmu.R[1] = r1;
+ _unicornEmu.R[2] = r2;
+ _unicornEmu.R[3] = r3;
+ _unicornEmu.SP = sp;
- _unicornEmu.Q[0] = V128ToSimdValue(v0);
- _unicornEmu.Q[1] = V128ToSimdValue(v1);
- _unicornEmu.Q[2] = V128ToSimdValue(v2);
- _unicornEmu.Q[3] = V128ToSimdValue(v3);
- _unicornEmu.Q[4] = V128ToSimdValue(v4);
- _unicornEmu.Q[5] = V128ToSimdValue(v5);
- _unicornEmu.Q[14] = V128ToSimdValue(v14);
- _unicornEmu.Q[15] = V128ToSimdValue(v15);
+ _unicornEmu.Q[0] = V128ToSimdValue(v0);
+ _unicornEmu.Q[1] = V128ToSimdValue(v1);
+ _unicornEmu.Q[2] = V128ToSimdValue(v2);
+ _unicornEmu.Q[3] = V128ToSimdValue(v3);
+ _unicornEmu.Q[4] = V128ToSimdValue(v4);
+ _unicornEmu.Q[5] = V128ToSimdValue(v5);
+ _unicornEmu.Q[14] = V128ToSimdValue(v14);
+ _unicornEmu.Q[15] = V128ToSimdValue(v15);
- _unicornEmu.QFlag = saturation;
- _unicornEmu.OverflowFlag = overflow;
- _unicornEmu.CarryFlag = carry;
- _unicornEmu.ZeroFlag = zero;
- _unicornEmu.NegativeFlag = negative;
+ _unicornEmu.QFlag = saturation;
+ _unicornEmu.OverflowFlag = overflow;
+ _unicornEmu.CarryFlag = carry;
+ _unicornEmu.ZeroFlag = zero;
+ _unicornEmu.NegativeFlag = negative;
- _unicornEmu.Fpscr = fpscr;
+ _unicornEmu.Fpscr = fpscr;
- _unicornEmu.ThumbFlag = thumb;
- }
+ _unicornEmu.ThumbFlag = thumb;
}
protected void ExecuteOpcodes(bool runUnicorn = true)
{
_cpuContext.Execute(_context, CodeBaseAddress);
- if (_unicornAvailable && runUnicorn)
+ if (runUnicorn)
{
_unicornEmu.RunForCount((_currAddress - CodeBaseAddress - 4) / 4);
}
@@ -322,10 +297,7 @@ namespace Ryujinx.Tests.Cpu
{
_memory.Write(DataBaseAddress + offset, data);
- if (_unicornAvailable)
- {
- _unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
- }
+ _unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
_usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
}
@@ -407,11 +379,6 @@ namespace Ryujinx.Tests.Cpu
FpSkips fpSkips = FpSkips.None,
FpTolerances fpTolerances = FpTolerances.None)
{
- if (!_unicornAvailable)
- {
- return;
- }
-
if (fpSkips != FpSkips.None)
{
ManageFpSkips(fpSkips);
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
index 0c4aa3b0e3..7318d97938 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
@@ -1,7 +1,6 @@
#define Alu
using NUnit.Framework;
-
using System.Collections.Generic;
namespace Ryujinx.Tests.Cpu
@@ -91,12 +90,10 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
-
[Test, Pairwise, Description("CLS , ")]
public void Cls_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource("_GenLeadingSignsX_")] [Random(RndCnt)] ulong xn)
+ [ValueSource(nameof(_GenLeadingSignsX_))] ulong xn)
{
uint opcode = 0xDAC01400; // CLS X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -111,7 +108,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLS , ")]
public void Cls_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource("_GenLeadingSignsW_")] [Random(RndCnt)] uint wn)
+ [ValueSource(nameof(_GenLeadingSignsW_))] uint wn)
{
uint opcode = 0x5AC01400; // CLS W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -126,7 +123,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ , ")]
public void Clz_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource("_GenLeadingZerosX_")] [Random(RndCnt)] ulong xn)
+ [ValueSource(nameof(_GenLeadingZerosX_))] ulong xn)
{
uint opcode = 0xDAC01000; // CLZ X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -141,7 +138,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ , ")]
public void Clz_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource("_GenLeadingZerosW_")] [Random(RndCnt)] uint wn)
+ [ValueSource(nameof(_GenLeadingZerosW_))] uint wn)
{
uint opcode = 0x5AC01000; // CLZ W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -157,7 +154,7 @@ namespace Ryujinx.Tests.Cpu
public void Rbit_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
{
uint opcode = 0xDAC00000; // RBIT X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -173,7 +170,7 @@ namespace Ryujinx.Tests.Cpu
public void Rbit_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn)
{
uint opcode = 0x5AC00000; // RBIT W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -189,7 +186,7 @@ namespace Ryujinx.Tests.Cpu
public void Rev16_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
{
uint opcode = 0xDAC00400; // REV16 X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -205,7 +202,7 @@ namespace Ryujinx.Tests.Cpu
public void Rev16_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn)
{
uint opcode = 0x5AC00400; // REV16 W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -221,7 +218,7 @@ namespace Ryujinx.Tests.Cpu
public void Rev32_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
{
uint opcode = 0xDAC00800; // REV32 X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -237,7 +234,7 @@ namespace Ryujinx.Tests.Cpu
public void Rev32_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn)
{
uint opcode = 0x5AC00800; // REV W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -253,7 +250,7 @@ namespace Ryujinx.Tests.Cpu
public void Rev64_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
{
uint opcode = 0xDAC00C00; // REV64 X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -266,4 +263,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
index c7537cd9b7..0d009e90e3 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Opcodes)"
private static uint[] _SU_H_AddSub_8_()
{
- return new uint[]
+ return new[]
{
0xe6100f90u, // SADD8 R0, R0, R0
0xe6100ff0u, // SSUB8 R0, R0, R0
@@ -27,7 +27,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Ssat_Usat_()
{
- return new uint[]
+ return new[]
{
0xe6a00010u, // SSAT R0, #1, R0, LSL #0
0xe6a00050u, // SSAT R0, #1, R0, ASR #32
@@ -38,7 +38,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Ssat16_Usat16_()
{
- return new uint[]
+ return new[]
{
0xe6a00f30u, // SSAT16 R0, #1, R0
0xe6e00f30u, // USAT16 R0, #0, R0
@@ -47,7 +47,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Lsr_Lsl_Asr_Ror_()
{
- return new uint[]
+ return new[]
{
0xe1b00030u, // LSRS R0, R0, R0
0xe1b00010u, // LSLS R0, R0, R0
@@ -63,7 +63,7 @@ namespace Ryujinx.Tests.Cpu
public void Rbit_32bit([Values(0u, 0xdu)] uint rd,
[Values(1u, 0xdu)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn)
{
uint opcode = 0xe6ff0f30u; // RBIT R0, R0
opcode |= ((rm & 15) << 0) | ((rd & 15) << 12);
@@ -76,10 +76,10 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Lsr_Lsl_Asr_Ror([ValueSource("_Lsr_Lsl_Asr_Ror_")] uint opcode,
+ public void Lsr_Lsl_Asr_Ror([ValueSource(nameof(_Lsr_Lsl_Asr_Ror_))] uint opcode,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
- [Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
+ 0x80000000u, 0xFFFFFFFFu)] uint shiftValue,
+ [Range(0, 31)] int shiftAmount)
{
uint rd = 0;
uint rm = 1;
@@ -130,13 +130,13 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Ssat_Usat([ValueSource("_Ssat_Usat_")] uint opcode,
+ public void Ssat_Usat([ValueSource(nameof(_Ssat_Usat_))] uint opcode,
[Values(0u, 0xdu)] uint rd,
[Values(1u, 0xdu)] uint rn,
[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint sat,
[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint shift,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn)
{
opcode |= ((rn & 15) << 0) | ((shift & 31) << 7) | ((rd & 15) << 12) | ((sat & 31) << 16);
@@ -148,12 +148,12 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Ssat16_Usat16([ValueSource("_Ssat16_Usat16_")] uint opcode,
+ public void Ssat16_Usat16([ValueSource(nameof(_Ssat16_Usat16_))] uint opcode,
[Values(0u, 0xdu)] uint rd,
[Values(1u, 0xdu)] uint rn,
[Values(0u, 7u, 8u, 0xfu)] uint sat,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn)
{
opcode |= ((rn & 15) << 0) | ((rd & 15) << 12) | ((sat & 15) << 16);
@@ -165,7 +165,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void SU_H_AddSub_8([ValueSource("_SU_H_AddSub_8_")] uint opcode,
+ public void SU_H_AddSub_8([ValueSource(nameof(_SU_H_AddSub_8_))] uint opcode,
[Values(0u, 0xdu)] uint rd,
[Values(1u)] uint rm,
[Values(2u)] uint rn,
@@ -206,4 +206,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs b/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
index eb94b84502..0265e52308 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
@@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Cpu
// - xor 0
// Only includes non-C variant, as the other can be tested with unicorn.
- return new CrcTest[]
+ return new[]
{
new CrcTest(0x00000000u, 0x00_00_00_00_00_00_00_00u, false, 0x00000000, 0x00000000, 0x00000000, 0x00000000),
new CrcTest(0x00000000u, 0x7f_ff_ff_ff_ff_ff_ff_ffu, false, 0x2d02ef8d, 0xbe2612ff, 0xdebb20e3, 0xa9de8355),
@@ -53,14 +53,12 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
-
[Test, Combinatorial]
public void Crc32_b_h_w_x([Values(0u)] uint rd,
[Values(1u)] uint rn,
[Values(2u)] uint rm,
[Range(0u, 3u)] uint size,
- [ValueSource("_CRC32_Test_Values_")] CrcTest test)
+ [ValueSource(nameof(_CRC32_Test_Values_))] CrcTest test)
{
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
@@ -85,11 +83,11 @@ namespace Ryujinx.Tests.Cpu
public void Crc32x([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((ulong)0x00_00_00_00_00_00_00_00,
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
- (ulong)0x80_00_00_00_00_00_00_00,
- (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
+ 0x80_00_00_00_00_00_00_00,
+ 0xFF_FF_FF_FF_FF_FF_FF_FF)] ulong xm)
{
uint opcode = 0x9AC04C00; // CRC32X W0, W0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -105,9 +103,9 @@ namespace Ryujinx.Tests.Cpu
public void Crc32w([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
- (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
+ 0x80_00_00_00, 0xFF_FF_FF_FF)] uint wm)
{
uint opcode = 0x1AC04800; // CRC32W W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -123,9 +121,9 @@ namespace Ryujinx.Tests.Cpu
public void Crc32h([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((ushort)0x00_00, (ushort)0x7F_FF,
- (ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
+ (ushort)0x80_00, (ushort)0xFF_FF)] ushort wm)
{
uint opcode = 0x1AC04400; // CRC32H W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -141,9 +139,9 @@ namespace Ryujinx.Tests.Cpu
public void Crc32b([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
+ (byte)0x80, (byte)0xFF)] byte wm)
{
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -159,11 +157,11 @@ namespace Ryujinx.Tests.Cpu
public void Crc32cx([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((ulong)0x00_00_00_00_00_00_00_00,
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
- (ulong)0x80_00_00_00_00_00_00_00,
- (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
+ 0x80_00_00_00_00_00_00_00,
+ 0xFF_FF_FF_FF_FF_FF_FF_FF)] ulong xm)
{
uint opcode = 0x9AC05C00; // CRC32CX W0, W0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -179,9 +177,9 @@ namespace Ryujinx.Tests.Cpu
public void Crc32cw([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
- (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
+ 0x80_00_00_00, 0xFF_FF_FF_FF)] uint wm)
{
uint opcode = 0x1AC05800; // CRC32CW W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -197,9 +195,9 @@ namespace Ryujinx.Tests.Cpu
public void Crc32ch([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((ushort)0x00_00, (ushort)0x7F_FF,
- (ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
+ (ushort)0x80_00, (ushort)0xFF_FF)] ushort wm)
{
uint opcode = 0x1AC05400; // CRC32CH W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -215,9 +213,9 @@ namespace Ryujinx.Tests.Cpu
public void Crc32cb([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
- [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ [Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
+ (byte)0x80, (byte)0xFF)] byte wm)
{
uint opcode = 0x1AC05000; // CRC32CB W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -234,9 +232,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9AC00C00; // SDIV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -253,9 +251,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
uint opcode = 0x1AC00C00; // SDIV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -272,9 +270,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9AC00800; // UDIV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -291,9 +289,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
uint opcode = 0x1AC00800; // UDIV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -306,4 +304,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs b/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs
index c402c4baa0..d92a952240 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs
@@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Cpu
// - bytes in order of increasing significance
// - xor 0
- return new CrcTest32[]
+ return new[]
{
new CrcTest32(0x00000000u, 0x00_00_00_00u, false, 0x00000000, 0x00000000, 0x00000000),
new CrcTest32(0x00000000u, 0x7f_ff_ff_ffu, false, 0x2d02ef8d, 0xbe2612ff, 0x3303a3c3),
@@ -70,7 +70,7 @@ namespace Ryujinx.Tests.Cpu
[Values(1u)] uint rn,
[Values(2u)] uint rm,
[Range(0u, 2u)] uint size,
- [ValueSource("_CRC32_Test_Values_")] CrcTest32 test)
+ [ValueSource(nameof(_CRC32_Test_Values_))] CrcTest32 test)
{
// Unicorn does not yet support 32bit crc instructions, so test against a known table of results/values.
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
index 9551ce2ce4..c97ef9ed04 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
@@ -8,17 +8,13 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestAluImm : CpuTest
{
#if AluImm
- private const int RndCnt = 2;
- private const int RndCntImm = 2;
- private const int RndCntImms = 2;
- private const int RndCntImmr = 2;
[Test, Pairwise, Description("ADD , , #{, }")]
public void Add_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
@@ -41,8 +37,8 @@ namespace Ryujinx.Tests.Cpu
public void Add_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
@@ -65,8 +61,8 @@ namespace Ryujinx.Tests.Cpu
public void Adds_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
@@ -89,8 +85,8 @@ namespace Ryujinx.Tests.Cpu
public void Adds_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
@@ -113,9 +109,9 @@ namespace Ryujinx.Tests.Cpu
public void And_N1_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 62u)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] uint immr) //
{
uint opcode = 0x92400000; // AND X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -132,9 +128,9 @@ namespace Ryujinx.Tests.Cpu
public void And_N0_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0x92000000; // AND X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -151,9 +147,9 @@ namespace Ryujinx.Tests.Cpu
public void And_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0x12000000; // AND W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -170,9 +166,9 @@ namespace Ryujinx.Tests.Cpu
public void Ands_N1_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 62u)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] uint immr) //
{
uint opcode = 0xF2400000; // ANDS X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -189,9 +185,9 @@ namespace Ryujinx.Tests.Cpu
public void Ands_N0_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -208,9 +204,9 @@ namespace Ryujinx.Tests.Cpu
public void Ands_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0x72000000; // ANDS W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -227,9 +223,9 @@ namespace Ryujinx.Tests.Cpu
public void Eor_N1_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 62u)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] uint immr) //
{
uint opcode = 0xD2400000; // EOR X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -246,9 +242,9 @@ namespace Ryujinx.Tests.Cpu
public void Eor_N0_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0xD2000000; // EOR X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -265,9 +261,9 @@ namespace Ryujinx.Tests.Cpu
public void Eor_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0x52000000; // EOR W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -284,9 +280,9 @@ namespace Ryujinx.Tests.Cpu
public void Orr_N1_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 62u)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] uint immr) //
{
uint opcode = 0xB2400000; // ORR X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -303,9 +299,9 @@ namespace Ryujinx.Tests.Cpu
public void Orr_N0_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0xB2000000; // ORR X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -322,9 +318,9 @@ namespace Ryujinx.Tests.Cpu
public void Orr_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 30u)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] uint immr) //
{
uint opcode = 0x32000000; // ORR W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -341,8 +337,8 @@ namespace Ryujinx.Tests.Cpu
public void Sub_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
@@ -365,8 +361,8 @@ namespace Ryujinx.Tests.Cpu
public void Sub_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
@@ -389,8 +385,8 @@ namespace Ryujinx.Tests.Cpu
public void Subs_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
@@ -413,8 +409,8 @@ namespace Ryujinx.Tests.Cpu
public void Subs_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
- [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
+ [Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
@@ -434,4 +430,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
index 440642c389..cc12f3871a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Opcodes)"
private static uint[] _opcodes()
{
- return new uint[]
+ return new[]
{
0xe2a00000u, // ADC R0, R0, #0
0xe2b00000u, // ADCS R0, R0, #0
@@ -33,10 +33,9 @@ namespace Ryujinx.Tests.Cpu
#endregion
private const int RndCnt = 2;
- private const int RndCntAmount = 2;
[Test, Pairwise]
- public void TestCpuTestAluImm32([ValueSource("_opcodes")] uint opcode,
+ public void TestCpuTestAluImm32([ValueSource(nameof(_opcodes))] uint opcode,
[Values(0u, 13u)] uint rd,
[Values(1u, 13u)] uint rn,
[Random(RndCnt)] uint imm,
@@ -53,4 +52,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
index 418dd56d23..20e0e396e6 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
@@ -8,18 +8,15 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestAluRs : CpuTest
{
#if AluRs
- private const int RndCnt = 2;
- private const int RndCntAmount = 2;
- private const int RndCntLsb = 2;
[Test, Pairwise, Description("ADC , , ")]
public void Adc_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values] bool carryIn)
{
uint opcode = 0x9A000000; // ADC X0, X0, X0
@@ -37,9 +34,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0x1A000000; // ADC W0, W0, W0
@@ -57,9 +54,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values] bool carryIn)
{
uint opcode = 0xBA000000; // ADCS X0, X0, X0
@@ -77,9 +74,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0x3A000000; // ADCS W0, W0, W0
@@ -97,11 +94,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0x8B000000; // ADD X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -119,11 +116,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x0B000000; // ADD W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -141,11 +138,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xAB000000; // ADDS X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -163,11 +160,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x2B000000; // ADDS W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -185,11 +182,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0x8A000000; // AND X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -207,11 +204,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x0A000000; // AND W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -229,11 +226,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xEA000000; // ANDS X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -251,11 +248,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x6A000000; // ANDS W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -273,9 +270,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9AC02800; // ASRV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -292,9 +289,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
uint opcode = 0x1AC02800; // ASRV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -311,11 +308,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0x8A200000; // BIC X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -333,11 +330,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x0A200000; // BIC W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -355,11 +352,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xEA200000; // BICS X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -377,11 +374,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x6A200000; // BICS W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -399,11 +396,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xCA200000; // EON X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -421,11 +418,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x4A200000; // EON W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -443,11 +440,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xCA000000; // EOR X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -465,11 +462,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x4A000000; // EOR W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -487,10 +484,10 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntLsb)] uint lsb)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
+ [Values(0u, 31u, 32u, 63u)] uint lsb)
{
uint opcode = 0x93C00000; // EXTR X0, X0, X0, #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -508,10 +505,10 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntLsb)] uint lsb)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
+ [Values(0u, 15u, 16u, 31u)] uint lsb)
{
uint opcode = 0x13800000; // EXTR W0, W0, W0, #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -529,9 +526,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9AC02000; // LSLV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -548,9 +545,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
uint opcode = 0x1AC02000; // LSLV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -567,9 +564,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9AC02400; // LSRV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -586,9 +583,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
uint opcode = 0x1AC02400; // LSRV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -605,11 +602,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xAA200000; // ORN X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -627,11 +624,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x2A200000; // ORN W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -649,11 +646,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xAA000000; // ORR X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -671,11 +668,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x2A000000; // ORR W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -693,9 +690,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9AC02C00; // RORV X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -712,9 +709,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
uint opcode = 0x1AC02C00; // RORV W0, W0, W0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -731,9 +728,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values] bool carryIn)
{
uint opcode = 0xDA000000; // SBC X0, X0, X0
@@ -751,9 +748,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0x5A000000; // SBC W0, W0, W0
@@ -771,9 +768,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values] bool carryIn)
{
uint opcode = 0xFA000000; // SBCS X0, X0, X0
@@ -791,9 +788,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0x7A000000; // SBCS W0, W0, W0
@@ -811,11 +808,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xCB000000; // SUB X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -833,11 +830,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x4B000000; // SUB W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -855,11 +852,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
+ [Values(0u, 31u, 32u, 63u)] uint amount)
{
uint opcode = 0xEB000000; // SUBS X0, X0, X0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -877,11 +874,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
uint opcode = 0x6B000000; // SUBS W0, W0, W0, LSL #0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -895,4 +892,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
index 25b2c96873..d241aac483 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Opcodes)"
private static uint[] _Add_Adds_Rsb_Rsbs_()
{
- return new uint[]
+ return new[]
{
0xe0800000u, // ADD R0, R0, R0, LSL #0
0xe0900000u, // ADDS R0, R0, R0, LSL #0
@@ -23,7 +23,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_()
{
- return new uint[]
+ return new[]
{
0xe0a00000u, // ADC R0, R0, R0
0xe0b00000u, // ADCS R0, R0, R0
@@ -35,8 +35,6 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
- private const int RndCntAmount = 2;
[Test, Pairwise]
public void Adc_Adcs_Rsc_Rscs_Sbc_Sbcs([ValueSource("_Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_")] uint opcode,
@@ -44,9 +42,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 13u)] uint rn,
[Values(2u, 13u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values] bool carryIn)
{
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
@@ -64,11 +62,11 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 13u)] uint rn,
[Values(2u, 13u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
+ [Values(0u, 15u, 16u, 31u)] uint amount)
{
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
@@ -81,4 +79,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
index 357a96ab94..d51e762098 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
@@ -8,16 +8,15 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestAluRx : CpuTest
{
#if AluRx
- private const int RndCnt = 2;
[Test, Pairwise, Description("ADD , , {, {#}}")]
public void Add_X_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
- (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
[Values(0b011u, 0b111u)] uint extend, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
{
@@ -44,9 +43,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -74,9 +73,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -104,9 +103,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -134,9 +133,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -164,9 +163,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -194,9 +193,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -224,9 +223,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
- (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
[Values(0b011u, 0b111u)] uint extend, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
{
@@ -244,9 +243,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -265,9 +264,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -286,9 +285,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -307,9 +306,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -328,9 +327,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -349,9 +348,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -370,9 +369,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
- (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
[Values(0b011u, 0b111u)] uint extend, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
{
@@ -399,9 +398,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -429,9 +428,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -459,9 +458,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -489,9 +488,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -519,9 +518,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -549,9 +548,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -579,9 +578,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
- (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
[Values(0b011u, 0b111u)] uint extend, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
{
@@ -599,9 +598,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -620,9 +619,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -641,9 +640,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -662,9 +661,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
- (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
+ 0x80000000, 0xFFFFFFFF)] uint wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -683,9 +682,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((ushort)0x0000, (ushort)0x7FFF,
- (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
+ (ushort)0x8000, (ushort)0xFFFF)] ushort wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -704,9 +703,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
+ 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
[Values((byte)0x00, (byte)0x7F,
- (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
+ (byte)0x80, (byte)0xFF)] byte wm,
[Values(0b000u, 0b001u, 0b010u, 0b011u, //
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
@@ -721,4 +720,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestBf32.cs b/Ryujinx.Tests/Cpu/CpuTestBf32.cs
index 66b8fc0623..871e7649fd 100644
--- a/Ryujinx.Tests/Cpu/CpuTestBf32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestBf32.cs
@@ -10,15 +10,13 @@ namespace Ryujinx.Tests.Cpu
{
#if Bf32
private const int RndCnt = 2;
- private const int RndCntImmr = 2;
- private const int RndCntImms = 2;
[Test, Pairwise, Description("BFC , #, #")]
public void Bfc([Values(0u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wd,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
+ 0x80000000u, 0xFFFFFFFFu)] uint wd,
+ [Values(0u, 15u, 16u, 31u)] uint lsb,
+ [Values(0u, 15u, 16u, 31u)] uint msb)
{
msb = Math.Max(lsb, msb); // Don't test unpredictable for now.
uint opcode = 0xe7c0001fu; // BFC R0, #0, #1
@@ -37,9 +35,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0xdu)] uint rn,
[Random(RndCnt)] uint wd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 31u)] uint lsb,
+ [Values(0u, 15u, 16u, 31u)] uint msb)
{
msb = Math.Max(lsb, msb); // Don't test unpredictable for now.
uint opcode = 0xe7c00010u; // BFI R0, R0, #0, #1
@@ -59,9 +57,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0xdu)] uint rn,
[Random(RndCnt)] uint wd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 31u)] uint lsb,
+ [Values(0u, 15u, 16u, 31u)] uint widthm1)
{
if (lsb + widthm1 > 31)
{
@@ -84,9 +82,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0xdu)] uint rn,
[Random(RndCnt)] uint wd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 31u)] uint lsb,
+ [Values(0u, 15u, 16u, 31u)] uint widthm1)
{
if (lsb + widthm1 > 31)
{
@@ -105,4 +103,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs
index 24f69036e4..c169ee41cd 100644
--- a/Ryujinx.Tests/Cpu/CpuTestBfm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs
@@ -9,17 +9,15 @@ namespace Ryujinx.Tests.Cpu
{
#if Bfm
private const int RndCnt = 2;
- private const int RndCntImmr = 2;
- private const int RndCntImms = 2;
[Test, Pairwise, Description("BFM , , #, #")]
public void Bfm_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Random(RndCnt)] ulong xd,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 63u)] uint immr,
+ [Values(0u, 31u, 32u, 63u)] uint imms)
{
uint opcode = 0xB3400000; // BFM X0, X0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -37,9 +35,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Random(RndCnt)] uint wd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 31u)] uint immr,
+ [Values(0u, 15u, 16u, 31u)] uint imms)
{
uint opcode = 0x33000000; // BFM W0, W0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -56,9 +54,9 @@ namespace Ryujinx.Tests.Cpu
public void Sbfm_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 63u)] uint immr,
+ [Values(0u, 31u, 32u, 63u)] uint imms)
{
uint opcode = 0x93400000; // SBFM X0, X0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -75,9 +73,9 @@ namespace Ryujinx.Tests.Cpu
public void Sbfm_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 31u)] uint immr,
+ [Values(0u, 15u, 16u, 31u)] uint imms)
{
uint opcode = 0x13000000; // SBFM W0, W0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -94,9 +92,9 @@ namespace Ryujinx.Tests.Cpu
public void Ubfm_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u, 32u, 63u)] uint immr,
+ [Values(0u, 31u, 32u, 63u)] uint imms)
{
uint opcode = 0xD3400000; // UBFM X0, X0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -113,9 +111,9 @@ namespace Ryujinx.Tests.Cpu
public void Ubfm_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 15u, 16u, 31u)] uint immr,
+ [Values(0u, 15u, 16u, 31u)] uint imms)
{
uint opcode = 0x53000000; // UBFM W0, W0, #0, #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -129,4 +127,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
index a2c7344944..2c431fb23a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
@@ -8,15 +8,13 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestCcmpImm : CpuTest
{
#if CcmpImm
- private const int RndCnt = 2;
- private const int RndCntImm = 2;
private const int RndCntNzcv = 2;
[Test, Pairwise, Description("CCMN , #, #, ")]
public void Ccmn_64bit([Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , #, #, ")]
public void Ccmn_32bit([Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 31u)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , #, #, ")]
public void Ccmp_64bit([Values(1u, 31u)] uint rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
- [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
+ [Values(0u, 31u)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , #, #, ")]
public void Ccmp_32bit([Values(1u, 31u)] uint rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
- [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
+ [Values(0u, 31u)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , #, ")]
public void Ccmn_64bit([Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")]
public void Csel_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, //
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, //
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, //
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, //
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , #{, LSL #}")]
public void Movk_64bit([Values(0u, 31u)] uint rd,
[Random(RndCnt)] ulong xd,
- [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
+ [Values(0u, 65535u)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint opcode = 0xF2800000; // MOVK X0, #0, LSL #0
@@ -31,7 +30,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("MOVK , #{, LSL #}")]
public void Movk_32bit([Values(0u, 31u)] uint rd,
[Random(RndCnt)] uint wd,
- [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
+ [Values(0u, 65535u)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint opcode = 0x72800000; // MOVK W0, #0, LSL #0
@@ -47,7 +46,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("MOVN , #{, LSL #}")]
public void Movn_64bit([Values(0u, 31u)] uint rd,
- [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
+ [Values(0u, 65535u)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint opcode = 0x92800000; // MOVN X0, #0, LSL #0
@@ -63,7 +62,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("MOVN , #{, LSL #}")]
public void Movn_32bit([Values(0u, 31u)] uint rd,
- [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
+ [Values(0u, 65535u)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint opcode = 0x12800000; // MOVN W0, #0, LSL #0
@@ -79,7 +78,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("MOVZ , #{, LSL #}")]
public void Movz_64bit([Values(0u, 31u)] uint rd,
- [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
+ [Values(0u, 65535u)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
@@ -95,7 +94,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("MOVZ , #{, LSL #}")]
public void Movz_32bit([Values(0u, 31u)] uint rd,
- [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
+ [Values(0u, 65535u)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint opcode = 0x52800000; // MOVZ W0, #0, LSL #0
@@ -110,4 +109,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestMul.cs b/Ryujinx.Tests/Cpu/CpuTestMul.cs
index 4ad7cf1104..c94bcbdb6e 100644
--- a/Ryujinx.Tests/Cpu/CpuTestMul.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestMul.cs
@@ -8,19 +8,17 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestMul : CpuTest
{
#if Mul
- private const int RndCnt = 2;
-
[Test, Pairwise, Description("MADD , , , ")]
public void Madd_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
{
uint opcode = 0x9B000000; // MADD X0, X0, X0, X0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -38,11 +36,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
+ 0x80000000u, 0xFFFFFFFFu)] uint wa)
{
uint opcode = 0x1B000000; // MADD W0, W0, W0, W0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -60,11 +58,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
{
uint opcode = 0x9B008000; // MSUB X0, X0, X0, X0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -82,11 +80,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
+ 0x80000000u, 0xFFFFFFFFu)] uint wa)
{
uint opcode = 0x1B008000; // MSUB W0, W0, W0, W0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -104,11 +102,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
{
uint opcode = 0x9B200000; // SMADDL X0, W0, W0, X0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -126,11 +124,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
{
uint opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -148,11 +146,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
{
uint opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -170,11 +168,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 31u)] uint rm,
[Values(3u, 31u)] uint ra,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
{
uint opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -191,9 +189,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9B407C00; // SMULH X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -210,9 +208,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 31u)] uint rn,
[Values(2u, 31u)] uint rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
{
uint opcode = 0x9BC07C00; // UMULH X0, X0, X0
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -225,4 +223,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestMul32.cs b/Ryujinx.Tests/Cpu/CpuTestMul32.cs
index daa6d46074..0743e913cc 100644
--- a/Ryujinx.Tests/Cpu/CpuTestMul32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestMul32.cs
@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Opcodes)"
private static uint[] _Smlabb_Smlabt_Smlatb_Smlatt_()
{
- return new uint[]
+ return new[]
{
0xe1000080u, // SMLABB R0, R0, R0, R0
0xe10000C0u, // SMLABT R0, R0, R0, R0
@@ -23,7 +23,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Smlawb_Smlawt_()
{
- return new uint[]
+ return new[]
{
0xe1200080u, // SMLAWB R0, R0, R0, R0
0xe12000C0u, // SMLAWT R0, R0, R0, R0
@@ -32,7 +32,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Smulbb_Smulbt_Smultb_Smultt_()
{
- return new uint[]
+ return new[]
{
0xe1600080u, // SMULBB R0, R0, R0
0xe16000C0u, // SMULBT R0, R0, R0
@@ -43,7 +43,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Smulwb_Smulwt_()
{
- return new uint[]
+ return new[]
{
0xe12000a0u, // SMULWB R0, R0, R0
0xe12000e0u, // SMULWT R0, R0, R0
@@ -51,8 +51,6 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
-
[Test, Pairwise, Description("SMLA , , , ")]
public void Smla___32bit([ValueSource("_Smlabb_Smlabt_Smlatb_Smlatt_")] uint opcode,
[Values(0u, 0xdu)] uint rn,
@@ -60,11 +58,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 0xdu)] uint ra,
[Values(3u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
+ 0x80000000u, 0xFFFFFFFFu)] uint wa)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
@@ -82,11 +80,11 @@ namespace Ryujinx.Tests.Cpu
[Values(2u, 0xdu)] uint ra,
[Values(3u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+ 0x80000000u, 0xFFFFFFFFu)] uint wm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
+ 0x80000000u, 0xFFFFFFFFu)] uint wa)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
@@ -103,9 +101,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
@@ -122,9 +120,9 @@ namespace Ryujinx.Tests.Cpu
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+ 0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+ 0x80000000u, 0xFFFFFFFFu)] uint wm)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
@@ -136,4 +134,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 04110ec377..7c68c0fa18 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -1,9 +1,7 @@
#define Simd
using ARMeilleure.State;
-
using NUnit.Framework;
-
using System;
using System.Collections.Generic;
@@ -47,8 +45,8 @@ namespace Ryujinx.Tests.Cpu
private static byte GenLeadingZeros8(int cnt) // 0 <= cnt <= 8
{
- if (cnt == 8) return (byte)0;
- if (cnt == 7) return (byte)1;
+ if (cnt == 8) return 0;
+ if (cnt == 7) return 1;
byte rnd = TestContext.CurrentContext.Random.NextByte();
sbyte mask = sbyte.MinValue;
@@ -58,8 +56,8 @@ namespace Ryujinx.Tests.Cpu
private static ushort GenLeadingZeros16(int cnt) // 0 <= cnt <= 16
{
- if (cnt == 16) return (ushort)0;
- if (cnt == 15) return (ushort)1;
+ if (cnt == 16) return 0;
+ if (cnt == 15) return 1;
ushort rnd = TestContext.CurrentContext.Random.NextUShort();
short mask = short.MinValue;
@@ -82,96 +80,96 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Types)"
private static ulong[] _1B1H1S1D_()
{
- return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
- 0x0000000000000080ul, 0x00000000000000FFul,
- 0x0000000000007FFFul, 0x0000000000008000ul,
- 0x000000000000FFFFul, 0x000000007FFFFFFFul,
- 0x0000000080000000ul, 0x00000000FFFFFFFFul,
- 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
- 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x000000000000007Ful,
+ 0x0000000000000080ul, 0x00000000000000FFul,
+ 0x0000000000007FFFul, 0x0000000000008000ul,
+ 0x000000000000FFFFul, 0x000000007FFFFFFFul,
+ 0x0000000080000000ul, 0x00000000FFFFFFFFul,
+ 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
+ 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _1D_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _1H1S1D_()
{
- return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
- 0x0000000000008000ul, 0x000000000000FFFFul,
- 0x000000007FFFFFFFul, 0x0000000080000000ul,
- 0x00000000FFFFFFFFul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x0000000000007FFFul,
+ 0x0000000000008000ul, 0x000000000000FFFFul,
+ 0x000000007FFFFFFFul, 0x0000000080000000ul,
+ 0x00000000FFFFFFFFul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _1S_()
{
- return new ulong[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
- 0x0000000080000000ul, 0x00000000FFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
+ 0x0000000080000000ul, 0x00000000FFFFFFFFul };
}
private static ulong[] _2S_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _4H_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _4H2S1D_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B4H_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B4H2S_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B4H2S1D_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static uint[] _W_()
{
- return new uint[] { 0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu };
+ return new[] { 0x00000000u, 0x7FFFFFFFu,
+ 0x80000000u, 0xFFFFFFFFu };
}
private static ulong[] _X_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static IEnumerable _1H_F_()
@@ -347,10 +345,8 @@ namespace Ryujinx.Tests.Cpu
{
ulong grbg = TestContext.CurrentContext.Random.NextUInt();
- ulong rnd1 = (uint)BitConverter.SingleToInt32Bits(
- (float)((int)TestContext.CurrentContext.Random.NextUInt()));
- ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(
- (float)((uint)TestContext.CurrentContext.Random.NextUInt()));
+ ulong rnd1 = (uint)BitConverter.SingleToInt32Bits((int)TestContext.CurrentContext.Random.NextUInt());
+ ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(TestContext.CurrentContext.Random.NextUInt());
ulong rnd3 = GenNormalS();
ulong rnd4 = GenSubnormalS();
@@ -451,9 +447,9 @@ namespace Ryujinx.Tests.Cpu
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong rnd1 = (uint)BitConverter.SingleToInt32Bits(
- (float)((int)TestContext.CurrentContext.Random.NextUInt()));
+ (int)TestContext.CurrentContext.Random.NextUInt());
ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(
- (float)((uint)TestContext.CurrentContext.Random.NextUInt()));
+ TestContext.CurrentContext.Random.NextUInt());
ulong rnd3 = GenNormalS();
ulong rnd4 = GenSubnormalS();
@@ -554,9 +550,9 @@ namespace Ryujinx.Tests.Cpu
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong rnd1 = (ulong)BitConverter.DoubleToInt64Bits(
- (double)((long)TestContext.CurrentContext.Random.NextULong()));
+ (long)TestContext.CurrentContext.Random.NextULong());
ulong rnd2 = (ulong)BitConverter.DoubleToInt64Bits(
- (double)((ulong)TestContext.CurrentContext.Random.NextULong()));
+ TestContext.CurrentContext.Random.NextULong());
ulong rnd3 = GenNormalD();
ulong rnd4 = GenSubnormalD();
@@ -651,7 +647,7 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Opcodes)"
private static uint[] _SU_Add_Max_Min_V_V_8BB_4HH_()
{
- return new uint[]
+ return new[]
{
0x0E31B800u, // ADDV B0, V0.8B
0x0E30A800u, // SMAXV B0, V0.8B
@@ -663,7 +659,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Add_Max_Min_V_V_16BB_8HH_4SS_()
{
- return new uint[]
+ return new[]
{
0x4E31B800u, // ADDV B0, V0.16B
0x4E30A800u, // SMAXV B0, V0.16B
@@ -675,7 +671,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_S_()
{
- return new uint[]
+ return new[]
{
0x1E20C020u, // FABS S0, S1
0x1E214020u, // FNEG S0, S1
@@ -686,7 +682,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_D_()
{
- return new uint[]
+ return new[]
{
0x1E60C020u, // FABS D0, D1
0x1E614020u, // FNEG D0, D1
@@ -697,7 +693,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Abs_Neg_Sqrt_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x0EA0F800u, // FABS V0.2S, V0.2S
0x2EA0F800u, // FNEG V0.2S, V0.2S
@@ -707,7 +703,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Abs_Neg_Sqrt_V_2D_()
{
- return new uint[]
+ return new[]
{
0x4EE0F800u, // FABS V0.2D, V0.2D
0x6EE0F800u, // FNEG V0.2D, V0.2D
@@ -717,7 +713,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Add_Max_Min_Nm_P_S_2SS_()
{
- return new uint[]
+ return new[]
{
0x7E30D820u, // FADDP S0, V1.2S
0x7E30C820u, // FMAXNMP S0, V1.2S
@@ -727,7 +723,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Add_Max_Min_Nm_P_S_2DD_()
{
- return new uint[]
+ return new[]
{
0x7E70D820u, // FADDP D0, V1.2D
0x7E70C820u, // FMAXNMP D0, V1.2D
@@ -737,7 +733,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cm_EqGeGtLeLt_S_S_()
{
- return new uint[]
+ return new[]
{
0x5EA0D820u, // FCMEQ S0, S1, #0.0
0x7EA0C820u, // FCMGE S0, S1, #0.0
@@ -749,7 +745,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cm_EqGeGtLeLt_S_D_()
{
- return new uint[]
+ return new[]
{
0x5EE0D820u, // FCMEQ D0, D1, #0.0
0x7EE0C820u, // FCMGE D0, D1, #0.0
@@ -761,7 +757,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cm_EqGeGtLeLt_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x0EA0D800u, // FCMEQ V0.2S, V0.2S, #0.0
0x2EA0C800u, // FCMGE V0.2S, V0.2S, #0.0
@@ -773,7 +769,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cm_EqGeGtLeLt_V_2D_()
{
- return new uint[]
+ return new[]
{
0x4EE0D800u, // FCMEQ V0.2D, V0.2D, #0.0
0x6EE0C800u, // FCMGE V0.2D, V0.2D, #0.0
@@ -785,7 +781,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cmp_Cmpe_S_S_()
{
- return new uint[]
+ return new[]
{
0x1E202028u, // FCMP S1, #0.0
0x1E202038u // FCMPE S1, #0.0
@@ -794,7 +790,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cmp_Cmpe_S_D_()
{
- return new uint[]
+ return new[]
{
0x1E602028u, // FCMP D1, #0.0
0x1E602038u // FCMPE D1, #0.0
@@ -803,7 +799,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_S_SD_()
{
- return new uint[]
+ return new[]
{
0x1E22C020u // FCVT D0, S1
};
@@ -811,7 +807,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_S_DS_()
{
- return new uint[]
+ return new[]
{
0x1E624020u // FCVT S0, D1
};
@@ -819,7 +815,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_S_SH_()
{
- return new uint[]
+ return new[]
{
0x1E23C020u // FCVT H0, S1
};
@@ -827,7 +823,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_S_DH_()
{
- return new uint[]
+ return new[]
{
0x1E63C020u // FCVT H0, D1
};
@@ -835,7 +831,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_S_HS_()
{
- return new uint[]
+ return new[]
{
0x1EE24020u // FCVT S0, H1
};
@@ -843,7 +839,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_S_HD_()
{
- return new uint[]
+ return new[]
{
0x1EE2C020u // FCVT D0, H1
};
@@ -851,7 +847,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_ANZ_SU_S_S_()
{
- return new uint[]
+ return new[]
{
0x5E21C820u, // FCVTAS S0, S1
0x7E21C820u, // FCVTAU S0, S1
@@ -864,7 +860,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_ANZ_SU_S_D_()
{
- return new uint[]
+ return new[]
{
0x5E61C820u, // FCVTAS D0, D1
0x7E61C820u, // FCVTAU D0, D1
@@ -877,7 +873,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_ANZ_SU_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x0E21C800u, // FCVTAS V0.2S, V0.2S
0x2E21C800u, // FCVTAU V0.2S, V0.2S
@@ -891,7 +887,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvt_ANZ_SU_V_2D_()
{
- return new uint[]
+ return new[]
{
0x4E61C800u, // FCVTAS V0.2D, V0.2D
0x6E61C800u, // FCVTAU V0.2D, V0.2D
@@ -905,7 +901,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvtl_V_4H4S_8H4S_()
{
- return new uint[]
+ return new[]
{
0x0E217800u // FCVTL V0.4S, V0.4H
};
@@ -913,7 +909,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvtl_V_2S2D_4S2D_()
{
- return new uint[]
+ return new[]
{
0x0E617800u // FCVTL V0.2D, V0.2S
};
@@ -921,7 +917,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvtn_V_4S4H_4S8H_()
{
- return new uint[]
+ return new[]
{
0x0E216800u // FCVTN V0.4H, V0.4S
};
@@ -929,7 +925,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Cvtn_V_2D2S_2D4S_()
{
- return new uint[]
+ return new[]
{
0x0E616800u // FCVTN V0.2S, V0.2D
};
@@ -937,7 +933,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Max_Min_Nm_V_V_4SS_()
{
- return new uint[]
+ return new[]
{
0x6E30C800u, // FMAXNMV S0, V0.4S
0x6E30F800u, // FMAXV S0, V0.4S
@@ -948,7 +944,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_Ftoi_SW_()
{
- return new uint[]
+ return new[]
{
0x1E260000u // FMOV W0, S0
};
@@ -956,7 +952,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_Ftoi_DX_()
{
- return new uint[]
+ return new[]
{
0x9E660000u // FMOV X0, D0
};
@@ -964,7 +960,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_Ftoi1_DX_()
{
- return new uint[]
+ return new[]
{
0x9EAE0000u // FMOV X0, V0.D[1]
};
@@ -972,7 +968,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_Itof_WS_()
{
- return new uint[]
+ return new[]
{
0x1E270000u // FMOV S0, W0
};
@@ -980,7 +976,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_Itof_XD_()
{
- return new uint[]
+ return new[]
{
0x9E670000u // FMOV D0, X0
};
@@ -988,7 +984,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_Itof1_XD_()
{
- return new uint[]
+ return new[]
{
0x9EAF0000u // FMOV V0.D[1], X0
};
@@ -996,7 +992,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_S_S_()
{
- return new uint[]
+ return new[]
{
0x1E204020u // FMOV S0, S1
};
@@ -1004,7 +1000,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Mov_S_D_()
{
- return new uint[]
+ return new[]
{
0x1E604020u // FMOV D0, D1
};
@@ -1012,7 +1008,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Recpe_Rsqrte_S_S_()
{
- return new uint[]
+ return new[]
{
0x5EA1D820u, // FRECPE S0, S1
0x7EA1D820u // FRSQRTE S0, S1
@@ -1021,7 +1017,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Recpe_Rsqrte_S_D_()
{
- return new uint[]
+ return new[]
{
0x5EE1D820u, // FRECPE D0, D1
0x7EE1D820u // FRSQRTE D0, D1
@@ -1030,7 +1026,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Recpe_Rsqrte_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x0EA1D800u, // FRECPE V0.2S, V0.2S
0x2EA1D800u // FRSQRTE V0.2S, V0.2S
@@ -1039,7 +1035,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Recpe_Rsqrte_V_2D_()
{
- return new uint[]
+ return new[]
{
0x4EE1D800u, // FRECPE V0.2D, V0.2D
0x6EE1D800u // FRSQRTE V0.2D, V0.2D
@@ -1048,7 +1044,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_AMNPZ_S_S_()
{
- return new uint[]
+ return new[]
{
0x1E264020u, // FRINTA S0, S1
0x1E254020u, // FRINTM S0, S1
@@ -1060,7 +1056,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_AMNPZ_S_D_()
{
- return new uint[]
+ return new[]
{
0x1E664020u, // FRINTA D0, D1
0x1E654020u, // FRINTM D0, D1
@@ -1072,7 +1068,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_AMNPZ_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x2E218800u, // FRINTA V0.2S, V0.2S
0x0E219800u, // FRINTM V0.2S, V0.2S
@@ -1084,7 +1080,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_AMNPZ_V_2D_()
{
- return new uint[]
+ return new[]
{
0x6E618800u, // FRINTA V0.2D, V0.2D
0x4E619800u, // FRINTM V0.2D, V0.2D
@@ -1096,7 +1092,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_IX_S_S_()
{
- return new uint[]
+ return new[]
{
0x1E27C020u, // FRINTI S0, S1
0x1E274020u // FRINTX S0, S1
@@ -1105,7 +1101,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_IX_S_D_()
{
- return new uint[]
+ return new[]
{
0x1E67C020u, // FRINTI D0, D1
0x1E674020u // FRINTX D0, D1
@@ -1114,7 +1110,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_IX_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x2EA19800u, // FRINTI V0.2S, V0.2S
0x2E219800u // FRINTX V0.2S, V0.2S
@@ -1123,7 +1119,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _F_Rint_IX_V_2D_()
{
- return new uint[]
+ return new[]
{
0x6EE19800u, // FRINTI V0.2D, V0.2D
0x6E619800u // FRINTX V0.2D, V0.2D
@@ -1132,7 +1128,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Addl_V_V_8BH_4HS_()
{
- return new uint[]
+ return new[]
{
0x0E303800u, // SADDLV H0, V0.8B
0x2E303800u // UADDLV H0, V0.8B
@@ -1141,7 +1137,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Addl_V_V_16BH_8HS_4SD_()
{
- return new uint[]
+ return new[]
{
0x4E303800u, // SADDLV H0, V0.16B
0x6E303800u // UADDLV H0, V0.16B
@@ -1150,7 +1146,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_S_S_()
{
- return new uint[]
+ return new[]
{
0x5E21D820u, // SCVTF S0, S1
0x7E21D820u // UCVTF S0, S1
@@ -1159,7 +1155,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_S_D_()
{
- return new uint[]
+ return new[]
{
0x5E61D820u, // SCVTF D0, D1
0x7E61D820u // UCVTF D0, D1
@@ -1168,7 +1164,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_V_2S_4S_()
{
- return new uint[]
+ return new[]
{
0x0E21D800u, // SCVTF V0.2S, V0.2S
0x2E21D800u // UCVTF V0.2S, V0.2S
@@ -1177,7 +1173,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _SU_Cvt_F_V_2D_()
{
- return new uint[]
+ return new[]
{
0x4E61D800u, // SCVTF V0.2D, V0.2D
0x6E61D800u // UCVTF V0.2D, V0.2D
@@ -1186,7 +1182,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Sha1h_Sha1su1_V_()
{
- return new uint[]
+ return new[]
{
0x5E280800u, // SHA1H S0, S0
0x5E281800u // SHA1SU1 V0.4S, V0.4S
@@ -1195,7 +1191,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Sha256su0_V_()
{
- return new uint[]
+ return new[]
{
0x5E282800u // SHA256SU0 V0.4S, V0.4S
};
@@ -1211,8 +1207,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("ABS , ")]
public void Abs_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_1D_")] [Random(RndCnt)] ulong z,
- [ValueSource("_1D_")] [Random(RndCnt)] ulong a)
+ [ValueSource(nameof(_1D_))] ulong z,
+ [ValueSource(nameof(_1D_))] ulong a)
{
uint opcode = 0x5EE0B800; // ABS D0, D0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -1228,8 +1224,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("ABS ., .")]
public void Abs_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
- [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_8B4H2S_))] ulong z,
+ [ValueSource(nameof(_8B4H2S_))] ulong a,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint opcode = 0x0E20B800; // ABS V0.8B, V0.8B
@@ -1247,8 +1243,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("ABS ., .")]
public void Abs_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
- [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_8B4H2S1D_))] ulong z,
+ [ValueSource(nameof(_8B4H2S1D_))] ulong a,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint opcode = 0x4E20B800; // ABS V0.16B, V0.16B
@@ -1266,8 +1262,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("ADDP , .")]
public void Addp_S_2DD([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_1D_")] [Random(RndCnt)] ulong z,
- [ValueSource("_1D_")] [Random(RndCnt)] ulong a)
+ [ValueSource(nameof(_1D_))] ulong z,
+ [ValueSource(nameof(_1D_))] ulong a)
{
uint opcode = 0x5EF1B800; // ADDP D0, V0.2D
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -1281,11 +1277,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void SU_Add_Max_Min_V_V_8BB_4HH([ValueSource("_SU_Add_Max_Min_V_V_8BB_4HH_")] uint opcodes,
+ public void SU_Add_Max_Min_V_V_8BB_4HH([ValueSource(nameof(_SU_Add_Max_Min_V_V_8BB_4HH_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_8B4H_")] [Random(RndCnt)] ulong z,
- [ValueSource("_8B4H_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_8B4H_))] ulong z,
+ [ValueSource(nameof(_8B4H_))] ulong a,
[Values(0b00u, 0b01u)] uint size) // <8BB, 4HH>
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -1300,11 +1296,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void SU_Add_Max_Min_V_V_16BB_8HH_4SS([ValueSource("_SU_Add_Max_Min_V_V_16BB_8HH_4SS_")] uint opcodes,
+ public void SU_Add_Max_Min_V_V_16BB_8HH_4SS([ValueSource(nameof(_SU_Add_Max_Min_V_V_16BB_8HH_4SS_))] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
- [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_8B4H2S_))] ulong z,
+ [ValueSource(nameof(_8B4H2S_))] ulong a,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16BB, 8HH, 4SS>
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -1321,8 +1317,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLS ., .")]
public void Cls_V_8B_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
- [ValueSource("_GenLeadingSigns8B_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_8B_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_GenLeadingSigns8B_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
uint opcode = 0x0E204800; // CLS V0.8B, V0.8B
@@ -1340,8 +1336,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLS ., .")]
public void Cls_V_4H_8H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong z,
- [ValueSource("_GenLeadingSigns4H_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_GenLeadingSigns4H_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
uint opcode = 0x0E604800; // CLS V0.4H, V0.4H
@@ -1359,8 +1355,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLS ., .")]
public void Cls_V_2S_4S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong z,
- [ValueSource("_GenLeadingSigns2S_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_GenLeadingSigns2S_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
uint opcode = 0x0EA04800; // CLS V0.2S, V0.2S
@@ -1378,8 +1374,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ ., .")]
public void Clz_V_8B_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
- [ValueSource("_GenLeadingZeros8B_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_8B_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_GenLeadingZeros8B_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
uint opcode = 0x2E204800; // CLZ V0.8B, V0.8B
@@ -1397,8 +1393,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ ., .")]
public void Clz_V_4H_8H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong z,
- [ValueSource("_GenLeadingZeros4H_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_GenLeadingZeros4H_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
uint opcode = 0x2E604800; // CLZ V0.4H, V0.4H
@@ -1416,8 +1412,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ ., .")]
public void Clz_V_2S_4S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong z,
- [ValueSource("_GenLeadingZeros2S_")] [Random(RndCnt)] ulong a,
+ [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_GenLeadingZeros2S_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
uint opcode = 0x2EA04800; // CLZ V0.2S, V0.2S
@@ -1435,8 +1431,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CMEQ ,