From a5ad1e9a064877c05beacd25b64f0bd2e1e1d1dd Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Thu, 26 Apr 2018 04:20:22 +0200
Subject: [PATCH] Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V,
Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
---
ChocolArm64/AOpCodeTable.cs | 3 +
ChocolArm64/Instruction/AInstEmitAlu.cs | 22 +-
.../Instruction/AInstEmitSimdArithmetic.cs | 37 ++
.../Instruction/AInstEmitSimdLogical.cs | 11 +-
ChocolArm64/Instruction/ASoftFallback.cs | 10 +-
Ryujinx.Tests/Cpu/CpuTestSimd.cs | 84 ++++
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 365 +++++++++++++++++-
Ryujinx.Tests/Cpu/Tester/Instructions.cs | 245 ++++++++++++
Ryujinx.Tests/Cpu/Tester/Pseudocode.cs | 5 +
9 files changed, 749 insertions(+), 33 deletions(-)
diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index 4dc1575491..71a179d1b2 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -148,6 +148,8 @@ namespace ChocolArm64
Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg));
Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
+ Set("0x001110<<100000010010xxxxxxxxxx", AInstEmit.Cls_V, typeof(AOpCodeSimd));
+ Set("0x101110<<100000010010xxxxxxxxxx", AInstEmit.Clz_V, typeof(AOpCodeSimd));
Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
Set("0>001110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimdReg));
@@ -289,6 +291,7 @@ namespace ChocolArm64
Set("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd));
Set("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd));
Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
+ Set("0x001110111xxxxx000111xxxxxxxxxx", AInstEmit.Orn_V, typeof(AOpCodeSimdReg));
Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
Set("0x101110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Raddhn_V, typeof(AOpCodeSimdReg));
diff --git a/ChocolArm64/Instruction/AInstEmitAlu.cs b/ChocolArm64/Instruction/AInstEmitAlu.cs
index bacbfc9e81..4fba5094ec 100644
--- a/ChocolArm64/Instruction/AInstEmitAlu.cs
+++ b/ChocolArm64/Instruction/AInstEmitAlu.cs
@@ -106,14 +106,9 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
- if (Op.RegisterSize == ARegisterSize.Int32)
- {
- ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns32));
- }
- else
- {
- ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns64));
- }
+ Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
+
+ ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns));
Context.EmitStintzr(Op.Rd);
}
@@ -124,14 +119,9 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
- if (Op.RegisterSize == ARegisterSize.Int32)
- {
- ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros32));
- }
- else
- {
- ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros64));
- }
+ Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
+
+ ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros));
Context.EmitStintzr(Op.Rd);
}
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 2dce741073..f4dcf86405 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -109,6 +109,43 @@ namespace ChocolArm64.Instruction
EmitScalarSet(Context, Op.Rd, Op.Size);
}
+ public static void Cls_V(AILEmitterCtx Context)
+ {
+ MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingSigns));
+
+ EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
+ }
+
+ public static void Clz_V(AILEmitterCtx Context)
+ {
+ MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingZeros));
+
+ EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
+ }
+
+ private static void EmitCountLeadingBits(AILEmitterCtx Context, Action Emit)
+ {
+ AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+ int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+
+ for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
+ {
+ EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
+
+ Context.EmitLdc_I4(8 << Op.Size);
+
+ Emit();
+
+ EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ }
+
+ if (Op.RegisterSize == ARegisterSize.SIMD64)
+ {
+ EmitVectorZeroUpper(Context, Op.Rd);
+ }
+ }
+
public static void Cnt_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
index 967c3d3006..25aa873bdf 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
@@ -103,6 +103,15 @@ namespace ChocolArm64.Instruction
EmitVectorUnaryOpZx(Context, () => Context.Emit(OpCodes.Not));
}
+ public static void Orn_V(AILEmitterCtx Context)
+ {
+ EmitVectorBinaryOpZx(Context, () =>
+ {
+ Context.Emit(OpCodes.Not);
+ Context.Emit(OpCodes.Or);
+ });
+ }
+
public static void Orr_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Or));
@@ -136,4 +145,4 @@ namespace ChocolArm64.Instruction
}
}
}
-}
\ No newline at end of file
+}
diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs
index c08f253e96..497605a41d 100644
--- a/ChocolArm64/Instruction/ASoftFallback.cs
+++ b/ChocolArm64/Instruction/ASoftFallback.cs
@@ -20,18 +20,12 @@ namespace ChocolArm64.Instruction
Context.EmitCall(typeof(ASoftFallback), MthdName);
}
- public static uint CountLeadingSigns32(uint Value) => (uint)CountLeadingSigns(Value, 32);
- public static ulong CountLeadingSigns64(ulong Value) => (ulong)CountLeadingSigns(Value, 64);
-
- private static ulong CountLeadingSigns(ulong Value, int Size)
+ public static ulong CountLeadingSigns(ulong Value, int Size)
{
return CountLeadingZeros((Value >> 1) ^ Value, Size - 1);
}
- public static uint CountLeadingZeros32(uint Value) => (uint)CountLeadingZeros(Value, 32);
- public static ulong CountLeadingZeros64(ulong Value) => (ulong)CountLeadingZeros(Value, 64);
-
- private static ulong CountLeadingZeros(ulong Value, int Size)
+ public static ulong CountLeadingZeros(ulong Value, int Size)
{
int HighBit = Size - 1;
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 5fa3a72df2..c41301c7e0 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -179,6 +179,90 @@ namespace Ryujinx.Tests.Cpu
});
}
+ [Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
+ public void Cls_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
+ [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+ {
+ uint Opcode = 0x0E204820; // CLS V0.8B, V1.8B
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
+
+ AArch64.V(1, new Bits(A));
+ SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("CLS <Vd>.<T>, <Vn>.<T>")]
+ public void Cls_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
+ [ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
+ [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+ {
+ uint Opcode = 0x4E204820; // CLS V0.16B, V1.16B
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
+
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
+ public void Clz_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
+ [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+ {
+ uint Opcode = 0x2E204820; // CLZ V0.8B, V1.8B
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
+
+ AArch64.V(1, new Bits(A));
+ SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
+ public void Clz_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
+ [ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
+ [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+ {
+ uint Opcode = 0x6E204820; // CLZ V0.16B, V1.16B
+ Opcode |= ((size & 3) << 22);
+ Bits Op = new Bits(Opcode);
+
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
+
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
[Test, Description("NEG <V><d>, <V><n>")]
public void Neg_S_D([ValueSource("_1D_")] [Random(1)] ulong A)
{
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index 8c13c33a2c..322181809e 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -26,6 +26,20 @@ namespace Ryujinx.Tests.Cpu
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
+ private static ulong[] _4H2S1D_()
+ {
+ return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ }
+
+ private static ulong[] _8B_()
+ {
+ return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+ }
+
private static ulong[] _8B4H2S_()
{
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
@@ -42,14 +56,6 @@ namespace Ryujinx.Tests.Cpu
0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
-
- private static ulong[] _4H2S1D_()
- {
- return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
- }
#endregion
[Test, Description("ADD <V><d>, <V><n>, <V><m>")]
@@ -231,6 +237,349 @@ namespace Ryujinx.Tests.Cpu
});
}
+ [Test, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void And_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x0E221C20; // AND V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void And_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x4E221C20; // AND V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
+
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bic_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x0E621C20; // BIC V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bic_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x4E621C20; // BIC V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
+
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bif_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
+ [ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x2EE21C20; // BIF V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.Vpart(0, 0, new Bits(_Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bif_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
+ [ValueSource("_8B_")] [Random(1)] ulong _Z1,
+ [ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x6EE21C20; // BIF V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.Vpart(0, 0, new Bits(_Z0));
+ AArch64.Vpart(0, 1, new Bits(_Z1));
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bit_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
+ [ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x2EA21C20; // BIT V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.Vpart(0, 0, new Bits(_Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bit_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
+ [ValueSource("_8B_")] [Random(1)] ulong _Z1,
+ [ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x6EA21C20; // BIT V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.Vpart(0, 0, new Bits(_Z0));
+ AArch64.Vpart(0, 1, new Bits(_Z1));
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bsl_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
+ [ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x2E621C20; // BSL V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.Vpart(0, 0, new Bits(_Z));
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Bsl_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
+ [ValueSource("_8B_")] [Random(1)] ulong _Z1,
+ [ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x6E621C20; // BSL V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.Vpart(0, 0, new Bits(_Z0));
+ AArch64.Vpart(0, 1, new Bits(_Z1));
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Orn_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x0EE21C20; // ORN V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Orn_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x4EE21C20; // ORN V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
+
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
+ [Test, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Orr_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
+ [ValueSource("_8B_")] [Random(1)] ulong B)
+ {
+ uint Opcode = 0x0EA21C20; // ORR V0.8B, V1.8B, V2.8B
+ Bits Op = new Bits(Opcode);
+
+ AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
+ AVec V1 = new AVec { X0 = A };
+ AVec V2 = new AVec { X0 = B };
+ AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+ AArch64.V(1, new Bits(A));
+ AArch64.V(2, new Bits(B));
+ SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.Zero);
+ }
+
+ [Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+ public void Orr_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
+ [ValueSource("_8B_")] [Random(1)] ulong A1,
+ [ValueSource("_8B_")] [Random(1)] ulong B0,
+ [ValueSource("_8B_")] [Random(1)] ulong B1)
+ {
+ uint Opcode = 0x4EA21C20; // ORR V0.16B, V1.16B, V2.16B
+ Bits Op = new Bits(Opcode);
+
+ AVec V1 = new AVec { X0 = A0, X1 = A1 };
+ AVec V2 = new AVec { X0 = B0, X1 = B1 };
+ AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
+
+ AArch64.Vpart(1, 0, new Bits(A0));
+ AArch64.Vpart(1, 1, new Bits(A1));
+ AArch64.Vpart(2, 0, new Bits(B0));
+ AArch64.Vpart(2, 1, new Bits(B1));
+ SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+ Assert.Multiple(() =>
+ {
+ Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+ Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+ });
+ }
+
[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
public void Raddhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
[ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs
index e866a9a0dd..7439aa8382 100644
--- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs
+++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs
@@ -1699,6 +1699,7 @@ namespace Ryujinx.Tests.Cpu.Tester
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
+
BigInteger element;
for (int e = 0; e <= elements - 1; e++)
@@ -1742,6 +1743,7 @@ namespace Ryujinx.Tests.Cpu.Tester
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
+
BigInteger element;
for (int e = 0; e <= elements - 1; e++)
@@ -1810,6 +1812,90 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, Reduce(op, operand, esize));
}
+ // https://meriac.github.io/archex/A64_v83A_ISA/cls_advsimd.xml
+ public static void Cls_V(bool Q, Bits size, Bits Rn, Bits Rd)
+ {
+ bool U = false;
+
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+
+ /* if size == '11' then ReservedValue(); */
+
+ int esize = 8 << (int)UInt(size);
+ int datasize = (Q ? 128 : 64);
+ int elements = datasize / esize;
+
+ CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits result = new Bits(datasize);
+ Bits operand = V(datasize, n);
+
+ BigInteger count;
+
+ for (int e = 0; e <= elements - 1; e++)
+ {
+ if (countop == CountOp.CountOp_CLS)
+ {
+ count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize));
+ }
+ else
+ {
+ count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize));
+ }
+
+ Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
+ }
+
+ V(d, result);
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/clz_advsimd.xml
+ public static void Clz_V(bool Q, Bits size, Bits Rn, Bits Rd)
+ {
+ bool U = true;
+
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+
+ /* if size == '11' then ReservedValue(); */
+
+ int esize = 8 << (int)UInt(size);
+ int datasize = (Q ? 128 : 64);
+ int elements = datasize / esize;
+
+ CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits result = new Bits(datasize);
+ Bits operand = V(datasize, n);
+
+ BigInteger count;
+
+ for (int e = 0; e <= elements - 1; e++)
+ {
+ if (countop == CountOp.CountOp_CLS)
+ {
+ count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize));
+ }
+ else
+ {
+ count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize));
+ }
+
+ Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
+ }
+
+ V(d, result);
+ }
+
// https://meriac.github.io/archex/A64_v83A_ISA/neg_advsimd.xml#NEG_asisdmisc_R
public static void Neg_S(Bits size, Bits Rn, Bits Rd)
{
@@ -1832,6 +1918,7 @@ namespace Ryujinx.Tests.Cpu.Tester
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
+
BigInteger element;
for (int e = 0; e <= elements - 1; e++)
@@ -1875,6 +1962,7 @@ namespace Ryujinx.Tests.Cpu.Tester
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
+
BigInteger element;
for (int e = 0; e <= elements - 1; e++)
@@ -2077,6 +2165,163 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
+ // https://meriac.github.io/archex/A64_v83A_ISA/and_advsimd.xml
+ public static void And_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+
+ Bits result = AND(operand1, operand2);
+
+ V(d, result);
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/bic_advsimd_reg.xml
+ public static void Bic_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+
+ operand2 = NOT(operand2);
+
+ Bits result = AND(operand1, operand2);
+
+ V(d, result);
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/bif_advsimd.xml
+ public static void Bif_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1;
+ Bits operand3;
+ Bits operand4 = V(datasize, n);
+
+ operand1 = V(datasize, d);
+ operand3 = NOT(V(datasize, m));
+
+ V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/bit_advsimd.xml
+ public static void Bit_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1;
+ Bits operand3;
+ Bits operand4 = V(datasize, n);
+
+ operand1 = V(datasize, d);
+ operand3 = V(datasize, m);
+
+ V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/bsl_advsimd.xml
+ public static void Bsl_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1;
+ Bits operand3;
+ Bits operand4 = V(datasize, n);
+
+ operand1 = V(datasize, m);
+ operand3 = V(datasize, d);
+
+ V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/orn_advsimd.xml
+ public static void Orn_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+
+ operand2 = NOT(operand2);
+
+ Bits result = OR(operand1, operand2);
+
+ V(d, result);
+ }
+
+ // https://meriac.github.io/archex/A64_v83A_ISA/orr_advsimd_reg.xml
+ public static void Orr_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
+ {
+ /* Decode */
+ int d = (int)UInt(Rd);
+ int n = (int)UInt(Rn);
+ int m = (int)UInt(Rm);
+
+ int datasize = (Q ? 128 : 64);
+
+ /* Operation */
+ /* CheckFPAdvSIMDEnabled64(); */
+
+ Bits operand1 = V(datasize, n);
+ Bits operand2 = V(datasize, m);
+
+ Bits result = OR(operand1, operand2);
+
+ V(d, result);
+ }
+
// https://meriac.github.io/archex/A64_v83A_ISA/raddhn_advsimd.xml
public static void Raddhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
diff --git a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
index cfe8aa3d6e..72e0bd7804 100644
--- a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
+++ b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
@@ -253,6 +253,11 @@ namespace Ryujinx.Tests.Cpu.Tester
}
#endregion
+#region "instrs/countop/"
+ // #CountOp
+ public enum CountOp {CountOp_CLZ, CountOp_CLS, CountOp_CNT};
+#endregion
+
#region "instrs/extendreg/"
/* #impl-aarch64.DecodeRegExtend.1 */
public static ExtendType DecodeRegExtend(Bits op)