diff --git a/src/Ryujinx.Tests/Audio/Renderer/Dsp/ResamplerTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Dsp/ResamplerTests.cs
index 364837ee08..0624f3401b 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Dsp/ResamplerTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Dsp/ResamplerTests.cs
@@ -1,14 +1,7 @@
using NUnit.Framework;
using Ryujinx.Audio.Renderer.Dsp;
using Ryujinx.Audio.Renderer.Parameter;
-using Ryujinx.Audio.Renderer.Server.Upsampler;
using System;
-using System.Collections.Generic;
-using System.IO;
-using System.Linq;
-using System.Runtime.CompilerServices;
-using System.Text;
-using System.Threading.Tasks;
namespace Ryujinx.Tests.Audio.Renderer.Dsp
{
@@ -41,8 +34,8 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
/// The resampler quality to use
private static void DoResamplingTest(int inputRate, int outputRate, VoiceInParameter.SampleRateConversionQuality quality)
{
- float inputSampleRate = (float)inputRate;
- float outputSampleRate = (float)outputRate;
+ float inputSampleRate = inputRate;
+ float outputSampleRate = outputRate;
int inputSampleCount = inputRate;
int outputSampleCount = outputRate;
short[] inputBuffer = new short[inputSampleCount + 100]; // add some safety buffer at the end
@@ -50,7 +43,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
for (int sample = 0; sample < inputBuffer.Length; sample++)
{
// 440 hz sine wave with amplitude = 0.5f at input sample rate
- inputBuffer[sample] = (short)(32767 * MathF.Sin((440 / inputSampleRate) * (float)sample * MathF.PI * 2f) * 0.5f);
+ inputBuffer[sample] = (short)(32767 * MathF.Sin((440 / inputSampleRate) * sample * MathF.PI * 2f) * 0.5f);
}
float fraction = 0;
@@ -70,14 +63,14 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
{
VoiceInParameter.SampleRateConversionQuality.High => 3,
VoiceInParameter.SampleRateConversionQuality.Default => 1,
- _ => 0
+ _ => 0,
};
for (int sample = 0; sample < outputSampleCount; sample++)
{
outputBuffer[sample] /= 32767;
// 440 hz sine wave with amplitude = 0.5f at output sample rate
- expectedOutput[sample] = MathF.Sin((440 / outputSampleRate) * (float)(sample + delay) * MathF.PI * 2f) * 0.5f;
+ expectedOutput[sample] = MathF.Sin((440 / outputSampleRate) * (sample + delay) * MathF.PI * 2f) * 0.5f;
float thisDelta = Math.Abs(expectedOutput[sample] - outputBuffer[sample]);
// Ensure no discontinuities
@@ -85,7 +78,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
sumDifference += thisDelta;
}
- sumDifference = sumDifference / (float)outputSampleCount;
+ sumDifference /= outputSampleCount;
// Expect the output to be 99% similar to the expected resampled sine wave
Assert.IsTrue(sumDifference < 0.01f);
}
diff --git a/src/Ryujinx.Tests/Audio/Renderer/Dsp/UpsamplerTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Dsp/UpsamplerTests.cs
index 2018752b3a..9b01b3ca68 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Dsp/UpsamplerTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Dsp/UpsamplerTests.cs
@@ -1,14 +1,7 @@
using NUnit.Framework;
using Ryujinx.Audio.Renderer.Dsp;
-using Ryujinx.Audio.Renderer.Parameter;
using Ryujinx.Audio.Renderer.Server.Upsampler;
using System;
-using System.Collections.Generic;
-using System.IO;
-using System.Linq;
-using System.Runtime.CompilerServices;
-using System.Text;
-using System.Threading.Tasks;
namespace Ryujinx.Tests.Audio.Renderer.Dsp
{
@@ -17,7 +10,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
[Test]
public void TestUpsamplerConsistency()
{
- UpsamplerBufferState bufferState = new UpsamplerBufferState();
+ UpsamplerBufferState bufferState = new();
int inputBlockSize = 160;
int numInputSamples = 32000;
int numOutputSamples = 48000;
@@ -28,14 +21,14 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
for (int sample = 0; sample < inputBuffer.Length; sample++)
{
// 440 hz sine wave with amplitude = 0.5f at input sample rate
- inputBuffer[sample] = MathF.Sin((440 / inputSampleRate) * (float)sample * MathF.PI * 2f) * 0.5f;
+ inputBuffer[sample] = MathF.Sin((440 / inputSampleRate) * sample * MathF.PI * 2f) * 0.5f;
}
int inputIdx = 0;
int outputIdx = 0;
while (inputIdx + inputBlockSize < numInputSamples)
{
- int outputBufLength = (int)Math.Round((float)(inputIdx + inputBlockSize) * outputSampleRate / inputSampleRate) - outputIdx;
+ int outputBufLength = (int)Math.Round((inputIdx + inputBlockSize) * outputSampleRate / inputSampleRate) - outputIdx;
UpsamplerHelper.Upsample(
outputBuffer.AsSpan(outputIdx),
inputBuffer.AsSpan(inputIdx),
@@ -52,11 +45,11 @@ namespace Ryujinx.Tests.Audio.Renderer.Dsp
for (int sample = 0; sample < numOutputSamples; sample++)
{
// 440 hz sine wave with amplitude = 0.5f at output sample rate with an offset of 15
- expectedOutput[sample] = MathF.Sin((440 / outputSampleRate) * (float)(sample - 15) * MathF.PI * 2f) * 0.5f;
+ expectedOutput[sample] = MathF.Sin((440 / outputSampleRate) * (sample - 15) * MathF.PI * 2f) * 0.5f;
sumDifference += Math.Abs(expectedOutput[sample] - outputBuffer[sample]);
}
- sumDifference = sumDifference / (float)expectedOutput.Length;
+ sumDifference /= expectedOutput.Length;
// Expect the output to be 98% similar to the expected resampled sine wave
Assert.IsTrue(sumDifference < 0.02f);
}
diff --git a/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/CompressorParameterTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/CompressorParameterTests.cs
index 24b834fcbf..016338dc71 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/CompressorParameterTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/CompressorParameterTests.cs
@@ -13,4 +13,3 @@ namespace Ryujinx.Tests.Audio.Renderer.Parameter.Effect
}
}
}
-
diff --git a/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterParameterTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterParameterTests.cs
index 8512ebd47c..e176cc62f4 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterParameterTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterParameterTests.cs
@@ -13,4 +13,3 @@ namespace Ryujinx.Tests.Audio.Renderer.Parameter.Effect
}
}
}
-
diff --git a/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterStatisticsTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterStatisticsTests.cs
index 43645ae427..13ad34ebd6 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterStatisticsTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Parameter/Effect/LimiterStatisticsTests.cs
@@ -13,4 +13,3 @@ namespace Ryujinx.Tests.Audio.Renderer.Parameter.Effect
}
}
}
-
diff --git a/src/Ryujinx.Tests/Audio/Renderer/Server/BehaviourContextTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Server/BehaviourContextTests.cs
index df946a12f9..557581881d 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Server/BehaviourContextTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Server/BehaviourContextTests.cs
@@ -8,7 +8,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestCheckFeature()
{
- int latestRevision = BehaviourContext.BaseRevisionMagic + BehaviourContext.LastRevision;
+ int latestRevision = BehaviourContext.BaseRevisionMagic + BehaviourContext.LastRevision;
int previousRevision = BehaviourContext.BaseRevisionMagic + (BehaviourContext.LastRevision - 1);
int invalidRevision = BehaviourContext.BaseRevisionMagic + (BehaviourContext.LastRevision + 1);
@@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestsMemoryPoolForceMappingEnabled()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision1);
@@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision1()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision1);
@@ -62,7 +62,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision2()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision2);
@@ -88,7 +88,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision3()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision3);
@@ -114,7 +114,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision4()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision4);
@@ -140,7 +140,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision5()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision5);
@@ -166,7 +166,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision6()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision6);
@@ -192,7 +192,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision7()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision7);
@@ -218,7 +218,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision8()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision8);
@@ -244,7 +244,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision9()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision9);
@@ -270,7 +270,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestRevision10()
{
- BehaviourContext behaviourContext = new BehaviourContext();
+ BehaviourContext behaviourContext = new();
behaviourContext.SetUserRevision(BehaviourContext.BaseRevisionMagic + BehaviourContext.Revision10);
@@ -293,4 +293,4 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
Assert.AreEqual(2, behaviourContext.GetPerformanceMetricsDataFormat());
}
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Audio/Renderer/Server/PoolMapperTests.cs b/src/Ryujinx.Tests/Audio/Renderer/Server/PoolMapperTests.cs
index d2c2e6cb94..4c931d9ee8 100644
--- a/src/Ryujinx.Tests/Audio/Renderer/Server/PoolMapperTests.cs
+++ b/src/Ryujinx.Tests/Audio/Renderer/Server/PoolMapperTests.cs
@@ -15,13 +15,13 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestInitializeSystemPool()
{
- PoolMapper poolMapper = new PoolMapper(DummyProcessHandle, true);
+ PoolMapper poolMapper = new(DummyProcessHandle, true);
MemoryPoolState memoryPoolDsp = MemoryPoolState.Create(MemoryPoolState.LocationType.Dsp);
MemoryPoolState memoryPoolCpu = MemoryPoolState.Create(MemoryPoolState.LocationType.Cpu);
const CpuAddress CpuAddress = 0x20000;
const DspAddress DspAddress = CpuAddress; // TODO: DSP LLE
- const ulong CpuSize = 0x1000;
+ const ulong CpuSize = 0x1000;
Assert.IsFalse(poolMapper.InitializeSystemPool(ref memoryPoolCpu, CpuAddress, CpuSize));
Assert.IsTrue(poolMapper.InitializeSystemPool(ref memoryPoolDsp, CpuAddress, CpuSize));
@@ -34,7 +34,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestGetProcessHandle()
{
- PoolMapper poolMapper = new PoolMapper(DummyProcessHandle, true);
+ PoolMapper poolMapper = new(DummyProcessHandle, true);
MemoryPoolState memoryPoolDsp = MemoryPoolState.Create(MemoryPoolState.LocationType.Dsp);
MemoryPoolState memoryPoolCpu = MemoryPoolState.Create(MemoryPoolState.LocationType.Cpu);
@@ -45,13 +45,13 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
[Test]
public void TestMappings()
{
- PoolMapper poolMapper = new PoolMapper(DummyProcessHandle, true);
+ PoolMapper poolMapper = new(DummyProcessHandle, true);
MemoryPoolState memoryPoolDsp = MemoryPoolState.Create(MemoryPoolState.LocationType.Dsp);
MemoryPoolState memoryPoolCpu = MemoryPoolState.Create(MemoryPoolState.LocationType.Cpu);
const CpuAddress CpuAddress = 0x20000;
const DspAddress DspAddress = CpuAddress; // TODO: DSP LLE
- const ulong CpuSize = 0x1000;
+ const ulong CpuSize = 0x1000;
memoryPoolDsp.SetCpuAddress(CpuAddress, CpuSize);
memoryPoolCpu.SetCpuAddress(CpuAddress, CpuSize);
@@ -72,10 +72,10 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
{
const CpuAddress CpuAddress = 0x20000;
const DspAddress DspAddress = CpuAddress; // TODO: DSP LLE
- const ulong CpuSize = 0x1000;
+ const ulong CpuSize = 0x1000;
- const int MemoryPoolStateArraySize = 0x10;
- const CpuAddress CpuAddressRegionEnding = CpuAddress * MemoryPoolStateArraySize;
+ const int MemoryPoolStateArraySize = 0x10;
+ const CpuAddress CpuAddressRegionEnding = CpuAddress * MemoryPoolStateArraySize;
MemoryPoolState[] memoryPoolStateArray = new MemoryPoolState[MemoryPoolStateArraySize];
@@ -85,13 +85,12 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
memoryPoolStateArray[i].SetCpuAddress(CpuAddress + (ulong)i * CpuSize, CpuSize);
}
- ErrorInfo errorInfo;
AddressInfo addressInfo = AddressInfo.Create();
- PoolMapper poolMapper = new PoolMapper(DummyProcessHandle, true);
+ PoolMapper poolMapper = new(DummyProcessHandle, true);
- Assert.IsTrue(poolMapper.TryAttachBuffer(out errorInfo, ref addressInfo, 0, 0));
+ Assert.IsTrue(poolMapper.TryAttachBuffer(out ErrorInfo errorInfo, ref addressInfo, 0, 0));
Assert.AreEqual(ResultCode.InvalidAddressInfo, errorInfo.ErrorCode);
Assert.AreEqual(0, errorInfo.ExtraErrorInfo);
@@ -105,7 +104,7 @@ namespace Ryujinx.Tests.Audio.Renderer.Server
poolMapper = new PoolMapper(DummyProcessHandle, false);
- Assert.IsFalse(poolMapper.TryAttachBuffer(out errorInfo, ref addressInfo, 0, 0));
+ Assert.IsFalse(poolMapper.TryAttachBuffer(out _, ref addressInfo, 0, 0));
addressInfo.ForceMappedDspAddress = 0;
diff --git a/src/Ryujinx.Tests/Cpu/Arm64CodeGenCommonTests.cs b/src/Ryujinx.Tests/Cpu/Arm64CodeGenCommonTests.cs
index e16361bbcd..0092d9a111 100644
--- a/src/Ryujinx.Tests/Cpu/Arm64CodeGenCommonTests.cs
+++ b/src/Ryujinx.Tests/Cpu/Arm64CodeGenCommonTests.cs
@@ -31,7 +31,7 @@ namespace Ryujinx.Tests.Cpu
new() { Value = 0xffff8fffffff8fff, Valid = true, ImmN = 0, ImmS = 0x1c, ImmR = 17 },
new() { Value = 0x000000000ffff800, Valid = true, ImmN = 1, ImmS = 0x10, ImmR = 53 },
};
-
+
[Test]
public void BitImmTests([ValueSource(nameof(TestCases))] TestCase test)
{
@@ -43,4 +43,4 @@ namespace Ryujinx.Tests.Cpu
Assert.That(immR, Is.EqualTo(test.ImmR));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTest.cs b/src/Ryujinx.Tests/Cpu/CpuTest.cs
index ad4ba539b2..35158c0b4b 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTest.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTest.cs
@@ -14,13 +14,15 @@ namespace Ryujinx.Tests.Cpu
public class CpuTest
{
protected static readonly ulong Size = MemoryBlock.GetPageSize();
+#pragma warning disable CA2211 // Non-constant fields should not be visible
protected static ulong CodeBaseAddress = Size;
protected static ulong DataBaseAddress = CodeBaseAddress + Size;
+#pragma warning restore CA2211
- private static bool Ignore_FpcrFz = false;
- private static bool Ignore_FpcrDn = false;
+ private static readonly bool _ignoreFpcrFz = false;
+ private static readonly bool _ignoreFpcrDn = false;
- private static bool IgnoreAllExcept_FpsrQc = false;
+ private static readonly bool _ignoreAllExceptFpsrQc = false;
private ulong _currAddress;
@@ -84,8 +86,8 @@ namespace Ryujinx.Tests.Cpu
_context.Dispose();
_ram.Dispose();
- _memory = null;
- _context = null;
+ _memory = null;
+ _context = null;
_cpuContext = null;
_unicornEmu = null;
@@ -109,38 +111,38 @@ namespace Ryujinx.Tests.Cpu
protected ExecutionContext GetContext() => _context;
- protected void SetContext(ulong x0 = 0,
- ulong x1 = 0,
- ulong x2 = 0,
- ulong x3 = 0,
- ulong x31 = 0,
- V128 v0 = default,
- V128 v1 = default,
- V128 v2 = default,
- V128 v3 = default,
- V128 v4 = default,
- V128 v5 = default,
- V128 v30 = default,
- V128 v31 = default,
- bool overflow = false,
- bool carry = false,
- bool zero = false,
- bool negative = false,
- int fpcr = 0,
- int fpsr = 0)
+ protected void SetContext(ulong x0 = 0,
+ ulong x1 = 0,
+ ulong x2 = 0,
+ ulong x3 = 0,
+ ulong x31 = 0,
+ V128 v0 = default,
+ V128 v1 = default,
+ V128 v2 = default,
+ V128 v3 = default,
+ V128 v4 = default,
+ V128 v5 = default,
+ V128 v30 = default,
+ V128 v31 = default,
+ bool overflow = false,
+ bool carry = false,
+ bool zero = false,
+ bool negative = false,
+ int fpcr = 0,
+ int fpsr = 0)
{
- _context.SetX(0, x0);
- _context.SetX(1, x1);
- _context.SetX(2, x2);
- _context.SetX(3, x3);
+ _context.SetX(0, x0);
+ _context.SetX(1, x1);
+ _context.SetX(2, x2);
+ _context.SetX(3, x3);
_context.SetX(31, x31);
- _context.SetV(0, v0);
- _context.SetV(1, v1);
- _context.SetV(2, v2);
- _context.SetV(3, v3);
- _context.SetV(4, v4);
- _context.SetV(5, v5);
+ _context.SetV(0, v0);
+ _context.SetV(1, v1);
+ _context.SetV(2, v2);
+ _context.SetV(3, v3);
+ _context.SetV(4, v4);
+ _context.SetV(5, v5);
_context.SetV(30, v30);
_context.SetV(31, v31);
@@ -156,20 +158,20 @@ namespace Ryujinx.Tests.Cpu
_unicornEmu.X[1] = x1;
_unicornEmu.X[2] = x2;
_unicornEmu.X[3] = x3;
- _unicornEmu.SP = x31;
+ _unicornEmu.SP = x31;
- _unicornEmu.Q[0] = V128ToSimdValue(v0);
- _unicornEmu.Q[1] = V128ToSimdValue(v1);
- _unicornEmu.Q[2] = V128ToSimdValue(v2);
- _unicornEmu.Q[3] = V128ToSimdValue(v3);
- _unicornEmu.Q[4] = V128ToSimdValue(v4);
- _unicornEmu.Q[5] = V128ToSimdValue(v5);
+ _unicornEmu.Q[0] = V128ToSimdValue(v0);
+ _unicornEmu.Q[1] = V128ToSimdValue(v1);
+ _unicornEmu.Q[2] = V128ToSimdValue(v2);
+ _unicornEmu.Q[3] = V128ToSimdValue(v3);
+ _unicornEmu.Q[4] = V128ToSimdValue(v4);
+ _unicornEmu.Q[5] = V128ToSimdValue(v5);
_unicornEmu.Q[30] = V128ToSimdValue(v30);
_unicornEmu.Q[31] = V128ToSimdValue(v31);
_unicornEmu.OverflowFlag = overflow;
- _unicornEmu.CarryFlag = carry;
- _unicornEmu.ZeroFlag = zero;
+ _unicornEmu.CarryFlag = carry;
+ _unicornEmu.ZeroFlag = zero;
_unicornEmu.NegativeFlag = negative;
_unicornEmu.Fpcr = fpcr;
@@ -186,34 +188,34 @@ namespace Ryujinx.Tests.Cpu
}
}
- protected ExecutionContext SingleOpcode(uint opcode,
- ulong x0 = 0,
- ulong x1 = 0,
- ulong x2 = 0,
- ulong x3 = 0,
- ulong x31 = 0,
- V128 v0 = default,
- V128 v1 = default,
- V128 v2 = default,
- V128 v3 = default,
- V128 v4 = default,
- V128 v5 = default,
- V128 v30 = default,
- V128 v31 = default,
- bool overflow = false,
- bool carry = false,
- bool zero = false,
- bool negative = false,
- int fpcr = 0,
- int fpsr = 0,
- bool runUnicorn = true)
+ protected ExecutionContext SingleOpcode(uint opcode,
+ ulong x0 = 0,
+ ulong x1 = 0,
+ ulong x2 = 0,
+ ulong x3 = 0,
+ ulong x31 = 0,
+ V128 v0 = default,
+ V128 v1 = default,
+ V128 v2 = default,
+ V128 v3 = default,
+ V128 v4 = default,
+ V128 v5 = default,
+ V128 v30 = default,
+ V128 v31 = default,
+ bool overflow = false,
+ bool carry = false,
+ bool zero = false,
+ bool negative = false,
+ int fpcr = 0,
+ int fpsr = 0,
+ bool runUnicorn = true)
{
- if (Ignore_FpcrFz)
+ if (_ignoreFpcrFz)
{
fpcr &= ~(1 << (int)Fpcr.Fz);
}
- if (Ignore_FpcrDn)
+ if (_ignoreFpcrDn)
{
fpcr &= ~(1 << (int)Fpcr.Dn);
}
@@ -254,8 +256,8 @@ namespace Ryujinx.Tests.Cpu
/// Round towards Minus Infinity mode.
Rm,
/// Round towards Zero mode.
- Rz
- };
+ Rz,
+ }
/// Floating-point Control Register.
protected enum Fpcr
@@ -263,15 +265,16 @@ namespace Ryujinx.Tests.Cpu
/// Rounding Mode control field.
RMode = 22,
/// Flush-to-zero mode control bit.
- Fz = 24,
+ Fz = 24,
/// Default NaN mode control bit.
- Dn = 25,
+ Dn = 25,
/// Alternative half-precision control bit.
- Ahp = 26
+ Ahp = 26,
}
/// Floating-point Status Register.
- [Flags] protected enum Fpsr
+ [Flags]
+ protected enum Fpsr
{
None = 0,
@@ -289,10 +292,11 @@ namespace Ryujinx.Tests.Cpu
Idc = 1 << 7,
/// Cumulative saturation bit.
- Qc = 1 << 27
+ Qc = 1 << 27,
}
- [Flags] protected enum FpSkips
+ [Flags]
+ protected enum FpSkips
{
None = 0,
@@ -300,7 +304,7 @@ namespace Ryujinx.Tests.Cpu
IfNaND = 2,
IfUnderflow = 4,
- IfOverflow = 8
+ IfOverflow = 8,
}
protected enum FpTolerances
@@ -308,15 +312,15 @@ namespace Ryujinx.Tests.Cpu
None,
UpToOneUlpsS,
- UpToOneUlpsD
+ UpToOneUlpsD,
}
protected void CompareAgainstUnicorn(
- Fpsr fpsrMask = Fpsr.None,
- FpSkips fpSkips = FpSkips.None,
+ Fpsr fpsrMask = Fpsr.None,
+ FpSkips fpSkips = FpSkips.None,
FpTolerances fpTolerances = FpTolerances.None)
{
- if (IgnoreAllExcept_FpsrQc)
+ if (_ignoreAllExceptFpsrQc)
{
fpsrMask &= Fpsr.Qc;
}
@@ -326,6 +330,7 @@ namespace Ryujinx.Tests.Cpu
ManageFpSkips(fpSkips);
}
+#pragma warning disable IDE0055 // Disable formatting
Assert.That(_context.GetX(0), Is.EqualTo(_unicornEmu.X[0]), "X0");
Assert.That(_context.GetX(1), Is.EqualTo(_unicornEmu.X[1]), "X1");
Assert.That(_context.GetX(2), Is.EqualTo(_unicornEmu.X[2]), "X2");
@@ -358,6 +363,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(_context.GetX(29), Is.EqualTo(_unicornEmu.X[29]));
Assert.That(_context.GetX(30), Is.EqualTo(_unicornEmu.X[30]));
Assert.That(_context.GetX(31), Is.EqualTo(_unicornEmu.SP), "X31");
+#pragma warning restore IDE0055
if (fpTolerances == FpTolerances.None)
{
@@ -367,6 +373,8 @@ namespace Ryujinx.Tests.Cpu
{
ManageFpTolerances(fpTolerances);
}
+
+#pragma warning disable IDE0055 // Disable formatting
Assert.That(V128ToSimdValue(_context.GetV(1)), Is.EqualTo(_unicornEmu.Q[1]), "V1");
Assert.That(V128ToSimdValue(_context.GetV(2)), Is.EqualTo(_unicornEmu.Q[2]), "V2");
Assert.That(V128ToSimdValue(_context.GetV(3)), Is.EqualTo(_unicornEmu.Q[3]), "V3");
@@ -409,6 +417,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That((int)_context.Fpcr, Is.EqualTo(_unicornEmu.Fpcr), "Fpcr");
Assert.That((int)_context.Fpsr & (int)fpsrMask, Is.EqualTo(_unicornEmu.Fpsr & (int)fpsrMask), "Fpsr");
+#pragma warning restore IDE0055
if (_usingMemory)
{
@@ -455,7 +464,7 @@ namespace Ryujinx.Tests.Cpu
private void ManageFpTolerances(FpTolerances fpTolerances)
{
- bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
+ bool IsNormalOrSubnormalS(float f) => float.IsNormal(f) || float.IsSubnormal(f);
bool IsNormalOrSubnormalD(double d) => double.IsNormal(d) || double.IsSubnormal(d);
if (!Is.EqualTo(_unicornEmu.Q[0]).ApplyTo(V128ToSimdValue(_context.GetV(0))).IsSuccess)
@@ -467,13 +476,13 @@ namespace Ryujinx.Tests.Cpu
{
Assert.Multiple(() =>
{
- Assert.That (_context.GetV(0).Extract(0),
+ Assert.That(_context.GetV(0).Extract(0),
Is.EqualTo(_unicornEmu.Q[0].GetFloat(0)).Within(1).Ulps, "V0[0]");
- Assert.That (_context.GetV(0).Extract(1),
+ Assert.That(_context.GetV(0).Extract(1),
Is.EqualTo(_unicornEmu.Q[0].GetFloat(1)).Within(1).Ulps, "V0[1]");
- Assert.That (_context.GetV(0).Extract(2),
+ Assert.That(_context.GetV(0).Extract(2),
Is.EqualTo(_unicornEmu.Q[0].GetFloat(2)).Within(1).Ulps, "V0[2]");
- Assert.That (_context.GetV(0).Extract(3),
+ Assert.That(_context.GetV(0).Extract(3),
Is.EqualTo(_unicornEmu.Q[0].GetFloat(3)).Within(1).Ulps, "V0[3]");
});
@@ -492,9 +501,9 @@ namespace Ryujinx.Tests.Cpu
{
Assert.Multiple(() =>
{
- Assert.That (_context.GetV(0).Extract(0),
+ Assert.That(_context.GetV(0).Extract(0),
Is.EqualTo(_unicornEmu.Q[0].GetDouble(0)).Within(1).Ulps, "V0[0]");
- Assert.That (_context.GetV(0).Extract(1),
+ Assert.That(_context.GetV(0).Extract(1),
Is.EqualTo(_unicornEmu.Q[0].GetDouble(1)).Within(1).Ulps, "V0[1]");
});
@@ -513,13 +522,13 @@ namespace Ryujinx.Tests.Cpu
return new SimdValue(value.Extract(0), value.Extract(1));
}
- protected static V128 MakeVectorScalar(float value) => new V128(value);
- protected static V128 MakeVectorScalar(double value) => new V128(value);
+ protected static V128 MakeVectorScalar(float value) => new(value);
+ protected static V128 MakeVectorScalar(double value) => new(value);
- protected static V128 MakeVectorE0(ulong e0) => new V128(e0, 0);
- protected static V128 MakeVectorE1(ulong e1) => new V128(0, e1);
+ protected static V128 MakeVectorE0(ulong e0) => new(e0, 0);
+ protected static V128 MakeVectorE1(ulong e1) => new(0, e1);
- protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new V128(e0, e1);
+ protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new(e0, e1);
protected static ulong GetVectorE0(V128 vector) => vector.Extract(0);
protected static ulong GetVectorE1(V128 vector) => vector.Extract(1);
@@ -528,8 +537,9 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUShort();
- while (( rnd & 0x7C00u) == 0u ||
+ do
+ rnd = TestContext.CurrentContext.Random.NextUShort();
+ while ((rnd & 0x7C00u) == 0u ||
(~rnd & 0x7C00u) == 0u);
return (ushort)rnd;
@@ -539,7 +549,8 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUShort();
+ do
+ rnd = TestContext.CurrentContext.Random.NextUShort();
while ((rnd & 0x03FFu) == 0u);
return (ushort)(rnd & 0x83FFu);
@@ -549,8 +560,9 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUInt();
- while (( rnd & 0x7F800000u) == 0u ||
+ do
+ rnd = TestContext.CurrentContext.Random.NextUInt();
+ while ((rnd & 0x7F800000u) == 0u ||
(~rnd & 0x7F800000u) == 0u);
return rnd;
@@ -560,7 +572,8 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUInt();
+ do
+ rnd = TestContext.CurrentContext.Random.NextUInt();
while ((rnd & 0x007FFFFFu) == 0u);
return rnd & 0x807FFFFFu;
@@ -570,8 +583,9 @@ namespace Ryujinx.Tests.Cpu
{
ulong rnd;
- do rnd = TestContext.CurrentContext.Random.NextULong();
- while (( rnd & 0x7FF0000000000000ul) == 0ul ||
+ do
+ rnd = TestContext.CurrentContext.Random.NextULong();
+ while ((rnd & 0x7FF0000000000000ul) == 0ul ||
(~rnd & 0x7FF0000000000000ul) == 0ul);
return rnd;
@@ -581,10 +595,11 @@ namespace Ryujinx.Tests.Cpu
{
ulong rnd;
- do rnd = TestContext.CurrentContext.Random.NextULong();
+ do
+ rnd = TestContext.CurrentContext.Random.NextULong();
while ((rnd & 0x000FFFFFFFFFFFFFul) == 0ul);
return rnd & 0x800FFFFFFFFFFFFFul;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTest32.cs b/src/Ryujinx.Tests/Cpu/CpuTest32.cs
index a1f6431cfb..05a4d3beea 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTest32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTest32.cs
@@ -14,8 +14,10 @@ namespace Ryujinx.Tests.Cpu
public class CpuTest32
{
protected static readonly uint Size = (uint)MemoryBlock.GetPageSize();
+#pragma warning disable CA2211 // Non-constant fields should not be visible
protected static uint CodeBaseAddress = Size;
protected static uint DataBaseAddress = CodeBaseAddress + Size;
+#pragma warning restore CA2211
private uint _currAddress;
@@ -79,8 +81,8 @@ namespace Ryujinx.Tests.Cpu
_context.Dispose();
_ram.Dispose();
- _memory = null;
- _context = null;
+ _memory = null;
+ _context = null;
_cpuContext = null;
_unicornEmu = null;
@@ -288,16 +290,17 @@ namespace Ryujinx.Tests.Cpu
SetWorkingMemory(0, testMem);
- RunPrecomputedTestCase(new PrecomputedThumbTestCase(){
+ RunPrecomputedTestCase(new PrecomputedThumbTestCase
+ {
Instructions = test.Instructions,
StartRegs = test.StartRegs,
FinalRegs = test.FinalRegs,
});
- foreach (var delta in test.MemoryDelta)
+ foreach (var (address, value) in test.MemoryDelta)
{
- testMem[delta.Address - DataBaseAddress + 0] = (byte)(delta.Value >> 0);
- testMem[delta.Address - DataBaseAddress + 1] = (byte)(delta.Value >> 8);
+ testMem[address - DataBaseAddress + 0] = (byte)(value >> 0);
+ testMem[address - DataBaseAddress + 1] = (byte)(value >> 8);
}
byte[] mem = _memory.GetSpan(DataBaseAddress, (int)Size).ToArray();
@@ -324,8 +327,8 @@ namespace Ryujinx.Tests.Cpu
/// Round towards Minus Infinity mode.
Rm,
/// Round towards Zero mode.
- Rz
- };
+ Rz,
+ }
/// Floating-point Control Register.
protected enum Fpcr
@@ -337,7 +340,7 @@ namespace Ryujinx.Tests.Cpu
/// Default NaN mode control bit.
Dn = 25,
/// Alternative half-precision control bit.
- Ahp = 26
+ Ahp = 26,
}
/// Floating-point Status Register.
@@ -363,7 +366,7 @@ namespace Ryujinx.Tests.Cpu
Qc = 1 << 27,
/// NZCV flags.
- Nzcv = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)
+ Nzcv = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28),
}
[Flags]
@@ -375,7 +378,7 @@ namespace Ryujinx.Tests.Cpu
IfNaND = 2,
IfUnderflow = 4,
- IfOverflow = 8
+ IfOverflow = 8,
}
protected enum FpTolerances
@@ -383,7 +386,7 @@ namespace Ryujinx.Tests.Cpu
None,
UpToOneUlpsS,
- UpToOneUlpsD
+ UpToOneUlpsD,
}
protected void CompareAgainstUnicorn(
@@ -554,13 +557,13 @@ namespace Ryujinx.Tests.Cpu
return new SimdValue(value.Extract(0), value.Extract(1));
}
- protected static V128 MakeVectorScalar(float value) => new V128(value);
- protected static V128 MakeVectorScalar(double value) => new V128(value);
+ protected static V128 MakeVectorScalar(float value) => new(value);
+ protected static V128 MakeVectorScalar(double value) => new(value);
- protected static V128 MakeVectorE0(ulong e0) => new V128(e0, 0);
- protected static V128 MakeVectorE1(ulong e1) => new V128(0, e1);
+ protected static V128 MakeVectorE0(ulong e0) => new(e0, 0);
+ protected static V128 MakeVectorE1(ulong e1) => new(0, e1);
- protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new V128(e0, e1);
+ protected static V128 MakeVectorE0E1(ulong e0, ulong e1) => new(e0, e1);
protected static V128 MakeVectorE0E1E2E3(uint e0, uint e1, uint e2, uint e3)
{
@@ -574,7 +577,8 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUShort();
+ do
+ rnd = TestContext.CurrentContext.Random.NextUShort();
while ((rnd & 0x7C00u) == 0u ||
(~rnd & 0x7C00u) == 0u);
@@ -585,7 +589,8 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUShort();
+ do
+ rnd = TestContext.CurrentContext.Random.NextUShort();
while ((rnd & 0x03FFu) == 0u);
return (ushort)(rnd & 0x83FFu);
@@ -595,7 +600,8 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUInt();
+ do
+ rnd = TestContext.CurrentContext.Random.NextUInt();
while ((rnd & 0x7F800000u) == 0u ||
(~rnd & 0x7F800000u) == 0u);
@@ -606,7 +612,8 @@ namespace Ryujinx.Tests.Cpu
{
uint rnd;
- do rnd = TestContext.CurrentContext.Random.NextUInt();
+ do
+ rnd = TestContext.CurrentContext.Random.NextUInt();
while ((rnd & 0x007FFFFFu) == 0u);
return rnd & 0x807FFFFFu;
@@ -616,7 +623,8 @@ namespace Ryujinx.Tests.Cpu
{
ulong rnd;
- do rnd = TestContext.CurrentContext.Random.NextULong();
+ do
+ rnd = TestContext.CurrentContext.Random.NextULong();
while ((rnd & 0x7FF0000000000000ul) == 0ul ||
(~rnd & 0x7FF0000000000000ul) == 0ul);
@@ -627,10 +635,11 @@ namespace Ryujinx.Tests.Cpu
{
ulong rnd;
- do rnd = TestContext.CurrentContext.Random.NextULong();
+ do
+ rnd = TestContext.CurrentContext.Random.NextULong();
while ((rnd & 0x000FFFFFFFFFFFFFul) == 0ul);
return rnd & 0x800FFFFFFFFFFFFFul;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs
index 7318d97938..9c1876c8cc 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs
@@ -10,7 +10,7 @@ namespace Ryujinx.Tests.Cpu
{
#if Alu
-#region "Helper methods"
+ #region "Helper methods"
private static uint GenLeadingSignsMinus32(int cnt) // 0 <= cnt <= 31
{
return ~GenLeadingZeros32(cnt + 1);
@@ -33,29 +33,43 @@ namespace Ryujinx.Tests.Cpu
private static uint GenLeadingZeros32(int cnt) // 0 <= cnt <= 32
{
- if (cnt == 32) return 0u;
- if (cnt == 31) return 1u;
+ if (cnt == 32)
+ {
+ return 0u;
+ }
- uint rnd = TestContext.CurrentContext.Random.NextUInt();
- int mask = int.MinValue;
+ if (cnt == 31)
+ {
+ return 1u;
+ }
+
+ uint rnd = TestContext.CurrentContext.Random.NextUInt();
+ int mask = int.MinValue;
return (rnd >> (cnt + 1)) | ((uint)mask >> cnt);
}
private static ulong GenLeadingZeros64(int cnt) // 0 <= cnt <= 64
{
- if (cnt == 64) return 0ul;
- if (cnt == 63) return 1ul;
+ if (cnt == 64)
+ {
+ return 0ul;
+ }
- ulong rnd = TestContext.CurrentContext.Random.NextULong();
- long mask = long.MinValue;
+ if (cnt == 63)
+ {
+ return 1ul;
+ }
+
+ ulong rnd = TestContext.CurrentContext.Random.NextULong();
+ long mask = long.MinValue;
return (rnd >> (cnt + 1)) | ((ulong)mask >> cnt);
}
-#endregion
+ #endregion
-#region "ValueSource (Types)"
- private static IEnumerable _GenLeadingSignsX_()
+ #region "ValueSource (Types)"
+ private static IEnumerable GenLeadingSignsX()
{
for (int cnt = 0; cnt <= 63; cnt++)
{
@@ -64,7 +78,7 @@ namespace Ryujinx.Tests.Cpu
}
}
- private static IEnumerable _GenLeadingSignsW_()
+ private static IEnumerable GenLeadingSignsW()
{
for (int cnt = 0; cnt <= 31; cnt++)
{
@@ -73,7 +87,7 @@ namespace Ryujinx.Tests.Cpu
}
}
- private static IEnumerable _GenLeadingZerosX_()
+ private static IEnumerable GenLeadingZerosX()
{
for (int cnt = 0; cnt <= 64; cnt++)
{
@@ -81,19 +95,19 @@ namespace Ryujinx.Tests.Cpu
}
}
- private static IEnumerable _GenLeadingZerosW_()
+ private static IEnumerable GenLeadingZerosW()
{
for (int cnt = 0; cnt <= 32; cnt++)
{
yield return GenLeadingZeros32(cnt);
}
}
-#endregion
+ #endregion
[Test, Pairwise, Description("CLS , ")]
public void Cls_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource(nameof(_GenLeadingSignsX_))] ulong xn)
+ [ValueSource(nameof(GenLeadingSignsX))] ulong xn)
{
uint opcode = 0xDAC01400; // CLS X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -108,7 +122,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLS , ")]
public void Cls_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource(nameof(_GenLeadingSignsW_))] uint wn)
+ [ValueSource(nameof(GenLeadingSignsW))] uint wn)
{
uint opcode = 0x5AC01400; // CLS W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -123,7 +137,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ , ")]
public void Clz_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource(nameof(_GenLeadingZerosX_))] ulong xn)
+ [ValueSource(nameof(GenLeadingZerosX))] ulong xn)
{
uint opcode = 0xDAC01000; // CLZ X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -138,7 +152,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ , ")]
public void Clz_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
- [ValueSource(nameof(_GenLeadingZerosW_))] uint wn)
+ [ValueSource(nameof(GenLeadingZerosW))] uint wn)
{
uint opcode = 0x5AC01000; // CLZ W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -263,4 +277,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
index 0d009e90e3..404dfd7de7 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
@@ -9,8 +9,8 @@ namespace Ryujinx.Tests.Cpu
{
#if Alu32
-#region "ValueSource (Opcodes)"
- private static uint[] _SU_H_AddSub_8_()
+ #region "ValueSource (Opcodes)"
+ private static uint[] SuHAddSub8()
{
return new[]
{
@@ -21,22 +21,22 @@ namespace Ryujinx.Tests.Cpu
0xe6500f90u, // UADD8 R0, R0, R0
0xe6500ff0u, // USUB8 R0, R0, R0
0xe6700f90u, // UHADD8 R0, R0, R0
- 0xe6700ff0u // UHSUB8 R0, R0, R0
+ 0xe6700ff0u, // UHSUB8 R0, R0, R0
};
}
- private static uint[] _Ssat_Usat_()
+ private static uint[] SsatUsat()
{
return new[]
{
0xe6a00010u, // SSAT R0, #1, R0, LSL #0
0xe6a00050u, // SSAT R0, #1, R0, ASR #32
0xe6e00010u, // USAT R0, #0, R0, LSL #0
- 0xe6e00050u // USAT R0, #0, R0, ASR #32
+ 0xe6e00050u, // USAT R0, #0, R0, ASR #32
};
}
- private static uint[] _Ssat16_Usat16_()
+ private static uint[] Ssat16Usat16()
{
return new[]
{
@@ -45,17 +45,17 @@ namespace Ryujinx.Tests.Cpu
};
}
- private static uint[] _Lsr_Lsl_Asr_Ror_()
+ private static uint[] LsrLslAsrRor()
{
return new[]
{
0xe1b00030u, // LSRS R0, R0, R0
0xe1b00010u, // LSLS R0, R0, R0
0xe1b00050u, // ASRS R0, R0, R0
- 0xe1b00070u // RORS R0, R0, R0
+ 0xe1b00070u, // RORS R0, R0, R0
};
}
-#endregion
+ #endregion
private const int RndCnt = 2;
@@ -76,7 +76,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Lsr_Lsl_Asr_Ror([ValueSource(nameof(_Lsr_Lsl_Asr_Ror_))] uint opcode,
+ public void Lsr_Lsl_Asr_Ror([ValueSource(nameof(LsrLslAsrRor))] uint opcode,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] uint shiftValue,
[Range(0, 31)] int shiftAmount)
@@ -130,7 +130,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Ssat_Usat([ValueSource(nameof(_Ssat_Usat_))] uint opcode,
+ public void Ssat_Usat([ValueSource(nameof(SsatUsat))] uint opcode,
[Values(0u, 0xdu)] uint rd,
[Values(1u, 0xdu)] uint rn,
[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint sat,
@@ -148,7 +148,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Ssat16_Usat16([ValueSource(nameof(_Ssat16_Usat16_))] uint opcode,
+ public void Ssat16_Usat16([ValueSource(nameof(Ssat16Usat16))] uint opcode,
[Values(0u, 0xdu)] uint rd,
[Values(1u, 0xdu)] uint rn,
[Values(0u, 7u, 8u, 0xfu)] uint sat,
@@ -165,7 +165,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void SU_H_AddSub_8([ValueSource(nameof(_SU_H_AddSub_8_))] uint opcode,
+ public void SU_H_AddSub_8([ValueSource(nameof(SuHAddSub8))] uint opcode,
[Values(0u, 0xdu)] uint rd,
[Values(1u)] uint rm,
[Values(2u)] uint rn,
@@ -191,9 +191,9 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCnt)] uint w2)
{
uint opUadd8 = 0xE6500F90; // UADD8 R0, R0, R0
- uint opSel = 0xE6800FB0; // SEL R0, R0, R0
+ uint opSel = 0xE6800FB0; // SEL R0, R0, R0
- opUadd8 |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
+ opUadd8 |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
opSel |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
SetContext(r0: w0, r1: w1, r2: w2);
@@ -206,4 +206,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
index 0265e52308..1e48086b20 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs
@@ -26,7 +26,7 @@ namespace Ryujinx.Tests.Cpu
}
}
-#region "ValueSource (CRC32)"
+ #region "ValueSource (CRC32)"
private static CrcTest[] _CRC32_Test_Values_()
{
// Created with http://www.sunshine2k.de/coding/javascript/crc/crc_js.html, with:
@@ -48,10 +48,10 @@ namespace Ryujinx.Tests.Cpu
new CrcTest(0xffffffffu, 0x7f_ff_ff_ff_ff_ff_ff_ffu, false, 0x00ffffff, 0x0000ffff, 0x00000000, 0x3303a3c3),
new CrcTest(0xffffffffu, 0x80_00_00_00_00_00_00_00u, false, 0x2dfd1072, 0xbe26ed00, 0xdebb20e3, 0x7765a3b6),
new CrcTest(0xffffffffu, 0xff_ff_ff_ff_ff_ff_ff_ffu, false, 0x00ffffff, 0x0000ffff, 0x00000000, 0xdebb20e3),
- new CrcTest(0xffffffffu, 0xa0_02_f1_ca_52_78_8c_1cu, false, 0x39fc4c3d, 0xbc5f7f56, 0x4ed8e906, 0x12cb419c)
+ new CrcTest(0xffffffffu, 0xa0_02_f1_ca_52_78_8c_1cu, false, 0x39fc4c3d, 0xbc5f7f56, 0x4ed8e906, 0x12cb419c),
};
}
-#endregion
+ #endregion
[Test, Combinatorial]
public void Crc32_b_h_w_x([Values(0u)] uint rd,
@@ -304,4 +304,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs
index d92a952240..4e355358ae 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs
@@ -27,7 +27,7 @@ namespace Ryujinx.Tests.Cpu
}
}
-#region "ValueSource (CRC32/CRC32C)"
+ #region "ValueSource (CRC32/CRC32C)"
private static CrcTest32[] _CRC32_Test_Values_()
{
// Created with http://www.sunshine2k.de/coding/javascript/crc/crc_js.html, with:
@@ -60,10 +60,10 @@ namespace Ryujinx.Tests.Cpu
new CrcTest32(0xffffffffu, 0x7f_ff_ff_ffu, true, 0x00ffffff, 0x0000ffff, 0x82f63b78),
new CrcTest32(0xffffffffu, 0x80_00_00_00u, true, 0xad82acae, 0x0e9e882d, 0x356e8f40),
new CrcTest32(0xffffffffu, 0xff_ff_ff_ffu, true, 0x00ffffff, 0x0000ffff, 0x00000000),
- new CrcTest32(0xffffffffu, 0x9d_cb_12_f0u, true, 0x5eecc3db, 0xbb6111cb, 0xcfb54fc9)
+ new CrcTest32(0xffffffffu, 0x9d_cb_12_f0u, true, 0x5eecc3db, 0xbb6111cb, 0xcfb54fc9),
};
}
-#endregion
+ #endregion
[Test, Combinatorial]
public void Crc32_Crc32c_b_h_w([Values(0u)] uint rd,
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
index c97ef9ed04..5c00cbc45f 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
@@ -430,4 +430,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
index cc12f3871a..eeeef085c3 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
@@ -9,8 +9,8 @@ namespace Ryujinx.Tests.Cpu
{
#if AluRs32
-#region "ValueSource (Opcodes)"
- private static uint[] _opcodes()
+ #region "ValueSource (Opcodes)"
+ private static uint[] Opcodes()
{
return new[]
{
@@ -30,12 +30,12 @@ namespace Ryujinx.Tests.Cpu
0xe2500000u, // SUBS R0, R0, #0
};
}
-#endregion
+ #endregion
private const int RndCnt = 2;
[Test, Pairwise]
- public void TestCpuTestAluImm32([ValueSource(nameof(_opcodes))] uint opcode,
+ public void TestCpuTestAluImm32([ValueSource(nameof(Opcodes))] uint opcode,
[Values(0u, 13u)] uint rd,
[Values(1u, 13u)] uint rn,
[Random(RndCnt)] uint imm,
@@ -52,4 +52,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
index 20e0e396e6..f63360c21e 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
@@ -892,4 +892,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
index d241aac483..f8fb013d52 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
{
#if AluRs32
-#region "ValueSource (Opcodes)"
+ #region "ValueSource (Opcodes)"
private static uint[] _Add_Adds_Rsb_Rsbs_()
{
return new[]
@@ -17,7 +17,7 @@ namespace Ryujinx.Tests.Cpu
0xe0800000u, // ADD R0, R0, R0, LSL #0
0xe0900000u, // ADDS R0, R0, R0, LSL #0
0xe0600000u, // RSB R0, R0, R0, LSL #0
- 0xe0700000u // RSBS R0, R0, R0, LSL #0
+ 0xe0700000u, // RSBS R0, R0, R0, LSL #0
};
}
@@ -30,14 +30,14 @@ namespace Ryujinx.Tests.Cpu
0xe0e00000u, // RSC R0, R0, R0
0xe0f00000u, // RSCS R0, R0, R0
0xe0c00000u, // SBC R0, R0, R0
- 0xe0d00000u // SBCS R0, R0, R0
+ 0xe0d00000u, // SBCS R0, R0, R0
};
}
-#endregion
+ #endregion
[Test, Pairwise]
- public void Adc_Adcs_Rsc_Rscs_Sbc_Sbcs([ValueSource("_Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_")] uint opcode,
+ public void Adc_Adcs_Rsc_Rscs_Sbc_Sbcs([ValueSource(nameof(_Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_))] uint opcode,
[Values(0u, 13u)] uint rd,
[Values(1u, 13u)] uint rn,
[Values(2u, 13u)] uint rm,
@@ -57,7 +57,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Add_Adds_Rsb_Rsbs([ValueSource("_Add_Adds_Rsb_Rsbs_")] uint opcode,
+ public void Add_Adds_Rsb_Rsbs([ValueSource(nameof(_Add_Adds_Rsb_Rsbs_))] uint opcode,
[Values(0u, 13u)] uint rd,
[Values(1u, 13u)] uint rn,
[Values(2u, 13u)] uint rm,
@@ -79,4 +79,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
index d51e762098..9897bdba3d 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs
@@ -720,4 +720,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs b/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs
index 871e7649fd..5afefd62c6 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs
@@ -103,4 +103,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs
index c169ee41cd..ed911d0586 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs
@@ -8,7 +8,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestBfm : CpuTest
{
#if Bfm
- private const int RndCnt = 2;
+ private const int RndCnt = 2;
[Test, Pairwise, Description("BFM , , #, #")]
public void Bfm_64bit([Values(0u, 31u)] uint rd,
@@ -127,4 +127,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
index 2c431fb23a..1bad4c87d7 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
@@ -99,4 +99,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
index 1021de930f..27fe241188 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
@@ -107,4 +107,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs
index 379cdfd8ec..86b1f092ac 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs
@@ -202,4 +202,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs
index c86d3996ee..aab0097664 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs
@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
{
#if Misc
-#region "ValueSource (Types)"
+ #region "ValueSource (Types)"
private static IEnumerable _1S_F_()
{
yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
@@ -24,19 +24,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x00000000007FFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x0000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0x00000000FF800000ul; // -Infinity
yield return 0x000000007F800000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
@@ -54,15 +54,15 @@ namespace Ryujinx.Tests.Cpu
yield return (grbg << 32) | rnd2;
}
}
-#endregion
+ #endregion
- private const int RndCnt = 2;
+ private const int RndCnt = 2;
- private static readonly bool NoZeros = false;
- private static readonly bool NoInfs = false;
- private static readonly bool NoNaNs = false;
+ private static readonly bool _noZeros = false;
+ private static readonly bool _noInfs = false;
+ private static readonly bool _noNaNs = false;
-#region "AluImm & Csel"
+ #region "AluImm & Csel"
[Test, Pairwise]
public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
@@ -73,10 +73,10 @@ namespace Ryujinx.Tests.Cpu
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
0b1100u, 0b1101u)] uint cond) // GT, LE>
{
- uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0
+ uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0
uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
- opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
+ opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
SetContext(x0: xn);
@@ -98,10 +98,10 @@ namespace Ryujinx.Tests.Cpu
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
0b1100u, 0b1101u)] uint cond) // GT, LE>
{
- uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0
+ uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0
uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
- opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
+ opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
SetContext(x0: wn);
@@ -123,10 +123,10 @@ namespace Ryujinx.Tests.Cpu
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
0b1100u, 0b1101u)] uint cond) // GT, LE>
{
- uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0
+ uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0
uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
- opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
+ opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
SetContext(x0: xn);
@@ -148,10 +148,10 @@ namespace Ryujinx.Tests.Cpu
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
0b1100u, 0b1101u)] uint cond) // GT, LE>
{
- uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0
+ uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0
uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
- opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
+ opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
SetContext(x0: wn);
@@ -162,10 +162,11 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
-#endregion
+ #endregion
+ // Roots.
[Explicit]
- [TestCase(0xFFFFFFFDu)] // Roots.
+ [TestCase(0xFFFFFFFDu)]
[TestCase(0x00000005u)]
public void Misc1(uint a)
{
@@ -196,25 +197,26 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetContext().GetX(0), Is.Zero);
}
+ // 18 integer solutions.
[Explicit]
- [TestCase(-20f, -5f)] // 18 integer solutions.
- [TestCase(-12f, -6f)]
- [TestCase(-12f, 3f)]
- [TestCase( -8f, -8f)]
- [TestCase( -6f, -12f)]
- [TestCase( -5f, -20f)]
- [TestCase( -4f, 2f)]
- [TestCase( -3f, 12f)]
- [TestCase( -2f, 4f)]
- [TestCase( 2f, -4f)]
- [TestCase( 3f, -12f)]
- [TestCase( 4f, -2f)]
- [TestCase( 5f, 20f)]
- [TestCase( 6f, 12f)]
- [TestCase( 8f, 8f)]
- [TestCase( 12f, -3f)]
- [TestCase( 12f, 6f)]
- [TestCase( 20f, 5f)]
+ [TestCase(-20f, -5f)]
+ [TestCase(-12f, -6f)]
+ [TestCase(-12f, 3f)]
+ [TestCase(-8f, -8f)]
+ [TestCase(-6f, -12f)]
+ [TestCase(-5f, -20f)]
+ [TestCase(-4f, 2f)]
+ [TestCase(-3f, 12f)]
+ [TestCase(-2f, 4f)]
+ [TestCase(2f, -4f)]
+ [TestCase(3f, -12f)]
+ [TestCase(4f, -2f)]
+ [TestCase(5f, 20f)]
+ [TestCase(6f, 12f)]
+ [TestCase(8f, 8f)]
+ [TestCase(12f, -3f)]
+ [TestCase(12f, 6f)]
+ [TestCase(20f, 5f)]
public void Misc2(float a, float b)
{
// 1 / ((1 / a + 1 / b) ^ 2) = 16
@@ -242,25 +244,26 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetContext().GetV(0).As(), Is.EqualTo(16f));
}
+ // 18 integer solutions.
[Explicit]
- [TestCase(-20d, -5d)] // 18 integer solutions.
- [TestCase(-12d, -6d)]
- [TestCase(-12d, 3d)]
- [TestCase( -8d, -8d)]
- [TestCase( -6d, -12d)]
- [TestCase( -5d, -20d)]
- [TestCase( -4d, 2d)]
- [TestCase( -3d, 12d)]
- [TestCase( -2d, 4d)]
- [TestCase( 2d, -4d)]
- [TestCase( 3d, -12d)]
- [TestCase( 4d, -2d)]
- [TestCase( 5d, 20d)]
- [TestCase( 6d, 12d)]
- [TestCase( 8d, 8d)]
- [TestCase( 12d, -3d)]
- [TestCase( 12d, 6d)]
- [TestCase( 20d, 5d)]
+ [TestCase(-20d, -5d)]
+ [TestCase(-12d, -6d)]
+ [TestCase(-12d, 3d)]
+ [TestCase(-8d, -8d)]
+ [TestCase(-6d, -12d)]
+ [TestCase(-5d, -20d)]
+ [TestCase(-4d, 2d)]
+ [TestCase(-3d, 12d)]
+ [TestCase(-2d, 4d)]
+ [TestCase(2d, -4d)]
+ [TestCase(3d, -12d)]
+ [TestCase(4d, -2d)]
+ [TestCase(5d, 20d)]
+ [TestCase(6d, 12d)]
+ [TestCase(8d, 8d)]
+ [TestCase(12d, -3d)]
+ [TestCase(12d, 6d)]
+ [TestCase(20d, 5d)]
public void Misc3(double a, double b)
{
// 1 / ((1 / a + 1 / b) ^ 2) = 16
@@ -291,7 +294,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Ignore("The Tester supports only one return point.")]
public void MiscF([Range(0u, 92u, 1u)] uint a)
{
- ulong Fn(uint n)
+ static ulong Fn(uint n)
{
ulong x = 0, y = 1, z;
@@ -395,9 +398,9 @@ namespace Ryujinx.Tests.Cpu
}
[Explicit]
- [TestCase( 0ul)]
- [TestCase( 1ul)]
- [TestCase( 2ul)]
+ [TestCase(0ul)]
+ [TestCase(1ul)]
+ [TestCase(2ul)]
[TestCase(42ul)]
public void SanityCheck(ulong a)
{
@@ -439,8 +442,8 @@ namespace Ryujinx.Tests.Cpu
v1: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()),
v2: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()),
overflow: TestContext.CurrentContext.Random.NextBool(),
- carry: TestContext.CurrentContext.Random.NextBool(),
- zero: TestContext.CurrentContext.Random.NextBool(),
+ carry: TestContext.CurrentContext.Random.NextBool(),
+ zero: TestContext.CurrentContext.Random.NextBool(),
negative: TestContext.CurrentContext.Random.NextBool());
Opcode(0xBD400001); // LDR S1, [X0,#0]
@@ -463,8 +466,8 @@ namespace Ryujinx.Tests.Cpu
v0: MakeVectorE0E1(a, TestContext.CurrentContext.Random.NextULong()),
v1: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()),
overflow: TestContext.CurrentContext.Random.NextBool(),
- carry: TestContext.CurrentContext.Random.NextBool(),
- zero: TestContext.CurrentContext.Random.NextBool(),
+ carry: TestContext.CurrentContext.Random.NextBool(),
+ zero: TestContext.CurrentContext.Random.NextBool(),
negative: TestContext.CurrentContext.Random.NextBool());
Opcode(0x1E202008); // FCMP S0, #0.0
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs b/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs
index e61150132c..e984a15848 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs
@@ -11,7 +11,7 @@ namespace Ryujinx.Tests.Cpu
{
#if Misc32
-#region "ValueSource (Types)"
+ #region "ValueSource (Types)"
private static IEnumerable _1S_F_()
{
yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
@@ -23,19 +23,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x00000000007FFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x0000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0x00000000FF800000ul; // -Infinity
yield return 0x000000007F800000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
@@ -53,13 +53,13 @@ namespace Ryujinx.Tests.Cpu
yield return (grbg << 32) | rnd2;
}
}
-#endregion
+ #endregion
private const int RndCnt = 2;
- private static readonly bool NoZeros = false;
- private static readonly bool NoInfs = false;
- private static readonly bool NoNaNs = false;
+ private static readonly bool _noZeros = false;
+ private static readonly bool _noInfs = false;
+ private static readonly bool _noNaNs = false;
[Test, Pairwise]
public void Vmsr_Vcmp_Vmrs([ValueSource(nameof(_1S_F_))] ulong a,
@@ -75,10 +75,10 @@ namespace Ryujinx.Tests.Cpu
? TestContext.CurrentContext.Random.NextUInt(0xf) << 28
: TestContext.CurrentContext.Random.NextUInt();
- bool v = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
- bool c = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
- bool z = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
- bool n = mode3 ? TestContext.CurrentContext.Random.NextBool() : false;
+ bool v = mode3 && TestContext.CurrentContext.Random.NextBool();
+ bool c = mode3 && TestContext.CurrentContext.Random.NextBool();
+ bool z = mode3 && TestContext.CurrentContext.Random.NextBool();
+ bool n = mode3 && TestContext.CurrentContext.Random.NextBool();
int fpscr = mode1
? (int)TestContext.CurrentContext.Random.NextUInt()
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMov.cs b/src/Ryujinx.Tests/Cpu/CpuTestMov.cs
index c437560a23..c8ee3857ee 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestMov.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestMov.cs
@@ -8,7 +8,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestMov : CpuTest
{
#if Mov
- private const int RndCnt = 2;
+ private const int RndCnt = 2;
[Test, Pairwise, Description("MOVK , #{, LSL #}")]
public void Movk_64bit([Values(0u, 31u)] uint rd,
@@ -109,4 +109,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMul.cs b/src/Ryujinx.Tests/Cpu/CpuTestMul.cs
index c94bcbdb6e..164ed97731 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestMul.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestMul.cs
@@ -223,4 +223,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs b/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs
index 0743e913cc..58da762dd5 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
{
#if Mul32
-#region "ValueSource (Opcodes)"
+ #region "ValueSource (Opcodes)"
private static uint[] _Smlabb_Smlabt_Smlatb_Smlatt_()
{
return new[]
@@ -49,10 +49,10 @@ namespace Ryujinx.Tests.Cpu
0xe12000e0u, // SMULWT R0, R0, R0
};
}
-#endregion
+ #endregion
[Test, Pairwise, Description("SMLA , , , ")]
- public void Smla___32bit([ValueSource("_Smlabb_Smlabt_Smlatb_Smlatt_")] uint opcode,
+ public void Smla___32bit([ValueSource(nameof(_Smlabb_Smlabt_Smlatb_Smlatt_))] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint ra,
@@ -74,7 +74,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SMLAW , , , ")]
- public void Smlaw__32bit([ValueSource("_Smlawb_Smlawt_")] uint opcode,
+ public void Smlaw__32bit([ValueSource(nameof(_Smlawb_Smlawt_))] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint ra,
@@ -96,7 +96,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SMUL , , ")]
- public void Smul___32bit([ValueSource("_Smulbb_Smulbt_Smultb_Smultt_")] uint opcode,
+ public void Smul___32bit([ValueSource(nameof(_Smulbb_Smulbt_Smultb_Smultt_))] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint rd,
@@ -115,7 +115,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SMULW , , ")]
- public void Smulw__32bit([ValueSource("_Smulwb_Smulwt_")] uint opcode,
+ public void Smulw__32bit([ValueSource(nameof(_Smulwb_Smulwt_))] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint rd,
@@ -134,4 +134,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
\ No newline at end of file
+}
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 7c68c0fa18..4c568a8f4b 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
{
#if Simd
-#region "Helper methods"
+ #region "Helper methods"
private static byte GenLeadingSignsMinus8(int cnt) // 0 <= cnt <= 7
{
return (byte)(~(uint)GenLeadingZeros8(cnt + 1));
@@ -45,10 +45,17 @@ namespace Ryujinx.Tests.Cpu
private static byte GenLeadingZeros8(int cnt) // 0 <= cnt <= 8
{
- if (cnt == 8) return 0;
- if (cnt == 7) return 1;
+ if (cnt == 8)
+ {
+ return 0;
+ }
- byte rnd = TestContext.CurrentContext.Random.NextByte();
+ if (cnt == 7)
+ {
+ return 1;
+ }
+
+ byte rnd = TestContext.CurrentContext.Random.NextByte();
sbyte mask = sbyte.MinValue;
return (byte)(((uint)rnd >> (cnt + 1)) | ((uint)((byte)mask) >> cnt));
@@ -56,120 +63,160 @@ namespace Ryujinx.Tests.Cpu
private static ushort GenLeadingZeros16(int cnt) // 0 <= cnt <= 16
{
- if (cnt == 16) return 0;
- if (cnt == 15) return 1;
+ if (cnt == 16)
+ {
+ return 0;
+ }
- ushort rnd = TestContext.CurrentContext.Random.NextUShort();
- short mask = short.MinValue;
+ if (cnt == 15)
+ {
+ return 1;
+ }
+
+ ushort rnd = TestContext.CurrentContext.Random.NextUShort();
+ short mask = short.MinValue;
return (ushort)(((uint)rnd >> (cnt + 1)) | ((uint)((ushort)mask) >> cnt));
}
private static uint GenLeadingZeros32(int cnt) // 0 <= cnt <= 32
{
- if (cnt == 32) return 0u;
- if (cnt == 31) return 1u;
+ if (cnt == 32)
+ {
+ return 0u;
+ }
- uint rnd = TestContext.CurrentContext.Random.NextUInt();
- int mask = int.MinValue;
+ if (cnt == 31)
+ {
+ return 1u;
+ }
+
+ uint rnd = TestContext.CurrentContext.Random.NextUInt();
+ int mask = int.MinValue;
return (rnd >> (cnt + 1)) | ((uint)mask >> cnt);
}
-#endregion
+ #endregion
-#region "ValueSource (Types)"
+ #region "ValueSource (Types)"
private static ulong[] _1B1H1S1D_()
{
- return new[] { 0x0000000000000000ul, 0x000000000000007Ful,
- 0x0000000000000080ul, 0x00000000000000FFul,
- 0x0000000000007FFFul, 0x0000000000008000ul,
- 0x000000000000FFFFul, 0x000000007FFFFFFFul,
- 0x0000000080000000ul, 0x00000000FFFFFFFFul,
- 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
- 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x000000000000007Ful,
+ 0x0000000000000080ul, 0x00000000000000FFul,
+ 0x0000000000007FFFul, 0x0000000000008000ul,
+ 0x000000000000FFFFul, 0x000000007FFFFFFFul,
+ 0x0000000080000000ul, 0x00000000FFFFFFFFul,
+ 0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
+ 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _1D_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _1H1S1D_()
{
- return new[] { 0x0000000000000000ul, 0x0000000000007FFFul,
- 0x0000000000008000ul, 0x000000000000FFFFul,
- 0x000000007FFFFFFFul, 0x0000000080000000ul,
- 0x00000000FFFFFFFFul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x0000000000007FFFul,
+ 0x0000000000008000ul, 0x000000000000FFFFul,
+ 0x000000007FFFFFFFul, 0x0000000080000000ul,
+ 0x00000000FFFFFFFFul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _1S_()
{
- return new[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
- 0x0000000080000000ul, 0x00000000FFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x000000007FFFFFFFul,
+ 0x0000000080000000ul, 0x00000000FFFFFFFFul,
+ };
}
private static ulong[] _2S_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _4H_()
{
- return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _4H2S1D_()
{
- return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B4H_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B4H2S_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B4H2S1D_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static uint[] _W_()
{
- return new[] { 0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu };
+ return new[] {
+ 0x00000000u, 0x7FFFFFFFu,
+ 0x80000000u, 0xFFFFFFFFu,
+ };
}
private static ulong[] _X_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static IEnumerable _1H_F_()
@@ -183,19 +230,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x00000000000003FFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x0000000000008000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0x000000000000FC00ul; // -Infinity
yield return 0x0000000000007C00ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0x000000000000FE00ul; // -QNaN (all zeros payload)
yield return 0x000000000000FDFFul; // -SNaN (all ones payload)
@@ -225,19 +272,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x03FF03FF03FF03FFul; // +Max Subnormal
yield return 0x0001000100010001ul; // +Min Subnormal
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x8000800080008000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0xFC00FC00FC00FC00ul; // -Infinity
yield return 0x7C007C007C007C00ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0xFE00FE00FE00FE00ul; // -QNaN (all zeros payload)
yield return 0xFDFFFDFFFDFFFDFFul; // -SNaN (all ones payload)
@@ -266,19 +313,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x00000000007FFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x0000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0x00000000FF800000ul; // -Infinity
yield return 0x000000007F800000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
@@ -321,19 +368,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x00000000007FFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x0000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0x00000000FF800000ul; // -Infinity
yield return 0x000000007F800000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
@@ -370,19 +417,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x8000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0xFF800000FF800000ul; // -Infinity
yield return 0x7F8000007F800000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
@@ -424,19 +471,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x8000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0xFF800000FF800000ul; // -Infinity
yield return 0x7F8000007F800000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
@@ -473,19 +520,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x8000000000000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0xFFF0000000000000ul; // -Infinity
yield return 0x7FF0000000000000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
@@ -527,19 +574,19 @@ namespace Ryujinx.Tests.Cpu
yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
- if (!NoZeros)
+ if (!_noZeros)
{
yield return 0x8000000000000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
- if (!NoInfs)
+ if (!_noInfs)
{
yield return 0xFFF0000000000000ul; // -Infinity
yield return 0x7FF0000000000000ul; // +Infinity
}
- if (!NoNaNs)
+ if (!_noNaNs)
{
yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
@@ -642,9 +689,9 @@ namespace Ryujinx.Tests.Cpu
(cnt << 24) | (cnt << 16) | (cnt << 08) | cnt;
}
}
-#endregion
+ #endregion
-#region "ValueSource (Opcodes)"
+ #region "ValueSource (Opcodes)"
private static uint[] _SU_Add_Max_Min_V_V_8BB_4HH_()
{
return new[]
@@ -653,7 +700,7 @@ namespace Ryujinx.Tests.Cpu
0x0E30A800u, // SMAXV B0, V0.8B
0x0E31A800u, // SMINV B0, V0.8B
0x2E30A800u, // UMAXV B0, V0.8B
- 0x2E31A800u // UMINV B0, V0.8B
+ 0x2E31A800u, // UMINV B0, V0.8B
};
}
@@ -665,7 +712,7 @@ namespace Ryujinx.Tests.Cpu
0x4E30A800u, // SMAXV B0, V0.16B
0x4E31A800u, // SMINV B0, V0.16B
0x6E30A800u, // UMAXV B0, V0.16B
- 0x6E31A800u // UMINV B0, V0.16B
+ 0x6E31A800u, // UMINV B0, V0.16B
};
}
@@ -676,7 +723,7 @@ namespace Ryujinx.Tests.Cpu
0x1E20C020u, // FABS S0, S1
0x1E214020u, // FNEG S0, S1
0x5EA1F820u, // FRECPX S0, S1
- 0x1E21C020u // FSQRT S0, S1
+ 0x1E21C020u, // FSQRT S0, S1
};
}
@@ -687,7 +734,7 @@ namespace Ryujinx.Tests.Cpu
0x1E60C020u, // FABS D0, D1
0x1E614020u, // FNEG D0, D1
0x5EE1F820u, // FRECPX D0, D1
- 0x1E61C020u // FSQRT D0, D1
+ 0x1E61C020u, // FSQRT D0, D1
};
}
@@ -697,7 +744,7 @@ namespace Ryujinx.Tests.Cpu
{
0x0EA0F800u, // FABS V0.2S, V0.2S
0x2EA0F800u, // FNEG V0.2S, V0.2S
- 0x2EA1F800u // FSQRT V0.2S, V0.2S
+ 0x2EA1F800u, // FSQRT V0.2S, V0.2S
};
}
@@ -707,7 +754,7 @@ namespace Ryujinx.Tests.Cpu
{
0x4EE0F800u, // FABS V0.2D, V0.2D
0x6EE0F800u, // FNEG V0.2D, V0.2D
- 0x6EE1F800u // FSQRT V0.2D, V0.2D
+ 0x6EE1F800u, // FSQRT V0.2D, V0.2D
};
}
@@ -717,7 +764,7 @@ namespace Ryujinx.Tests.Cpu
{
0x7E30D820u, // FADDP S0, V1.2S
0x7E30C820u, // FMAXNMP S0, V1.2S
- 0x7EB0C820u // FMINNMP S0, V1.2S
+ 0x7EB0C820u, // FMINNMP S0, V1.2S
};
}
@@ -727,7 +774,7 @@ namespace Ryujinx.Tests.Cpu
{
0x7E70D820u, // FADDP D0, V1.2D
0x7E70C820u, // FMAXNMP D0, V1.2D
- 0x7EF0C820u // FMINNMP D0, V1.2D
+ 0x7EF0C820u, // FMINNMP D0, V1.2D
};
}
@@ -739,7 +786,7 @@ namespace Ryujinx.Tests.Cpu
0x7EA0C820u, // FCMGE S0, S1, #0.0
0x5EA0C820u, // FCMGT S0, S1, #0.0
0x7EA0D820u, // FCMLE S0, S1, #0.0
- 0x5EA0E820u // FCMLT S0, S1, #0.0
+ 0x5EA0E820u, // FCMLT S0, S1, #0.0
};
}
@@ -751,7 +798,7 @@ namespace Ryujinx.Tests.Cpu
0x7EE0C820u, // FCMGE D0, D1, #0.0
0x5EE0C820u, // FCMGT D0, D1, #0.0
0x7EE0D820u, // FCMLE D0, D1, #0.0
- 0x5EE0E820u // FCMLT D0, D1, #0.0
+ 0x5EE0E820u, // FCMLT D0, D1, #0.0
};
}
@@ -763,7 +810,7 @@ namespace Ryujinx.Tests.Cpu
0x2EA0C800u, // FCMGE V0.2S, V0.2S, #0.0
0x0EA0C800u, // FCMGT V0.2S, V0.2S, #0.0
0x2EA0D800u, // FCMLE V0.2S, V0.2S, #0.0
- 0x0EA0E800u // FCMLT V0.2S, V0.2S, #0.0
+ 0x0EA0E800u, // FCMLT V0.2S, V0.2S, #0.0
};
}
@@ -775,7 +822,7 @@ namespace Ryujinx.Tests.Cpu
0x6EE0C800u, // FCMGE V0.2D, V0.2D, #0.0
0x4EE0C800u, // FCMGT V0.2D, V0.2D, #0.0
0x6EE0D800u, // FCMLE V0.2D, V0.2D, #0.0
- 0x4EE0E800u // FCMLT V0.2D, V0.2D, #0.0
+ 0x4EE0E800u, // FCMLT V0.2D, V0.2D, #0.0
};
}
@@ -784,7 +831,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x1E202028u, // FCMP S1, #0.0
- 0x1E202038u // FCMPE S1, #0.0
+ 0x1E202038u, // FCMPE S1, #0.0
};
}
@@ -793,7 +840,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x1E602028u, // FCMP D1, #0.0
- 0x1E602038u // FCMPE D1, #0.0
+ 0x1E602038u, // FCMPE D1, #0.0
};
}
@@ -801,7 +848,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E22C020u // FCVT D0, S1
+ 0x1E22C020u, // FCVT D0, S1
};
}
@@ -809,7 +856,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E624020u // FCVT S0, D1
+ 0x1E624020u, // FCVT S0, D1
};
}
@@ -817,7 +864,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E23C020u // FCVT H0, S1
+ 0x1E23C020u, // FCVT H0, S1
};
}
@@ -825,7 +872,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E63C020u // FCVT H0, D1
+ 0x1E63C020u, // FCVT H0, D1
};
}
@@ -833,7 +880,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1EE24020u // FCVT S0, H1
+ 0x1EE24020u, // FCVT S0, H1
};
}
@@ -841,7 +888,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1EE2C020u // FCVT D0, H1
+ 0x1EE2C020u, // FCVT D0, H1
};
}
@@ -854,7 +901,7 @@ namespace Ryujinx.Tests.Cpu
0x5E21A820u, // FCVTNS S0, S1
0x7E21A820u, // FCVTNU S0, S1
0x5EA1B820u, // FCVTZS S0, S1
- 0x7EA1B820u // FCVTZU S0, S1
+ 0x7EA1B820u, // FCVTZU S0, S1
};
}
@@ -867,7 +914,7 @@ namespace Ryujinx.Tests.Cpu
0x5E61A820u, // FCVTNS D0, D1
0x7E61A820u, // FCVTNU D0, D1
0x5EE1B820u, // FCVTZS D0, D1
- 0x7EE1B820u // FCVTZU D0, D1
+ 0x7EE1B820u, // FCVTZU D0, D1
};
}
@@ -881,7 +928,7 @@ namespace Ryujinx.Tests.Cpu
0x0E21A800u, // FCVTNS V0.2S, V0.2S
0x2E21A800u, // FCVTNU V0.2S, V0.2S
0x0EA1B800u, // FCVTZS V0.2S, V0.2S
- 0x2EA1B800u // FCVTZU V0.2S, V0.2S
+ 0x2EA1B800u, // FCVTZU V0.2S, V0.2S
};
}
@@ -895,7 +942,7 @@ namespace Ryujinx.Tests.Cpu
0x4E61A800u, // FCVTNS V0.2D, V0.2D
0x6E61A800u, // FCVTNU V0.2D, V0.2D
0x4EE1B800u, // FCVTZS V0.2D, V0.2D
- 0x6EE1B800u // FCVTZU V0.2D, V0.2D
+ 0x6EE1B800u, // FCVTZU V0.2D, V0.2D
};
}
@@ -903,7 +950,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x0E217800u // FCVTL V0.4S, V0.4H
+ 0x0E217800u, // FCVTL V0.4S, V0.4H
};
}
@@ -911,7 +958,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x0E617800u // FCVTL V0.2D, V0.2S
+ 0x0E617800u, // FCVTL V0.2D, V0.2S
};
}
@@ -919,7 +966,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x0E216800u // FCVTN V0.4H, V0.4S
+ 0x0E216800u, // FCVTN V0.4H, V0.4S
};
}
@@ -927,7 +974,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x0E616800u // FCVTN V0.2S, V0.2D
+ 0x0E616800u, // FCVTN V0.2S, V0.2D
};
}
@@ -938,7 +985,7 @@ namespace Ryujinx.Tests.Cpu
0x6E30C800u, // FMAXNMV S0, V0.4S
0x6E30F800u, // FMAXV S0, V0.4S
0x6EB0C800u, // FMINNMV S0, V0.4S
- 0x6EB0F800u // FMINV S0, V0.4S
+ 0x6EB0F800u, // FMINV S0, V0.4S
};
}
@@ -946,7 +993,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E260000u // FMOV W0, S0
+ 0x1E260000u, // FMOV W0, S0
};
}
@@ -954,7 +1001,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x9E660000u // FMOV X0, D0
+ 0x9E660000u, // FMOV X0, D0
};
}
@@ -962,7 +1009,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x9EAE0000u // FMOV X0, V0.D[1]
+ 0x9EAE0000u, // FMOV X0, V0.D[1]
};
}
@@ -970,7 +1017,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E270000u // FMOV S0, W0
+ 0x1E270000u, // FMOV S0, W0
};
}
@@ -978,7 +1025,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x9E670000u // FMOV D0, X0
+ 0x9E670000u, // FMOV D0, X0
};
}
@@ -986,7 +1033,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x9EAF0000u // FMOV V0.D[1], X0
+ 0x9EAF0000u, // FMOV V0.D[1], X0
};
}
@@ -994,7 +1041,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E204020u // FMOV S0, S1
+ 0x1E204020u, // FMOV S0, S1
};
}
@@ -1002,7 +1049,7 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x1E604020u // FMOV D0, D1
+ 0x1E604020u, // FMOV D0, D1
};
}
@@ -1011,7 +1058,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x5EA1D820u, // FRECPE S0, S1
- 0x7EA1D820u // FRSQRTE S0, S1
+ 0x7EA1D820u, // FRSQRTE S0, S1
};
}
@@ -1020,7 +1067,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x5EE1D820u, // FRECPE D0, D1
- 0x7EE1D820u // FRSQRTE D0, D1
+ 0x7EE1D820u, // FRSQRTE D0, D1
};
}
@@ -1029,7 +1076,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x0EA1D800u, // FRECPE V0.2S, V0.2S
- 0x2EA1D800u // FRSQRTE V0.2S, V0.2S
+ 0x2EA1D800u, // FRSQRTE V0.2S, V0.2S
};
}
@@ -1038,7 +1085,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x4EE1D800u, // FRECPE V0.2D, V0.2D
- 0x6EE1D800u // FRSQRTE V0.2D, V0.2D
+ 0x6EE1D800u, // FRSQRTE V0.2D, V0.2D
};
}
@@ -1050,7 +1097,7 @@ namespace Ryujinx.Tests.Cpu
0x1E254020u, // FRINTM S0, S1
0x1E244020u, // FRINTN S0, S1
0x1E24C020u, // FRINTP S0, S1
- 0x1E25C020u // FRINTZ S0, S1
+ 0x1E25C020u, // FRINTZ S0, S1
};
}
@@ -1062,7 +1109,7 @@ namespace Ryujinx.Tests.Cpu
0x1E654020u, // FRINTM D0, D1
0x1E644020u, // FRINTN D0, D1
0x1E64C020u, // FRINTP D0, D1
- 0x1E65C020u // FRINTZ D0, D1
+ 0x1E65C020u, // FRINTZ D0, D1
};
}
@@ -1074,7 +1121,7 @@ namespace Ryujinx.Tests.Cpu
0x0E219800u, // FRINTM V0.2S, V0.2S
0x0E218800u, // FRINTN V0.2S, V0.2S
0x0EA18800u, // FRINTP V0.2S, V0.2S
- 0x0EA19800u // FRINTZ V0.2S, V0.2S
+ 0x0EA19800u, // FRINTZ V0.2S, V0.2S
};
}
@@ -1086,7 +1133,7 @@ namespace Ryujinx.Tests.Cpu
0x4E619800u, // FRINTM V0.2D, V0.2D
0x4E618800u, // FRINTN V0.2D, V0.2D
0x4EE18800u, // FRINTP V0.2D, V0.2D
- 0x4EE19800u // FRINTZ V0.2D, V0.2D
+ 0x4EE19800u, // FRINTZ V0.2D, V0.2D
};
}
@@ -1095,7 +1142,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x1E27C020u, // FRINTI S0, S1
- 0x1E274020u // FRINTX S0, S1
+ 0x1E274020u, // FRINTX S0, S1
};
}
@@ -1104,7 +1151,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x1E67C020u, // FRINTI D0, D1
- 0x1E674020u // FRINTX D0, D1
+ 0x1E674020u, // FRINTX D0, D1
};
}
@@ -1113,7 +1160,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x2EA19800u, // FRINTI V0.2S, V0.2S
- 0x2E219800u // FRINTX V0.2S, V0.2S
+ 0x2E219800u, // FRINTX V0.2S, V0.2S
};
}
@@ -1122,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x6EE19800u, // FRINTI V0.2D, V0.2D
- 0x6E619800u // FRINTX V0.2D, V0.2D
+ 0x6E619800u, // FRINTX V0.2D, V0.2D
};
}
@@ -1131,7 +1178,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x0E303800u, // SADDLV H0, V0.8B
- 0x2E303800u // UADDLV H0, V0.8B
+ 0x2E303800u, // UADDLV H0, V0.8B
};
}
@@ -1140,7 +1187,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x4E303800u, // SADDLV H0, V0.16B
- 0x6E303800u // UADDLV H0, V0.16B
+ 0x6E303800u, // UADDLV H0, V0.16B
};
}
@@ -1149,7 +1196,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x5E21D820u, // SCVTF S0, S1
- 0x7E21D820u // UCVTF S0, S1
+ 0x7E21D820u, // UCVTF S0, S1
};
}
@@ -1158,7 +1205,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x5E61D820u, // SCVTF D0, D1
- 0x7E61D820u // UCVTF D0, D1
+ 0x7E61D820u, // UCVTF D0, D1
};
}
@@ -1167,7 +1214,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x0E21D800u, // SCVTF V0.2S, V0.2S
- 0x2E21D800u // UCVTF V0.2S, V0.2S
+ 0x2E21D800u, // UCVTF V0.2S, V0.2S
};
}
@@ -1176,7 +1223,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x4E61D800u, // SCVTF V0.2D, V0.2D
- 0x6E61D800u // UCVTF V0.2D, V0.2D
+ 0x6E61D800u, // UCVTF V0.2D, V0.2D
};
}
@@ -1185,7 +1232,7 @@ namespace Ryujinx.Tests.Cpu
return new[]
{
0x5E280800u, // SHA1H S0, S0
- 0x5E281800u // SHA1SU1 V0.4S, V0.4S
+ 0x5E281800u, // SHA1SU1 V0.4S, V0.4S
};
}
@@ -1193,19 +1240,19 @@ namespace Ryujinx.Tests.Cpu
{
return new[]
{
- 0x5E282800u // SHA256SU0 V0.4S, V0.4S
+ 0x5E282800u, // SHA256SU0 V0.4S, V0.4S
};
}
-#endregion
+ #endregion
private const int RndCnt = 2;
- private static readonly bool NoZeros = false;
- private static readonly bool NoInfs = false;
- private static readonly bool NoNaNs = false;
+ private static readonly bool _noZeros = false;
+ private static readonly bool _noInfs = false;
+ private static readonly bool _noNaNs = false;
[Test, Pairwise, Description("ABS , ")]
- public void Abs_S_D([Values(0u)] uint rd,
+ public void Abs_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1222,7 +1269,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ABS ., .")]
- public void Abs_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Abs_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1241,7 +1288,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ABS ., .")]
- public void Abs_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Abs_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -1260,7 +1307,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("ADDP , .")]
- public void Addp_S_2DD([Values(0u)] uint rd,
+ public void Addp_S_2DD([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1278,7 +1325,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void SU_Add_Max_Min_V_V_8BB_4HH([ValueSource(nameof(_SU_Add_Max_Min_V_V_8BB_4HH_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H_))] ulong z,
[ValueSource(nameof(_8B4H_))] ulong a,
@@ -1297,7 +1344,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void SU_Add_Max_Min_V_V_16BB_8HH_4SS([ValueSource(nameof(_SU_Add_Max_Min_V_V_16BB_8HH_4SS_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1315,9 +1362,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CLS ., .")]
- public void Cls_V_8B_16B([Values(0u)] uint rd,
+ public void Cls_V_8B_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_8B_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_8B_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenLeadingSigns8B_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
@@ -1334,9 +1381,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CLS ., .")]
- public void Cls_V_4H_8H([Values(0u)] uint rd,
+ public void Cls_V_4H_8H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_4H_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenLeadingSigns4H_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
@@ -1353,9 +1400,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CLS ., .")]
- public void Cls_V_2S_4S([Values(0u)] uint rd,
+ public void Cls_V_2S_4S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_2S_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenLeadingSigns2S_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
@@ -1372,9 +1419,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CLZ ., .")]
- public void Clz_V_8B_16B([Values(0u)] uint rd,
+ public void Clz_V_8B_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_8B_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_8B_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenLeadingZeros8B_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
{
@@ -1391,9 +1438,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CLZ ., .")]
- public void Clz_V_4H_8H([Values(0u)] uint rd,
+ public void Clz_V_4H_8H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_4H_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenLeadingZeros4H_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
{
@@ -1410,9 +1457,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CLZ ., .")]
- public void Clz_V_2S_4S([Values(0u)] uint rd,
+ public void Clz_V_2S_4S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_2S_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenLeadingZeros2S_))] ulong a,
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
{
@@ -1429,7 +1476,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMEQ , , #0")]
- public void Cmeq_S_D([Values(0u)] uint rd,
+ public void Cmeq_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1446,7 +1493,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMEQ ., ., #0")]
- public void Cmeq_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Cmeq_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1465,7 +1512,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMEQ ., ., #0")]
- public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -1484,7 +1531,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGE , , #0")]
- public void Cmge_S_D([Values(0u)] uint rd,
+ public void Cmge_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1501,7 +1548,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGE ., ., #0")]
- public void Cmge_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Cmge_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1520,7 +1567,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGE ., ., #0")]
- public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -1539,7 +1586,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGT , , #0")]
- public void Cmgt_S_D([Values(0u)] uint rd,
+ public void Cmgt_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1556,7 +1603,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGT ., ., #0")]
- public void Cmgt_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Cmgt_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1575,7 +1622,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMGT ., ., #0")]
- public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -1594,7 +1641,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMLE , , #0")]
- public void Cmle_S_D([Values(0u)] uint rd,
+ public void Cmle_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1611,7 +1658,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMLE ., ., #0")]
- public void Cmle_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Cmle_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1630,7 +1677,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMLE ., ., #0")]
- public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -1649,7 +1696,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMLT , , #0")]
- public void Cmlt_S_D([Values(0u)] uint rd,
+ public void Cmlt_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -1666,7 +1713,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMLT ., ., #0")]
- public void Cmlt_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Cmlt_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -1685,7 +1732,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CMLT ., ., #0")]
- public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -1704,9 +1751,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CNT ., .")]
- public void Cnt_V_8B([Values(0u)] uint rd,
+ public void Cnt_V_8B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_8B_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_8B_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenPopCnt8B_))] ulong a)
{
uint opcode = 0x0E205800; // CNT V0.8B, V0.8B
@@ -1721,9 +1768,9 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("CNT ., .")]
- public void Cnt_V_16B([Values(0u)] uint rd,
+ public void Cnt_V_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
- [ValueSource(nameof(_8B_))] [Random(RndCnt)] ulong z,
+ [ValueSource(nameof(_8B_))][Random(RndCnt)] ulong z,
[ValueSource(nameof(_GenPopCnt8B_))] ulong a)
{
uint opcode = 0x4E205800; // CNT V0.16B, V0.16B
@@ -1737,7 +1784,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Abs_Neg_Recpx_Sqrt_S_S([ValueSource(nameof(_F_Abs_Neg_Recpx_Sqrt_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a)
{
@@ -1755,7 +1803,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Abs_Neg_Recpx_Sqrt_S_D([ValueSource(nameof(_F_Abs_Neg_Recpx_Sqrt_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a)
{
@@ -1773,9 +1822,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Abs_Neg_Sqrt_V_2S_4S([ValueSource(nameof(_F_Abs_Neg_Sqrt_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -1797,9 +1847,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Abs_Neg_Sqrt_V_2D([ValueSource(nameof(_F_Abs_Neg_Sqrt_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong z,
[ValueSource(nameof(_1D_F_))] ulong a)
@@ -1819,7 +1870,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Add_Max_Min_Nm_P_S_2SS([ValueSource(nameof(_F_Add_Max_Min_Nm_P_S_2SS_))] uint opcodes,
[ValueSource(nameof(_2S_F_))] ulong a)
{
@@ -1838,7 +1890,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Add_Max_Min_Nm_P_S_2DD([ValueSource(nameof(_F_Add_Max_Min_Nm_P_S_2DD_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a0,
[ValueSource(nameof(_1D_F_))] ulong a1)
@@ -1858,7 +1911,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cm_EqGeGtLeLt_S_S([ValueSource(nameof(_F_Cm_EqGeGtLeLt_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a)
{
@@ -1875,7 +1929,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cm_EqGeGtLeLt_S_D([ValueSource(nameof(_F_Cm_EqGeGtLeLt_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a)
{
@@ -1892,9 +1947,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cm_EqGeGtLeLt_V_2S_4S([ValueSource(nameof(_F_Cm_EqGeGtLeLt_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -1915,9 +1971,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cm_EqGeGtLeLt_V_2D([ValueSource(nameof(_F_Cm_EqGeGtLeLt_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong z,
[ValueSource(nameof(_1D_F_))] ulong a)
@@ -1936,7 +1993,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cmp_Cmpe_S_S([ValueSource(nameof(_F_Cmp_Cmpe_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a)
{
@@ -1952,7 +2010,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cmp_Cmpe_S_D([ValueSource(nameof(_F_Cmp_Cmpe_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a)
{
@@ -1968,7 +2027,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_S_SD([ValueSource(nameof(_F_Cvt_S_SD_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a)
{
@@ -1981,7 +2041,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_S_DS([ValueSource(nameof(_F_Cvt_S_DS_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a)
{
@@ -1994,7 +2055,9 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit] // Unicorn seems to default all rounding modes to RMode.Rn.
+ // Unicorn seems to default all rounding modes to RMode.Rn.
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_S_SH([ValueSource(nameof(_F_Cvt_S_SH_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a,
[Values(RMode.Rn)] RMode rMode)
@@ -2010,7 +2073,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_S_DH([ValueSource(nameof(_F_Cvt_S_DH_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a,
[Values(RMode.Rn)] RMode rMode)
@@ -2026,7 +2090,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_S_HS([ValueSource(nameof(_F_Cvt_S_HS_))] uint opcodes,
[ValueSource(nameof(_1H_F_))] ulong a)
{
@@ -2039,7 +2104,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_S_HD([ValueSource(nameof(_F_Cvt_S_HD_))] uint opcodes,
[ValueSource(nameof(_1H_F_))] ulong a)
{
@@ -2052,7 +2118,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_ANZ_SU_S_S([ValueSource(nameof(_F_Cvt_ANZ_SU_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_W_))] ulong a)
{
@@ -2065,7 +2132,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_ANZ_SU_S_D([ValueSource(nameof(_F_Cvt_ANZ_SU_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_X_))] ulong a)
{
@@ -2078,9 +2146,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_ANZ_SU_V_2S_4S([ValueSource(nameof(_F_Cvt_ANZ_SU_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_W_))] ulong z,
[ValueSource(nameof(_2S_F_W_))] ulong a,
@@ -2097,9 +2166,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvt_ANZ_SU_V_2D([ValueSource(nameof(_F_Cvt_ANZ_SU_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_X_))] ulong z,
[ValueSource(nameof(_1D_F_X_))] ulong a)
@@ -2114,9 +2184,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvtl_V_4H4S_8H4S([ValueSource(nameof(_F_Cvtl_V_4H4S_8H4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_4H_F_))] ulong z,
[ValueSource(nameof(_4H_F_))] ulong a,
@@ -2141,9 +2212,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvtl_V_2S2D_4S2D([ValueSource(nameof(_F_Cvtl_V_2S2D_4S2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -2160,9 +2232,11 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit] // Unicorn seems to default all rounding modes to RMode.Rn.
+ // Unicorn seems to default all rounding modes to RMode.Rn.
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvtn_V_4S4H_4S8H([ValueSource(nameof(_F_Cvtn_V_4S4H_4S8H_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -2187,9 +2261,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Cvtn_V_2D2S_2D4S([ValueSource(nameof(_F_Cvtn_V_2D2S_2D4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong z,
[ValueSource(nameof(_1D_F_))] ulong a,
@@ -2206,9 +2281,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Max_Min_Nm_V_V_4SS([ValueSource(nameof(_F_Max_Min_Nm_V_V_4SS_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a)
@@ -2228,10 +2304,11 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_Ftoi_SW([ValueSource(nameof(_F_Mov_Ftoi_SW_))] uint opcodes,
[Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_1S_F_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -2245,10 +2322,11 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_Ftoi_DX([ValueSource(nameof(_F_Mov_Ftoi_DX_))] uint opcodes,
[Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -2261,10 +2339,11 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_Ftoi1_DX([ValueSource(nameof(_F_Mov_Ftoi1_DX_))] uint opcodes,
[Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -2277,16 +2356,17 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_Itof_WS([ValueSource(nameof(_F_Mov_Itof_WS_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_W_))] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
- uint w31 = TestContext.CurrentContext.Random.NextUInt();
- ulong z = TestContext.CurrentContext.Random.NextULong();
+ uint w31 = TestContext.CurrentContext.Random.NextUInt();
+ ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
@@ -2294,16 +2374,17 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_Itof_XD([ValueSource(nameof(_F_Mov_Itof_XD_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_X_))] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
- ulong z = TestContext.CurrentContext.Random.NextULong();
+ ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
@@ -2311,16 +2392,17 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_Itof1_XD([ValueSource(nameof(_F_Mov_Itof1_XD_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_X_))] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
- ulong z = TestContext.CurrentContext.Random.NextULong();
+ ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0(z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
@@ -2328,7 +2410,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_S_S([ValueSource(nameof(_F_Mov_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a)
{
@@ -2341,7 +2424,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Mov_S_D([ValueSource(nameof(_F_Mov_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a)
{
@@ -2354,7 +2438,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Recpe_Rsqrte_S_S([ValueSource(nameof(_F_Recpe_Rsqrte_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a,
[Values(RMode.Rn)] RMode rMode)
@@ -2374,7 +2459,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Recpe_Rsqrte_S_D([ValueSource(nameof(_F_Recpe_Rsqrte_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a,
[Values(RMode.Rn)] RMode rMode)
@@ -2394,9 +2480,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Recpe_Rsqrte_V_2S_4S([ValueSource(nameof(_F_Recpe_Rsqrte_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -2420,9 +2507,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Recpe_Rsqrte_V_2D([ValueSource(nameof(_F_Recpe_Rsqrte_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong z,
[ValueSource(nameof(_1D_F_))] ulong a,
@@ -2444,7 +2532,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Dzc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_AMNPZ_S_S([ValueSource(nameof(_F_Rint_AMNPZ_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a)
{
@@ -2457,7 +2546,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_AMNPZ_S_D([ValueSource(nameof(_F_Rint_AMNPZ_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a)
{
@@ -2470,9 +2560,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_AMNPZ_V_2S_4S([ValueSource(nameof(_F_Rint_AMNPZ_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -2489,9 +2580,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_AMNPZ_V_2D([ValueSource(nameof(_F_Rint_AMNPZ_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong z,
[ValueSource(nameof(_1D_F_))] ulong a)
@@ -2506,7 +2598,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_IX_S_S([ValueSource(nameof(_F_Rint_IX_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_F_))] ulong a,
[Values] RMode rMode)
@@ -2522,7 +2615,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_IX_S_D([ValueSource(nameof(_F_Rint_IX_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_F_))] ulong a,
[Values] RMode rMode)
@@ -2538,9 +2632,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_IX_V_2S_4S([ValueSource(nameof(_F_Rint_IX_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_F_))] ulong z,
[ValueSource(nameof(_2S_F_))] ulong a,
@@ -2560,9 +2655,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void F_Rint_IX_V_2D([ValueSource(nameof(_F_Rint_IX_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_F_))] ulong z,
[ValueSource(nameof(_1D_F_))] ulong a,
@@ -2581,7 +2677,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("NEG , ")]
- public void Neg_S_D([Values(0u)] uint rd,
+ public void Neg_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -2598,7 +2694,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("NEG ., .")]
- public void Neg_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Neg_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2617,7 +2713,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("NEG ., .")]
- public void Neg_V_16B_8H_4S_2D([Values(0u)] uint rd,
+ public void Neg_V_16B_8H_4S_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
@@ -2636,7 +2732,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("NOT ., .")]
- public void Not_V_8B([Values(0u)] uint rd,
+ public void Not_V_8B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a)
@@ -2653,7 +2749,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("NOT ., .")]
- public void Not_V_16B([Values(0u)] uint rd,
+ public void Not_V_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a)
@@ -2670,7 +2766,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("RBIT ., .")]
- public void Rbit_V_8B([Values(0u)] uint rd,
+ public void Rbit_V_8B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a)
@@ -2687,7 +2783,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("RBIT ., .")]
- public void Rbit_V_16B([Values(0u)] uint rd,
+ public void Rbit_V_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a)
@@ -2704,7 +2800,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("REV16 ., .")]
- public void Rev16_V_8B([Values(0u)] uint rd,
+ public void Rev16_V_8B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a)
@@ -2721,7 +2817,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("REV16 ., .")]
- public void Rev16_V_16B([Values(0u)] uint rd,
+ public void Rev16_V_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a)
@@ -2738,7 +2834,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("REV32 ., .")]
- public void Rev32_V_8B_4H([Values(0u)] uint rd,
+ public void Rev32_V_8B_4H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H_))] ulong z,
[ValueSource(nameof(_8B4H_))] ulong a,
@@ -2757,7 +2853,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("REV32 ., .")]
- public void Rev32_V_16B_8H([Values(0u)] uint rd,
+ public void Rev32_V_16B_8H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H_))] ulong z,
[ValueSource(nameof(_8B4H_))] ulong a,
@@ -2776,7 +2872,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("REV64 ., .")]
- public void Rev64_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Rev64_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2795,7 +2891,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("REV64 ., .")]
- public void Rev64_V_16B_8H_4S([Values(0u)] uint rd,
+ public void Rev64_V_16B_8H_4S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2814,7 +2910,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SADALP ., .")]
- public void Sadalp_V_8B4H_4H2S_2S1D([Values(0u)] uint rd,
+ public void Sadalp_V_8B4H_4H2S_2S1D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2833,7 +2929,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SADALP ., .")]
- public void Sadalp_V_16B8H_8H4S_4S2D([Values(0u)] uint rd,
+ public void Sadalp_V_16B8H_8H4S_4S2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2852,7 +2948,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SADDLP ., .")]
- public void Saddlp_V_8B4H_4H2S_2S1D([Values(0u)] uint rd,
+ public void Saddlp_V_8B4H_4H2S_2S1D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2871,7 +2967,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SADDLP ., .")]
- public void Saddlp_V_16B8H_8H4S_4S2D([Values(0u)] uint rd,
+ public void Saddlp_V_16B8H_8H4S_4S2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2891,7 +2987,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void SU_Addl_V_V_8BH_4HS([ValueSource(nameof(_SU_Addl_V_V_8BH_4HS_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H_))] ulong z,
[ValueSource(nameof(_8B4H_))] ulong a,
@@ -2910,7 +3006,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void SU_Addl_V_V_16BH_8HS_4SD([ValueSource(nameof(_SU_Addl_V_V_16BH_8HS_4SD_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -2927,7 +3023,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void SU_Cvt_F_S_S([ValueSource(nameof(_SU_Cvt_F_S_S_))] uint opcodes,
[ValueSource(nameof(_1S_))] ulong a)
{
@@ -2940,7 +3037,8 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void SU_Cvt_F_S_D([ValueSource(nameof(_SU_Cvt_F_S_D_))] uint opcodes,
[ValueSource(nameof(_1D_))] ulong a)
{
@@ -2953,9 +3051,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void SU_Cvt_F_V_2S_4S([ValueSource(nameof(_SU_Cvt_F_V_2S_4S_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_))] ulong z,
[ValueSource(nameof(_2S_))] ulong a,
@@ -2972,9 +3071,10 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise] [Explicit]
+ [Test, Pairwise]
+ [Explicit]
public void SU_Cvt_F_V_2D([ValueSource(nameof(_SU_Cvt_F_V_2D_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a)
@@ -2991,7 +3091,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void Sha1h_Sha1su1_V([ValueSource(nameof(_Sha1h_Sha1su1_V_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Random(RndCnt / 2)] ulong z0, [Random(RndCnt / 2)] ulong z1,
[Random(RndCnt / 2)] ulong a0, [Random(RndCnt / 2)] ulong a1)
@@ -3008,7 +3108,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void Sha256su0_V([ValueSource(nameof(_Sha256su0_V_))] uint opcodes,
- [Values(0u)] uint rd,
+ [Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Random(RndCnt / 2)] ulong z0, [Random(RndCnt / 2)] ulong z1,
[Random(RndCnt / 2)] ulong a0, [Random(RndCnt / 2)] ulong a1)
@@ -3024,7 +3124,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SHLL{2} ., ., #")]
- public void Shll_V([Values(0u)] uint rd,
+ public void Shll_V([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -3045,7 +3145,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQABS , ")]
- public void Sqabs_S_B_H_S_D([Values(0u)] uint rd,
+ public void Sqabs_S_B_H_S_D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1B1H1S1D_))] ulong z,
[ValueSource(nameof(_1B1H1S1D_))] ulong a,
@@ -3064,7 +3164,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQABS ., .")]
- public void Sqabs_V_8B_4H_2S([Values(0u)] uint rd,
+ public void Sqabs_V_8B_4H_2S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B4H2S_))] ulong z,
[ValueSource(nameof(_8B4H2S_))] ulong a,
@@ -3083,7 +3183,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("SQABS