From 76ac31add656c71f9cfb3307f5863cc98c8d1467 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Fri, 30 Mar 2018 16:46:00 -0300
Subject: [PATCH] Add BIT instruction

---
 ChocolArm64/AOpCodeTable.cs                     |  1 +
 ChocolArm64/Instruction/AInstEmitSimdLogical.cs | 15 +++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index c2929d9bce..0d3fa29623 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -141,6 +141,7 @@ namespace ChocolArm64
             Set("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V,         typeof(AOpCodeSimdReg));
             Set("0x10111100000xxx<<x101xxxxxxxxxx", AInstEmit.Bic_Vi,        typeof(AOpCodeSimdImm));
             Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V,         typeof(AOpCodeSimdReg));
+            Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V,         typeof(AOpCodeSimdReg));
             Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V,         typeof(AOpCodeSimdReg));
             Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V,        typeof(AOpCodeSimdReg));
             Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V,        typeof(AOpCodeSimd));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
index 8fd8ea4d10..967c3d3006 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
@@ -33,6 +33,16 @@ namespace ChocolArm64.Instruction
         }
 
         public static void Bif_V(AILEmitterCtx Context)
+        {
+            EmitBitBif(Context, true);
+        }
+
+        public static void Bit_V(AILEmitterCtx Context)
+        {
+            EmitBitBif(Context, false);
+        }
+
+        public static void EmitBitBif(AILEmitterCtx Context, bool NotRm)
         {
             AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
 
@@ -47,6 +57,11 @@ namespace ChocolArm64.Instruction
 
                 EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
 
+                if (NotRm)
+                {
+                    Context.Emit(OpCodes.Not);
+                }
+
                 Context.Emit(OpCodes.And);
 
                 EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);