From efef605b260119642fa023c8488fb3ff4501cafd Mon Sep 17 00:00:00 2001 From: gdkchan Date: Fri, 2 Mar 2018 20:24:16 -0300 Subject: [PATCH] Fix REV64 (vector) instruction --- ChocolArm64/AOpCodeTable.cs | 2 +- .../Instruction/AInstEmitSimdLogical.cs | 26 ++++++++++++++----- ChocolArm64/Instruction/ASoftFallback.cs | 2 +- 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 13df4d9868..e192f5ec5e 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -230,7 +230,7 @@ namespace ChocolArm64 Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd)); Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg)); Set("0x00111100000xxx< + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + int Bytes = Context.CurrOp.GetBitsCount() >> 3; + + int Elems = Bytes >> Op.Size; + + int RevIndex = Elems - 1; + + for (int Index = 0; Index < (Bytes >> Op.Size); Index++) { - ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64)); - }; - - EmitVectorUnaryOpZx(Context, Emit); + EmitVectorExtractZx(Context, Op.Rn, RevIndex--, Op.Size); + + EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + } + + if (Op.RegisterSize == ARegisterSize.SIMD64) + { + EmitVectorZeroUpper(Context, Op.Rd); + } } } } \ No newline at end of file diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs index 5127182ddc..797d815736 100644 --- a/ChocolArm64/Instruction/ASoftFallback.cs +++ b/ChocolArm64/Instruction/ASoftFallback.cs @@ -75,7 +75,7 @@ namespace ChocolArm64.Instruction private static ulong ReverseBytes(ulong Value, RevSize Size) { - Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8); + Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8); if (Size == RevSize.Rev16) {