forked from Mirror/Ryujinx
4770cfa920
* Only enable clip distance if written to on shader * Signal InstanceId use through FeatureFlags * Shader cache version bump
664 lines
No EOL
21 KiB
C#
664 lines
No EOL
21 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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private enum MemoryRegion
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{
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Local,
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Shared
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}
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public static void Ald(EmitterContext context)
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{
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OpCodeAttribute op = (OpCodeAttribute)context.CurrOp;
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Operand primVertex = context.Copy(GetSrcC(context));
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for (int index = 0; index < op.Count; index++)
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{
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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if (rd.IsRZ)
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{
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break;
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}
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Operand src = Attribute(op.AttributeOffset + index * 4);
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context.FlagAttributeRead(src.Value);
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context.Copy(Register(rd), context.LoadAttribute(src, primVertex));
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}
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}
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public static void Ast(EmitterContext context)
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{
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OpCodeAttribute op = (OpCodeAttribute)context.CurrOp;
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for (int index = 0; index < op.Count; index++)
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{
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if (op.Rd.Index + index > RegisterConsts.RegisterZeroIndex)
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{
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break;
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}
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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Operand dest = Attribute(op.AttributeOffset + index * 4);
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context.FlagAttributeWritten(dest.Value);
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context.Copy(dest, Register(rd));
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}
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}
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public static void Atom(EmitterContext context)
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{
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OpCodeAtom op = (OpCodeAtom)context.CurrOp;
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ReductionType type = (ReductionType)op.RawOpCode.Extract(49, 2);
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int sOffset = (op.RawOpCode.Extract(28, 20) << 12) >> 12;
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, op.Ra, op.Extended, sOffset);
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Operand value = GetSrcB(context);
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Operand res = EmitAtomicOp(
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context,
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Instruction.MrGlobal,
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op.AtomicOp,
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type,
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addrLow,
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addrHigh,
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value);
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context.Copy(GetDest(context), res);
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}
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public static void Atoms(EmitterContext context)
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{
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OpCodeAtom op = (OpCodeAtom)context.CurrOp;
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ReductionType type = op.RawOpCode.Extract(28, 2) switch
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{
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0 => ReductionType.U32,
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1 => ReductionType.S32,
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2 => ReductionType.U64,
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_ => ReductionType.S64
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};
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Operand offset = context.ShiftRightU32(GetSrcA(context), Const(2));
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int sOffset = (op.RawOpCode.Extract(30, 22) << 10) >> 10;
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offset = context.IAdd(offset, Const(sOffset));
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Operand value = GetSrcB(context);
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Operand res = EmitAtomicOp(
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context,
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Instruction.MrShared,
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op.AtomicOp,
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type,
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offset,
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Const(0),
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value);
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context.Copy(GetDest(context), res);
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}
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public static void Bar(EmitterContext context)
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{
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OpCodeBarrier op = (OpCodeBarrier)context.CurrOp;
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// TODO: Support other modes.
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if (op.Mode == BarrierMode.Sync)
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{
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context.Barrier();
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid barrier mode: {op.Mode}.");
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}
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}
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public static void Ipa(EmitterContext context)
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{
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OpCodeIpa op = (OpCodeIpa)context.CurrOp;
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context.FlagAttributeRead(op.AttributeOffset);
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Operand res = Attribute(op.AttributeOffset);
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if (op.AttributeOffset >= AttributeConsts.UserAttributeBase &&
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op.AttributeOffset < AttributeConsts.UserAttributeEnd)
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{
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int index = (op.AttributeOffset - AttributeConsts.UserAttributeBase) >> 4;
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if (context.Config.ImapTypes[index].GetFirstUsedType() == PixelImap.Perspective)
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{
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res = context.FPMultiply(res, Attribute(AttributeConsts.PositionW));
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}
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}
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if (op.Mode == InterpolationMode.Default)
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{
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Operand srcB = GetSrcB(context);
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res = context.FPMultiply(res, srcB);
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}
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res = context.FPSaturate(res, op.Saturate);
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context.Copy(GetDest(context), res);
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}
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public static void Isberd(EmitterContext context)
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{
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// This instruction performs a load from ISBE memory,
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// however it seems to be only used to get some vertex
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// input data, so we instead propagate the offset so that
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// it can be used on the attribute load.
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context.Copy(GetDest(context), GetSrcA(context));
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}
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public static void Ld(EmitterContext context)
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{
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EmitLoad(context, MemoryRegion.Local);
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}
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public static void Ldc(EmitterContext context)
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{
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OpCodeLdc op = (OpCodeLdc)context.CurrOp;
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if (op.Size > IntegerSize.B64)
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{
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context.Config.GpuAccessor.Log($"Invalid LDC size: {op.Size}.");
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}
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bool isSmallInt = op.Size < IntegerSize.B32;
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int count = op.Size == IntegerSize.B64 ? 2 : 1;
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Operand slot = Const(op.Slot);
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Operand srcA = GetSrcA(context);
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if (op.IndexMode == CbIndexMode.Is ||
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op.IndexMode == CbIndexMode.Isl)
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{
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slot = context.IAdd(slot, context.BitfieldExtractU32(srcA, Const(16), Const(16)));
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srcA = context.BitwiseAnd(srcA, Const(0xffff));
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}
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Operand addr = context.IAdd(srcA, Const(op.Offset));
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Operand wordOffset = context.ShiftRightU32(addr, Const(2));
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Operand bitOffset = GetBitOffset(context, addr);
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for (int index = 0; index < count; index++)
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{
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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if (rd.IsRZ)
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{
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break;
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}
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Operand offset = context.IAdd(wordOffset, Const(index));
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Operand value = context.LoadConstant(slot, offset);
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if (isSmallInt)
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{
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value = ExtractSmallInt(context, op.Size, bitOffset, value);
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}
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context.Copy(Register(rd), value);
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}
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}
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public static void Ldg(EmitterContext context)
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{
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EmitLoadGlobal(context);
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}
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public static void Lds(EmitterContext context)
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{
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EmitLoad(context, MemoryRegion.Shared);
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}
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public static void Membar(EmitterContext context)
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{
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OpCodeMemoryBarrier op = (OpCodeMemoryBarrier)context.CurrOp;
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if (op.Level == BarrierLevel.Cta)
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{
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context.GroupMemoryBarrier();
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}
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else
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{
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context.MemoryBarrier();
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}
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}
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public static void Out(EmitterContext context)
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{
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OpCode op = context.CurrOp;
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bool emit = op.RawOpCode.Extract(39);
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bool cut = op.RawOpCode.Extract(40);
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if (!(emit || cut))
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{
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context.Config.GpuAccessor.Log("Invalid OUT encoding.");
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}
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if (emit)
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{
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context.EmitVertex();
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}
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if (cut)
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{
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context.EndPrimitive();
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}
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}
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public static void Red(EmitterContext context)
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{
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OpCodeRed op = (OpCodeRed)context.CurrOp;
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, op.Ra, op.Extended, op.Offset);
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EmitAtomicOp(
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context,
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Instruction.MrGlobal,
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op.AtomicOp,
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op.Type,
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addrLow,
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addrHigh,
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GetDest(context));
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}
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public static void St(EmitterContext context)
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{
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EmitStore(context, MemoryRegion.Local);
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}
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public static void Stg(EmitterContext context)
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{
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EmitStoreGlobal(context);
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}
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public static void Sts(EmitterContext context)
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{
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EmitStore(context, MemoryRegion.Shared);
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}
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private static Operand EmitAtomicOp(
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EmitterContext context,
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Instruction mr,
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AtomicOp op,
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ReductionType type,
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Operand addrLow,
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Operand addrHigh,
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Operand value)
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{
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Operand res = Const(0);
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switch (op)
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{
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case AtomicOp.Add:
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if (type == ReductionType.S32 || type == ReductionType.U32)
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{
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res = context.AtomicAdd(mr, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomicOp.BitwiseAnd:
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if (type == ReductionType.S32 || type == ReductionType.U32)
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{
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res = context.AtomicAnd(mr, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomicOp.BitwiseExclusiveOr:
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if (type == ReductionType.S32 || type == ReductionType.U32)
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{
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res = context.AtomicXor(mr, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomicOp.BitwiseOr:
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if (type == ReductionType.S32 || type == ReductionType.U32)
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{
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res = context.AtomicOr(mr, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomicOp.Maximum:
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if (type == ReductionType.S32)
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{
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res = context.AtomicMaxS32(mr, addrLow, addrHigh, value);
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}
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else if (type == ReductionType.U32)
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{
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res = context.AtomicMaxU32(mr, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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case AtomicOp.Minimum:
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if (type == ReductionType.S32)
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{
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res = context.AtomicMinS32(mr, addrLow, addrHigh, value);
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}
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else if (type == ReductionType.U32)
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{
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res = context.AtomicMinU32(mr, addrLow, addrHigh, value);
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}
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else
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{
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context.Config.GpuAccessor.Log($"Invalid reduction type: {type}.");
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}
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break;
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}
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return res;
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}
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private static void EmitLoad(EmitterContext context, MemoryRegion region)
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{
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OpCodeMemory op = (OpCodeMemory)context.CurrOp;
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if (op.Size > IntegerSize.B128)
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{
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context.Config.GpuAccessor.Log($"Invalid load size: {op.Size}.");
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}
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bool isSmallInt = op.Size < IntegerSize.B32;
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int count = 1;
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switch (op.Size)
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{
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case IntegerSize.B64: count = 2; break;
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case IntegerSize.B128: count = 4; break;
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}
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Operand baseOffset = context.IAdd(GetSrcA(context), Const(op.Offset));
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// Word offset = byte offset / 4 (one word = 4 bytes).
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Operand wordOffset = context.ShiftRightU32(baseOffset, Const(2));
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Operand bitOffset = GetBitOffset(context, baseOffset);
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for (int index = 0; index < count; index++)
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{
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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if (rd.IsRZ)
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{
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break;
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}
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Operand offset = context.IAdd(wordOffset, Const(index));
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Operand value = null;
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switch (region)
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{
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case MemoryRegion.Local: value = context.LoadLocal (offset); break;
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case MemoryRegion.Shared: value = context.LoadShared(offset); break;
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}
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if (isSmallInt)
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{
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value = ExtractSmallInt(context, op.Size, bitOffset, value);
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}
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context.Copy(Register(rd), value);
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}
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}
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private static void EmitLoadGlobal(EmitterContext context)
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{
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OpCodeMemory op = (OpCodeMemory)context.CurrOp;
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bool isSmallInt = op.Size < IntegerSize.B32;
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int count = GetVectorCount(op.Size);
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, op.Ra, op.Extended, op.Offset);
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Operand bitOffset = GetBitOffset(context, addrLow);
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for (int index = 0; index < count; index++)
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{
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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if (rd.IsRZ)
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{
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break;
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}
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Operand value = context.LoadGlobal(context.IAdd(addrLow, Const(index * 4)), addrHigh);
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if (isSmallInt)
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{
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value = ExtractSmallInt(context, op.Size, bitOffset, value);
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}
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context.Copy(Register(rd), value);
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}
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}
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private static void EmitStore(EmitterContext context, MemoryRegion region)
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{
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OpCodeMemory op = (OpCodeMemory)context.CurrOp;
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if (op.Size > IntegerSize.B128)
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{
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context.Config.GpuAccessor.Log($"Invalid store size: {op.Size}.");
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}
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bool isSmallInt = op.Size < IntegerSize.B32;
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int count = 1;
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switch (op.Size)
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{
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case IntegerSize.B64: count = 2; break;
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case IntegerSize.B128: count = 4; break;
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}
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Operand baseOffset = context.IAdd(GetSrcA(context), Const(op.Offset));
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Operand wordOffset = context.ShiftRightU32(baseOffset, Const(2));
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Operand bitOffset = GetBitOffset(context, baseOffset);
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for (int index = 0; index < count; index++)
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{
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bool isRz = op.Rd.IsRZ;
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Register rd = new Register(isRz ? op.Rd.Index : op.Rd.Index + index, RegisterType.Gpr);
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Operand value = Register(rd);
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Operand offset = context.IAdd(wordOffset, Const(index));
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if (isSmallInt)
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{
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Operand word = null;
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switch (region)
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{
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case MemoryRegion.Local: word = context.LoadLocal (offset); break;
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case MemoryRegion.Shared: word = context.LoadShared(offset); break;
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}
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value = InsertSmallInt(context, op.Size, bitOffset, word, value);
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}
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switch (region)
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{
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case MemoryRegion.Local: context.StoreLocal (offset, value); break;
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case MemoryRegion.Shared: context.StoreShared(offset, value); break;
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}
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}
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}
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private static void EmitStoreGlobal(EmitterContext context)
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{
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OpCodeMemory op = (OpCodeMemory)context.CurrOp;
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bool isSmallInt = op.Size < IntegerSize.B32;
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int count = GetVectorCount(op.Size);
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, op.Ra, op.Extended, op.Offset);
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Operand bitOffset = GetBitOffset(context, addrLow);
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for (int index = 0; index < count; index++)
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{
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bool isRz = op.Rd.IsRZ;
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Register rd = new Register(isRz ? op.Rd.Index : op.Rd.Index + index, RegisterType.Gpr);
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Operand value = Register(rd);
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if (isSmallInt)
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{
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Operand word = context.LoadGlobal(addrLow, addrHigh);
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value = InsertSmallInt(context, op.Size, bitOffset, word, value);
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}
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context.StoreGlobal(context.IAdd(addrLow, Const(index * 4)), addrHigh, value);
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}
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}
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private static int GetVectorCount(IntegerSize size)
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{
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switch (size)
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{
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case IntegerSize.B64:
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return 2;
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case IntegerSize.B128:
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case IntegerSize.UB128:
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return 4;
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}
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return 1;
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}
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private static (Operand, Operand) Get40BitsAddress(
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EmitterContext context,
|
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Register ra,
|
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bool extended,
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int offset)
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|
{
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Operand addrLow = GetSrcA(context);
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Operand addrHigh;
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if (extended && !ra.IsRZ)
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{
|
|
addrHigh = Register(ra.Index + 1, RegisterType.Gpr);
|
|
}
|
|
else
|
|
{
|
|
addrHigh = Const(0);
|
|
}
|
|
|
|
Operand offs = Const(offset);
|
|
|
|
addrLow = context.IAdd(addrLow, offs);
|
|
|
|
if (extended)
|
|
{
|
|
Operand carry = context.ICompareLessUnsigned(addrLow, offs);
|
|
|
|
addrHigh = context.IAdd(addrHigh, context.ConditionalSelect(carry, Const(1), Const(0)));
|
|
}
|
|
|
|
return (addrLow, addrHigh);
|
|
}
|
|
|
|
private static Operand GetBitOffset(EmitterContext context, Operand baseOffset)
|
|
{
|
|
// Note: bit offset = (baseOffset & 0b11) * 8.
|
|
// Addresses should be always aligned to the integer type,
|
|
// so we don't need to take unaligned addresses into account.
|
|
return context.ShiftLeft(context.BitwiseAnd(baseOffset, Const(3)), Const(3));
|
|
}
|
|
|
|
private static Operand ExtractSmallInt(
|
|
EmitterContext context,
|
|
IntegerSize size,
|
|
Operand bitOffset,
|
|
Operand value)
|
|
{
|
|
value = context.ShiftRightU32(value, bitOffset);
|
|
|
|
switch (size)
|
|
{
|
|
case IntegerSize.U8: value = ZeroExtendTo32(context, value, 8); break;
|
|
case IntegerSize.U16: value = ZeroExtendTo32(context, value, 16); break;
|
|
case IntegerSize.S8: value = SignExtendTo32(context, value, 8); break;
|
|
case IntegerSize.S16: value = SignExtendTo32(context, value, 16); break;
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
private static Operand InsertSmallInt(
|
|
EmitterContext context,
|
|
IntegerSize size,
|
|
Operand bitOffset,
|
|
Operand word,
|
|
Operand value)
|
|
{
|
|
switch (size)
|
|
{
|
|
case IntegerSize.U8:
|
|
case IntegerSize.S8:
|
|
value = context.BitwiseAnd(value, Const(0xff));
|
|
value = context.BitfieldInsert(word, value, bitOffset, Const(8));
|
|
break;
|
|
|
|
case IntegerSize.U16:
|
|
case IntegerSize.S16:
|
|
value = context.BitwiseAnd(value, Const(0xffff));
|
|
value = context.BitfieldInsert(word, value, bitOffset, Const(16));
|
|
break;
|
|
}
|
|
|
|
return value;
|
|
}
|
|
}
|
|
} |