forked from Mirror/Ryujinx
f5235fff29
* ARMeilleure/HardwareCapabilities: Add Sha * ARMeilleure/Intrinsic: Add X86Sha256Rnds2 * ARmeilleure: Hardware accelerate SHA256H/SHA256H2 * ARMeilleure/Intrinsic: Add X86Sha256Msg1, X86Sha256Msg2 * ARMeilleure/Intrinsic: Add X86Palignr * ARMeilleure: Hardware accelerate SHA256SU0, SHA256SU1 * PTC: Bump InternalVersion
64 lines
1.9 KiB
C#
64 lines
1.9 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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#region "Sha256"
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public static void Sha256h_V(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand d = GetVecA32(op.Qd);
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Operand n = GetVecA32(op.Qn);
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Operand m = GetVecA32(op.Qm);
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Operand res = InstEmitSimdHashHelper.EmitSha256h(context, d, n, m, part2: false);
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Sha256h2_V(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand d = GetVecA32(op.Qd);
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Operand n = GetVecA32(op.Qn);
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Operand m = GetVecA32(op.Qm);
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Operand res = InstEmitSimdHashHelper.EmitSha256h(context, n, d, m, part2: true);
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Sha256su0_V(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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Operand d = GetVecA32(op.Qd);
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Operand m = GetVecA32(op.Qm);
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Operand res = InstEmitSimdHashHelper.EmitSha256su0(context, d, m);
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Sha256su1_V(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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Operand d = GetVecA32(op.Qd);
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Operand n = GetVecA32(op.Qn);
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Operand m = GetVecA32(op.Qm);
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Operand res = InstEmitSimdHashHelper.EmitSha256su1(context, d, n, m);
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context.Copy(GetVecA32(op.Qd), res);
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}
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#endregion
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}
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}
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