forked from Mirror/Ryujinx
33 lines
1.4 KiB
C#
33 lines
1.4 KiB
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32Simd : OpCode32SimdBase
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{
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public int Opc { get; protected set; }
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public bool Q { get; protected set; }
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public bool F { get; protected set; }
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public bool U { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, false);
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public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, true);
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public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
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{
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Size = (opCode >> 20) & 0x3;
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Q = ((opCode >> 6) & 0x1) != 0;
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F = ((opCode >> 10) & 0x1) != 0;
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U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
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Opc = (opCode >> 7) & 0x3;
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RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
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Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
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Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
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// Subclasses have their own handling of Vx to account for before checking.
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if (GetType() == typeof(OpCode32Simd) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm))
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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