forked from Mirror/Ryujinx
814f75142e
* Implemented in IR the managed methods of the Saturating region ... ... of the SoftFallback class (the SatQ ones). The need to natively manage the Fpcr and Fpsr system registers is still a fact. Contributes to https://github.com/Ryujinx/Ryujinx/issues/2917 ; I will open another PR to implement in Intrinsics-branchless the methods of the Saturation region as well (the SatXXXToXXX ones). All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq. * Ptc.InternalVersion = 3665 * Addressed PR feedback. * Implemented in IR the managed methods of the ShlReg region of the SoftFallback class. It also includes the last two SatQ ones (following up on https://github.com/Ryujinx/Ryujinx/pull/3665). All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq. * Fpsr and Fpcr freed. Handling/isolation of Fpsr and Fpcr via register for IR and via memory for Tests and Threads, with synchronization to context exchanges (explicit for SoftFloat); without having to call managed methods. Thanks to the inlining work of the previous two PRs and others in this. Tests performed locally in both release and debug modes, in both lowcq and highcq, with FastFP to true and false (explicit FP tests included). Tested with the title Tony Hawk's PS. Depends on shlreg. * Update InstEmitSimdHelper.cs * De-magic Masks. Remove the Stride and Len flags; Fpsr.NZCV are A32 only, then moved to Fpscr: this leads to emitting less IR in reference to Get/Set Fpsr/Fpcr/Fpscr methods in reference to Mrs/Msr (A64) and Vmrs/Vmsr (A32) instructions. * Addressed PR feedback.
391 lines
13 KiB
C#
391 lines
13 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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using Func2I = Func<Operand, Operand, Operand>;
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static partial class InstEmit32
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{
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public static void Vceq_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.Equal, false);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareEQFpscr), false);
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}
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}
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public static void Vceq_I(ArmEmitterContext context)
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{
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EmitCmpOpI32(context, context.ICompareEqual, context.ICompareEqual, false, false);
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}
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public static void Vceq_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.Equal, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareEQFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareEqual, context.ICompareEqual, true, false);
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}
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}
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public static void Vcge_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThanOrEqual, false);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGEFpscr), false);
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}
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}
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public static void Vcge_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitCmpOpI32(context, context.ICompareGreaterOrEqual, context.ICompareGreaterOrEqualUI, false, !op.U);
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}
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public static void Vcge_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThanOrEqual, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGEFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareGreaterOrEqual, context.ICompareGreaterOrEqualUI, true, true);
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}
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}
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public static void Vcgt_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThan, false);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGTFpscr), false);
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}
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}
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public static void Vcgt_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitCmpOpI32(context, context.ICompareGreater, context.ICompareGreaterUI, false, !op.U);
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}
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public static void Vcgt_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseAvx)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.GreaterThan, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareGTFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareGreater, context.ICompareGreaterUI, true, true);
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}
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}
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public static void Vcle_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.LessThanOrEqual, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareLEFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareLessOrEqual, context.ICompareLessOrEqualUI, true, true);
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}
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}
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public static void Vclt_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2OrAvxCmpOpF32(context, CmpCondition.LessThan, true);
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}
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else
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{
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EmitCmpOpF32(context, nameof(SoftFloat32.FPCompareLTFpscr), true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareLess, context.ICompareLessUI, true, true);
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}
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}
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private static void EmitCmpOpF32(ArmEmitterContext context, string name, bool zero)
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{
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if (zero)
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{
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EmitVectorUnaryOpF32(context, (m) =>
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{
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Operand zeroOp = m.Type == OperandType.FP64 ? ConstF(0.0d) : ConstF(0.0f);
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return EmitSoftFloatCallDefaultFpscr(context, name, m, zeroOp);
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});
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}
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else
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{
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EmitVectorBinaryOpF32(context, (n, m) =>
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{
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return EmitSoftFloatCallDefaultFpscr(context, name, n, m);
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});
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}
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}
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private static Operand ZerosOrOnes(ArmEmitterContext context, Operand fromBool, OperandType baseType)
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{
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var ones = (baseType == OperandType.I64) ? Const(-1L) : Const(-1);
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return context.ConditionalSelect(fromBool, ones, Const(baseType, 0L));
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}
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private static void EmitCmpOpI32(
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ArmEmitterContext context,
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Func2I signedOp,
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Func2I unsignedOp,
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bool zero,
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bool signed)
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{
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if (zero)
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{
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if (signed)
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{
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EmitVectorUnaryOpSx32(context, (m) =>
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{
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OperandType type = m.Type;
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Operand zeroV = (type == OperandType.I64) ? Const(0L) : Const(0);
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return ZerosOrOnes(context, signedOp(m, zeroV), type);
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});
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}
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else
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{
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EmitVectorUnaryOpZx32(context, (m) =>
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{
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OperandType type = m.Type;
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Operand zeroV = (type == OperandType.I64) ? Const(0L) : Const(0);
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return ZerosOrOnes(context, unsignedOp(m, zeroV), type);
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});
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}
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}
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else
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{
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if (signed)
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{
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EmitVectorBinaryOpSx32(context, (n, m) => ZerosOrOnes(context, signedOp(n, m), n.Type));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (n, m) => ZerosOrOnes(context, unsignedOp(n, m), n.Type));
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}
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}
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}
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public static void Vcmp(ArmEmitterContext context)
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{
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EmitVcmpOrVcmpe(context, false);
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}
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public static void Vcmpe(ArmEmitterContext context)
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{
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EmitVcmpOrVcmpe(context, true);
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}
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private static void EmitVcmpOrVcmpe(ArmEmitterContext context, bool signalNaNs)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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bool cmpWithZero = (op.Opc & 2) != 0;
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2))
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{
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CmpCondition cmpOrdered = signalNaNs ? CmpCondition.OrderedS : CmpCondition.OrderedQ;
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bool doubleSize = sizeF != 0;
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int shift = doubleSize ? 1 : 2;
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Operand m = GetVecA32(op.Vm >> shift);
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Operand n = GetVecA32(op.Vd >> shift);
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n = EmitSwapScalar(context, n, op.Vd, doubleSize);
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m = cmpWithZero ? context.VectorZero() : EmitSwapScalar(context, m, op.Vm, doubleSize);
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Operand lblNaN = Label();
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Operand lblEnd = Label();
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if (!doubleSize)
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpss, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comissge, n, m);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, n, m);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, n, m);
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SetFpFlag(context, FPState.VFlag, Const(0));
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SetFpFlag(context, FPState.CFlag, cf);
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SetFpFlag(context, FPState.ZFlag, zf);
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SetFpFlag(context, FPState.NFlag, nf);
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}
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else
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comisdge, n, m);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, n, m);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, n, m);
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SetFpFlag(context, FPState.VFlag, Const(0));
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SetFpFlag(context, FPState.CFlag, cf);
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SetFpFlag(context, FPState.ZFlag, zf);
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SetFpFlag(context, FPState.NFlag, nf);
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}
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context.Branch(lblEnd);
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context.MarkLabel(lblNaN);
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SetFpFlag(context, FPState.VFlag, Const(1));
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SetFpFlag(context, FPState.CFlag, Const(1));
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SetFpFlag(context, FPState.ZFlag, Const(0));
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SetFpFlag(context, FPState.NFlag, Const(0));
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context.MarkLabel(lblEnd);
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}
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else
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{
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand ne = ExtractScalar(context, type, op.Vd);
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Operand me;
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if (cmpWithZero)
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{
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me = sizeF == 0 ? ConstF(0f) : ConstF(0d);
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}
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else
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{
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me = ExtractScalar(context, type, op.Vm);
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}
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Operand nzcv = EmitSoftFloatCall(context, nameof(SoftFloat32.FPCompare), ne, me, Const(signalNaNs));
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EmitSetFpscrNzcv(context, nzcv);
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}
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}
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private static void EmitSetFpscrNzcv(ArmEmitterContext context, Operand nzcv)
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{
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Operand Extract(Operand value, int bit)
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{
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if (bit != 0)
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{
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value = context.ShiftRightUI(value, Const(bit));
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}
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value = context.BitwiseAnd(value, Const(1));
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return value;
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}
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SetFpFlag(context, FPState.VFlag, Extract(nzcv, 0));
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SetFpFlag(context, FPState.CFlag, Extract(nzcv, 1));
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SetFpFlag(context, FPState.ZFlag, Extract(nzcv, 2));
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SetFpFlag(context, FPState.NFlag, Extract(nzcv, 3));
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}
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private static void EmitSse2OrAvxCmpOpF32(ArmEmitterContext context, CmpCondition cond, bool zero)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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int sizeF = op.Size & 1;
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Intrinsic inst = (sizeF == 0) ? Intrinsic.X86Cmpps : Intrinsic.X86Cmppd;
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if (zero)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(inst, m, context.VectorZero(), Const((int)cond));
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});
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}
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else
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{
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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return context.AddIntrinsic(inst, n, m, Const((int)cond));
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});
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}
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}
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}
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}
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