forked from Mirror/Ryujinx
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
1307 lines
36 KiB
C#
1307 lines
36 KiB
C#
using ARMeilleure.State;
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using System;
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namespace ARMeilleure.Instructions
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{
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static class SoftFallback
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{
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#region "ShlReg"
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public static long SignedShlReg(long value, long shift, bool round, int size)
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{
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int eSize = 8 << size;
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int shiftLsB = (sbyte)shift;
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if (shiftLsB < 0)
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{
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return SignedShrReg(value, -shiftLsB, round, eSize);
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}
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else if (shiftLsB > 0)
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{
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if (shiftLsB >= eSize)
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{
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return 0L;
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}
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return value << shiftLsB;
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}
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else /* if (shiftLsB == 0) */
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{
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return value;
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}
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}
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public static ulong UnsignedShlReg(ulong value, ulong shift, bool round, int size)
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{
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int eSize = 8 << size;
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int shiftLsB = (sbyte)shift;
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if (shiftLsB < 0)
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{
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return UnsignedShrReg(value, -shiftLsB, round, eSize);
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}
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else if (shiftLsB > 0)
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{
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if (shiftLsB >= eSize)
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{
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return 0UL;
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}
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return value << shiftLsB;
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}
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else /* if (shiftLsB == 0) */
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{
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return value;
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}
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}
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public static long SignedShlRegSatQ(long value, long shift, bool round, int size)
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{
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ExecutionContext context = NativeInterface.GetContext();
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int eSize = 8 << size;
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int shiftLsB = (sbyte)shift;
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if (shiftLsB < 0)
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{
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return SignedShrReg(value, -shiftLsB, round, eSize);
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}
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else if (shiftLsB > 0)
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{
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if (shiftLsB >= eSize)
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{
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return SignedSignSatQ(value, eSize, context);
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}
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if (eSize == 64)
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{
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long shl = value << shiftLsB;
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long shr = shl >> shiftLsB;
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if (shr != value)
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{
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return SignedSignSatQ(value, eSize, context);
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}
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else /* if (shr == value) */
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{
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return shl;
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}
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}
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else /* if (eSize != 64) */
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{
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return SignedSrcSignedDstSatQ(value << shiftLsB, size);
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}
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}
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else /* if (shiftLsB == 0) */
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{
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return value;
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}
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}
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public static ulong UnsignedShlRegSatQ(ulong value, ulong shift, bool round, int size)
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{
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ExecutionContext context = NativeInterface.GetContext();
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int eSize = 8 << size;
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int shiftLsB = (sbyte)shift;
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if (shiftLsB < 0)
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{
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return UnsignedShrReg(value, -shiftLsB, round, eSize);
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}
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else if (shiftLsB > 0)
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{
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if (shiftLsB >= eSize)
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{
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return UnsignedSignSatQ(value, eSize, context);
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}
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if (eSize == 64)
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{
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ulong shl = value << shiftLsB;
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ulong shr = shl >> shiftLsB;
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if (shr != value)
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{
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return UnsignedSignSatQ(value, eSize, context);
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}
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else /* if (shr == value) */
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{
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return shl;
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}
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}
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else /* if (eSize != 64) */
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{
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return UnsignedSrcUnsignedDstSatQ(value << shiftLsB, size);
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}
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}
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else /* if (shiftLsB == 0) */
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{
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return value;
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}
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}
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private static long SignedShrReg(long value, int shift, bool round, int eSize) // shift := [1, 128]; eSize := {8, 16, 32, 64}.
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{
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if (round)
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{
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if (shift >= eSize)
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{
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return 0L;
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}
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long roundConst = 1L << (shift - 1);
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long add = value + roundConst;
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if (eSize == 64)
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{
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if ((~value & (value ^ add)) < 0L)
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{
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return (long)((ulong)add >> shift);
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}
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else
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{
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return add >> shift;
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}
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}
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else /* if (eSize != 64) */
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{
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return add >> shift;
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}
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}
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else /* if (!round) */
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{
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if (shift >= eSize)
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{
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if (value < 0L)
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{
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return -1L;
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}
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else /* if (value >= 0L) */
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{
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return 0L;
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}
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}
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return value >> shift;
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}
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}
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private static ulong UnsignedShrReg(ulong value, int shift, bool round, int eSize) // shift := [1, 128]; eSize := {8, 16, 32, 64}.
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{
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if (round)
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{
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if (shift > 64)
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{
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return 0UL;
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}
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ulong roundConst = 1UL << (shift - 1);
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ulong add = value + roundConst;
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if (eSize == 64)
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{
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if ((add < value) && (add < roundConst))
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{
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if (shift == 64)
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{
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return 1UL;
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}
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return (add >> shift) | (0x8000000000000000UL >> (shift - 1));
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}
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else
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{
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if (shift == 64)
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{
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return 0UL;
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}
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return add >> shift;
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}
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}
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else /* if (eSize != 64) */
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{
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if (shift == 64)
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{
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return 0UL;
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}
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return add >> shift;
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}
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}
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else /* if (!round) */
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{
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if (shift >= eSize)
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{
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return 0UL;
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}
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return value >> shift;
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}
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}
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private static long SignedSignSatQ(long op, int eSize, ExecutionContext context) // eSize := {8, 16, 32, 64}.
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{
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long tMaxValue = (1L << (eSize - 1)) - 1L;
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long tMinValue = -(1L << (eSize - 1));
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if (op > 0L)
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{
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context.Fpsr |= FPSR.Qc;
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return tMaxValue;
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}
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else if (op < 0L)
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{
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context.Fpsr |= FPSR.Qc;
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return tMinValue;
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}
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else
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{
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return 0L;
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}
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}
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private static ulong UnsignedSignSatQ(ulong op, int eSize, ExecutionContext context) // eSize := {8, 16, 32, 64}.
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{
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ulong tMaxValue = ulong.MaxValue >> (64 - eSize);
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if (op > 0UL)
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{
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context.Fpsr |= FPSR.Qc;
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return tMaxValue;
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}
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else
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{
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return 0UL;
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}
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}
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#endregion
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#region "ShrImm64"
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public static long SignedShrImm64(long value, long roundConst, int shift)
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{
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if (roundConst == 0L)
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{
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if (shift <= 63)
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{
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return value >> shift;
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}
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else /* if (shift == 64) */
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{
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if (value < 0L)
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{
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return -1L;
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}
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else /* if (value >= 0L) */
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{
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return 0L;
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}
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}
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}
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else /* if (roundConst == 1L << (shift - 1)) */
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{
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if (shift <= 63)
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{
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long add = value + roundConst;
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if ((~value & (value ^ add)) < 0L)
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{
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return (long)((ulong)add >> shift);
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}
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else
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{
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return add >> shift;
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}
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}
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else /* if (shift == 64) */
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{
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return 0L;
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}
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}
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}
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public static ulong UnsignedShrImm64(ulong value, long roundConst, int shift)
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{
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if (roundConst == 0L)
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{
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if (shift <= 63)
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{
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return value >> shift;
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}
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else /* if (shift == 64) */
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{
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return 0UL;
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}
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}
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else /* if (roundConst == 1L << (shift - 1)) */
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{
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ulong add = value + (ulong)roundConst;
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if ((add < value) && (add < (ulong)roundConst))
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{
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if (shift <= 63)
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{
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return (add >> shift) | (0x8000000000000000UL >> (shift - 1));
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}
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else /* if (shift == 64) */
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{
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return 1UL;
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}
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}
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else
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{
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if (shift <= 63)
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{
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return add >> shift;
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}
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else /* if (shift == 64) */
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{
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return 0UL;
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}
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}
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}
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}
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#endregion
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#region "Rounding"
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public static double Round(double value)
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{
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ExecutionContext context = NativeInterface.GetContext();
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FPRoundingMode roundMode = context.Fpcr.GetRoundingMode();
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if (roundMode == FPRoundingMode.ToNearest)
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{
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return Math.Round(value); // even
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}
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else if (roundMode == FPRoundingMode.TowardsPlusInfinity)
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{
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return Math.Ceiling(value);
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}
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else if (roundMode == FPRoundingMode.TowardsMinusInfinity)
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{
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return Math.Floor(value);
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}
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else /* if (roundMode == FPRoundingMode.TowardsZero) */
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{
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return Math.Truncate(value);
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}
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}
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public static float RoundF(float value)
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{
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ExecutionContext context = NativeInterface.GetContext();
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FPRoundingMode roundMode = context.Fpcr.GetRoundingMode();
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if (roundMode == FPRoundingMode.ToNearest)
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{
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return MathF.Round(value); // even
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}
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else if (roundMode == FPRoundingMode.TowardsPlusInfinity)
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{
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return MathF.Ceiling(value);
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}
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else if (roundMode == FPRoundingMode.TowardsMinusInfinity)
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{
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return MathF.Floor(value);
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}
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else /* if (roundMode == FPRoundingMode.TowardsZero) */
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{
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return MathF.Truncate(value);
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}
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}
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#endregion
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#region "Saturation"
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public static int SatF32ToS32(float value)
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{
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if (float.IsNaN(value)) return 0;
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return value >= int.MaxValue ? int.MaxValue :
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value <= int.MinValue ? int.MinValue : (int)value;
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}
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public static long SatF32ToS64(float value)
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{
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if (float.IsNaN(value)) return 0;
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return value >= long.MaxValue ? long.MaxValue :
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value <= long.MinValue ? long.MinValue : (long)value;
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}
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public static uint SatF32ToU32(float value)
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{
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if (float.IsNaN(value)) return 0;
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return value >= uint.MaxValue ? uint.MaxValue :
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value <= uint.MinValue ? uint.MinValue : (uint)value;
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}
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public static ulong SatF32ToU64(float value)
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{
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if (float.IsNaN(value)) return 0;
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return value >= ulong.MaxValue ? ulong.MaxValue :
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value <= ulong.MinValue ? ulong.MinValue : (ulong)value;
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}
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public static int SatF64ToS32(double value)
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{
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if (double.IsNaN(value)) return 0;
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return value >= int.MaxValue ? int.MaxValue :
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value <= int.MinValue ? int.MinValue : (int)value;
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}
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public static long SatF64ToS64(double value)
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{
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if (double.IsNaN(value)) return 0;
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return value >= long.MaxValue ? long.MaxValue :
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value <= long.MinValue ? long.MinValue : (long)value;
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}
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public static uint SatF64ToU32(double value)
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{
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if (double.IsNaN(value)) return 0;
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return value >= uint.MaxValue ? uint.MaxValue :
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value <= uint.MinValue ? uint.MinValue : (uint)value;
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}
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public static ulong SatF64ToU64(double value)
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{
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if (double.IsNaN(value)) return 0;
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return value >= ulong.MaxValue ? ulong.MaxValue :
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value <= ulong.MinValue ? ulong.MinValue : (ulong)value;
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}
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#endregion
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#region "Saturating"
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public static long SignedSrcSignedDstSatQ(long op, int size)
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{
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ExecutionContext context = NativeInterface.GetContext();
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int eSize = 8 << size;
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long tMaxValue = (1L << (eSize - 1)) - 1L;
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long tMinValue = -(1L << (eSize - 1));
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if (op > tMaxValue)
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{
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context.Fpsr |= FPSR.Qc;
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return tMaxValue;
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}
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else if (op < tMinValue)
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{
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context.Fpsr |= FPSR.Qc;
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return tMinValue;
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}
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else
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{
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return op;
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}
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}
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public static ulong SignedSrcUnsignedDstSatQ(long op, int size)
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{
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ExecutionContext context = NativeInterface.GetContext();
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int eSize = 8 << size;
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ulong tMaxValue = (1UL << eSize) - 1UL;
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ulong tMinValue = 0UL;
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if (op > (long)tMaxValue)
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{
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context.Fpsr |= FPSR.Qc;
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return tMaxValue;
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}
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else if (op < (long)tMinValue)
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{
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context.Fpsr |= FPSR.Qc;
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return tMinValue;
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}
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else
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{
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return (ulong)op;
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}
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}
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public static long UnsignedSrcSignedDstSatQ(ulong op, int size)
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{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
int eSize = 8 << size;
|
|
|
|
long tMaxValue = (1L << (eSize - 1)) - 1L;
|
|
|
|
if (op > (ulong)tMaxValue)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return tMaxValue;
|
|
}
|
|
else
|
|
{
|
|
return (long)op;
|
|
}
|
|
}
|
|
|
|
public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int size)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
int eSize = 8 << size;
|
|
|
|
ulong tMaxValue = (1UL << eSize) - 1UL;
|
|
|
|
if (op > tMaxValue)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return tMaxValue;
|
|
}
|
|
else
|
|
{
|
|
return op;
|
|
}
|
|
}
|
|
|
|
public static long UnarySignedSatQAbsOrNeg(long op)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
if (op == long.MinValue)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return long.MaxValue;
|
|
}
|
|
else
|
|
{
|
|
return op;
|
|
}
|
|
}
|
|
|
|
public static long BinarySignedSatQAdd(long op1, long op2)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
long add = op1 + op2;
|
|
|
|
if ((~(op1 ^ op2) & (op1 ^ add)) < 0L)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
if (op1 < 0L)
|
|
{
|
|
return long.MinValue;
|
|
}
|
|
else
|
|
{
|
|
return long.MaxValue;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return add;
|
|
}
|
|
}
|
|
|
|
public static ulong BinaryUnsignedSatQAdd(ulong op1, ulong op2)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
ulong add = op1 + op2;
|
|
|
|
if ((add < op1) && (add < op2))
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return ulong.MaxValue;
|
|
}
|
|
else
|
|
{
|
|
return add;
|
|
}
|
|
}
|
|
|
|
public static long BinarySignedSatQSub(long op1, long op2)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
long sub = op1 - op2;
|
|
|
|
if (((op1 ^ op2) & (op1 ^ sub)) < 0L)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
if (op1 < 0L)
|
|
{
|
|
return long.MinValue;
|
|
}
|
|
else
|
|
{
|
|
return long.MaxValue;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return sub;
|
|
}
|
|
}
|
|
|
|
public static ulong BinaryUnsignedSatQSub(ulong op1, ulong op2)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
ulong sub = op1 - op2;
|
|
|
|
if (op1 < op2)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return ulong.MinValue;
|
|
}
|
|
else
|
|
{
|
|
return sub;
|
|
}
|
|
}
|
|
|
|
public static long BinarySignedSatQAcc(ulong op1, long op2)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
if (op1 <= (ulong)long.MaxValue)
|
|
{
|
|
// op1 from ulong.MinValue to (ulong)long.MaxValue
|
|
// op2 from long.MinValue to long.MaxValue
|
|
|
|
long add = (long)op1 + op2;
|
|
|
|
if ((~op2 & add) < 0L)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return long.MaxValue;
|
|
}
|
|
else
|
|
{
|
|
return add;
|
|
}
|
|
}
|
|
else if (op2 >= 0L)
|
|
{
|
|
// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
|
|
// op2 from (long)ulong.MinValue to long.MaxValue
|
|
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return long.MaxValue;
|
|
}
|
|
else
|
|
{
|
|
// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
|
|
// op2 from long.MinValue to (long)ulong.MinValue - 1L
|
|
|
|
ulong add = op1 + (ulong)op2;
|
|
|
|
if (add > (ulong)long.MaxValue)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return long.MaxValue;
|
|
}
|
|
else
|
|
{
|
|
return (long)add;
|
|
}
|
|
}
|
|
}
|
|
|
|
public static ulong BinaryUnsignedSatQAcc(long op1, ulong op2)
|
|
{
|
|
ExecutionContext context = NativeInterface.GetContext();
|
|
|
|
if (op1 >= 0L)
|
|
{
|
|
// op1 from (long)ulong.MinValue to long.MaxValue
|
|
// op2 from ulong.MinValue to ulong.MaxValue
|
|
|
|
ulong add = (ulong)op1 + op2;
|
|
|
|
if ((add < (ulong)op1) && (add < op2))
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return ulong.MaxValue;
|
|
}
|
|
else
|
|
{
|
|
return add;
|
|
}
|
|
}
|
|
else if (op2 > (ulong)long.MaxValue)
|
|
{
|
|
// op1 from long.MinValue to (long)ulong.MinValue - 1L
|
|
// op2 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
|
|
|
|
return (ulong)op1 + op2;
|
|
}
|
|
else
|
|
{
|
|
// op1 from long.MinValue to (long)ulong.MinValue - 1L
|
|
// op2 from ulong.MinValue to (ulong)long.MaxValue
|
|
|
|
long add = op1 + (long)op2;
|
|
|
|
if (add < (long)ulong.MinValue)
|
|
{
|
|
context.Fpsr |= FPSR.Qc;
|
|
|
|
return ulong.MinValue;
|
|
}
|
|
else
|
|
{
|
|
return (ulong)add;
|
|
}
|
|
}
|
|
}
|
|
#endregion
|
|
|
|
#region "Count"
|
|
public static ulong CountLeadingSigns(ulong value, int size) // size is 8, 16, 32 or 64 (SIMD&FP or Base Inst.).
|
|
{
|
|
value ^= value >> 1;
|
|
|
|
int highBit = size - 2;
|
|
|
|
for (int bit = highBit; bit >= 0; bit--)
|
|
{
|
|
if (((int)(value >> bit) & 0b1) != 0)
|
|
{
|
|
return (ulong)(highBit - bit);
|
|
}
|
|
}
|
|
|
|
return (ulong)(size - 1);
|
|
}
|
|
|
|
private static readonly byte[] ClzNibbleTbl = { 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
|
|
public static ulong CountLeadingZeros(ulong value, int size) // size is 8, 16, 32 or 64 (SIMD&FP or Base Inst.).
|
|
{
|
|
if (value == 0ul)
|
|
{
|
|
return (ulong)size;
|
|
}
|
|
|
|
int nibbleIdx = size;
|
|
int preCount, count = 0;
|
|
|
|
do
|
|
{
|
|
nibbleIdx -= 4;
|
|
preCount = ClzNibbleTbl[(int)(value >> nibbleIdx) & 0b1111];
|
|
count += preCount;
|
|
}
|
|
while (preCount == 4);
|
|
|
|
return (ulong)count;
|
|
}
|
|
|
|
public static ulong CountSetBits8(ulong value) // "size" is 8 (SIMD&FP Inst.).
|
|
{
|
|
value = ((value >> 1) & 0x55ul) + (value & 0x55ul);
|
|
value = ((value >> 2) & 0x33ul) + (value & 0x33ul);
|
|
|
|
return (value >> 4) + (value & 0x0ful);
|
|
}
|
|
#endregion
|
|
|
|
#region "Table"
|
|
public static V128 Tbl1_V64(V128 vector, V128 tb0)
|
|
{
|
|
return Tbl(vector, 8, tb0);
|
|
}
|
|
|
|
public static V128 Tbl1_V128(V128 vector, V128 tb0)
|
|
{
|
|
return Tbl(vector, 16, tb0);
|
|
}
|
|
|
|
public static V128 Tbl2_V64(V128 vector, V128 tb0, V128 tb1)
|
|
{
|
|
return Tbl(vector, 8, tb0, tb1);
|
|
}
|
|
|
|
public static V128 Tbl2_V128(V128 vector, V128 tb0, V128 tb1)
|
|
{
|
|
return Tbl(vector, 16, tb0, tb1);
|
|
}
|
|
|
|
public static V128 Tbl3_V64(V128 vector, V128 tb0, V128 tb1, V128 tb2)
|
|
{
|
|
return Tbl(vector, 8, tb0, tb1, tb2);
|
|
}
|
|
|
|
public static V128 Tbl3_V128(V128 vector, V128 tb0, V128 tb1, V128 tb2)
|
|
{
|
|
return Tbl(vector, 16, tb0, tb1, tb2);
|
|
}
|
|
|
|
public static V128 Tbl4_V64(V128 vector, V128 tb0, V128 tb1, V128 tb2, V128 tb3)
|
|
{
|
|
return Tbl(vector, 8, tb0, tb1, tb2, tb3);
|
|
}
|
|
|
|
public static V128 Tbl4_V128(V128 vector, V128 tb0, V128 tb1, V128 tb2, V128 tb3)
|
|
{
|
|
return Tbl(vector, 16, tb0, tb1, tb2, tb3);
|
|
}
|
|
|
|
private static V128 Tbl(V128 vector, int bytes, params V128[] tb)
|
|
{
|
|
byte[] res = new byte[16];
|
|
byte[] table = new byte[tb.Length * 16];
|
|
|
|
for (byte index = 0; index < tb.Length; index++)
|
|
{
|
|
Buffer.BlockCopy(tb[index].ToArray(), 0, table, index * 16, 16);
|
|
}
|
|
|
|
byte[] v = vector.ToArray();
|
|
|
|
for (byte index = 0; index < bytes; index++)
|
|
{
|
|
byte tblIndex = v[index];
|
|
|
|
if (tblIndex < table.Length)
|
|
{
|
|
res[index] = table[tblIndex];
|
|
}
|
|
}
|
|
|
|
return new V128(res);
|
|
}
|
|
#endregion
|
|
|
|
#region "Crc32"
|
|
private const uint Crc32RevPoly = 0xedb88320;
|
|
private const uint Crc32cRevPoly = 0x82f63b78;
|
|
|
|
public static uint Crc32b(uint crc, byte value) => Crc32 (crc, Crc32RevPoly, value);
|
|
public static uint Crc32h(uint crc, ushort value) => Crc32h(crc, Crc32RevPoly, value);
|
|
public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value);
|
|
public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value);
|
|
|
|
public static uint Crc32cb(uint crc, byte value) => Crc32 (crc, Crc32cRevPoly, value);
|
|
public static uint Crc32ch(uint crc, ushort value) => Crc32h(crc, Crc32cRevPoly, value);
|
|
public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value);
|
|
public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value);
|
|
|
|
private static uint Crc32h(uint crc, uint poly, ushort val)
|
|
{
|
|
crc = Crc32(crc, poly, (byte)(val >> 0));
|
|
crc = Crc32(crc, poly, (byte)(val >> 8));
|
|
|
|
return crc;
|
|
}
|
|
|
|
private static uint Crc32w(uint crc, uint poly, uint val)
|
|
{
|
|
crc = Crc32(crc, poly, (byte)(val >> 0));
|
|
crc = Crc32(crc, poly, (byte)(val >> 8));
|
|
crc = Crc32(crc, poly, (byte)(val >> 16));
|
|
crc = Crc32(crc, poly, (byte)(val >> 24));
|
|
|
|
return crc;
|
|
}
|
|
|
|
private static uint Crc32x(uint crc, uint poly, ulong val)
|
|
{
|
|
crc = Crc32(crc, poly, (byte)(val >> 0));
|
|
crc = Crc32(crc, poly, (byte)(val >> 8));
|
|
crc = Crc32(crc, poly, (byte)(val >> 16));
|
|
crc = Crc32(crc, poly, (byte)(val >> 24));
|
|
crc = Crc32(crc, poly, (byte)(val >> 32));
|
|
crc = Crc32(crc, poly, (byte)(val >> 40));
|
|
crc = Crc32(crc, poly, (byte)(val >> 48));
|
|
crc = Crc32(crc, poly, (byte)(val >> 56));
|
|
|
|
return crc;
|
|
}
|
|
|
|
private static uint Crc32(uint crc, uint poly, byte val)
|
|
{
|
|
crc ^= val;
|
|
|
|
for (int bit = 7; bit >= 0; bit--)
|
|
{
|
|
uint mask = (uint)(-(int)(crc & 1));
|
|
|
|
crc = (crc >> 1) ^ (poly & mask);
|
|
}
|
|
|
|
return crc;
|
|
}
|
|
#endregion
|
|
|
|
#region "Aes"
|
|
public static V128 Decrypt(V128 value, V128 roundKey)
|
|
{
|
|
return CryptoHelper.AesInvSubBytes(CryptoHelper.AesInvShiftRows(value ^ roundKey));
|
|
}
|
|
|
|
public static V128 Encrypt(V128 value, V128 roundKey)
|
|
{
|
|
return CryptoHelper.AesSubBytes(CryptoHelper.AesShiftRows(value ^ roundKey));
|
|
}
|
|
|
|
public static V128 InverseMixColumns(V128 value)
|
|
{
|
|
return CryptoHelper.AesInvMixColumns(value);
|
|
}
|
|
|
|
public static V128 MixColumns(V128 value)
|
|
{
|
|
return CryptoHelper.AesMixColumns(value);
|
|
}
|
|
#endregion
|
|
|
|
#region "Sha1"
|
|
public static V128 HashChoose(V128 hash_abcd, uint hash_e, V128 wk)
|
|
{
|
|
for (int e = 0; e <= 3; e++)
|
|
{
|
|
uint t = ShaChoose(hash_abcd.GetUInt32(1),
|
|
hash_abcd.GetUInt32(2),
|
|
hash_abcd.GetUInt32(3));
|
|
|
|
hash_e += Rol(hash_abcd.GetUInt32(0), 5) + t + wk.GetUInt32(e);
|
|
|
|
t = Rol(hash_abcd.GetUInt32(1), 30);
|
|
|
|
hash_abcd.Insert(1, t);
|
|
|
|
Rol32_160(ref hash_e, ref hash_abcd);
|
|
}
|
|
|
|
return hash_abcd;
|
|
}
|
|
|
|
public static uint FixedRotate(uint hash_e)
|
|
{
|
|
return hash_e.Rol(30);
|
|
}
|
|
|
|
public static V128 HashMajority(V128 hash_abcd, uint hash_e, V128 wk)
|
|
{
|
|
for (int e = 0; e <= 3; e++)
|
|
{
|
|
uint t = ShaMajority(hash_abcd.GetUInt32(1),
|
|
hash_abcd.GetUInt32(2),
|
|
hash_abcd.GetUInt32(3));
|
|
|
|
hash_e += Rol(hash_abcd.GetUInt32(0), 5) + t + wk.GetUInt32(e);
|
|
|
|
t = Rol(hash_abcd.GetUInt32(1), 30);
|
|
|
|
hash_abcd.Insert(1, t);
|
|
|
|
Rol32_160(ref hash_e, ref hash_abcd);
|
|
}
|
|
|
|
return hash_abcd;
|
|
}
|
|
|
|
public static V128 HashParity(V128 hash_abcd, uint hash_e, V128 wk)
|
|
{
|
|
for (int e = 0; e <= 3; e++)
|
|
{
|
|
uint t = ShaParity(hash_abcd.GetUInt32(1),
|
|
hash_abcd.GetUInt32(2),
|
|
hash_abcd.GetUInt32(3));
|
|
|
|
hash_e += Rol(hash_abcd.GetUInt32(0), 5) + t + wk.GetUInt32(e);
|
|
|
|
t = Rol(hash_abcd.GetUInt32(1), 30);
|
|
|
|
hash_abcd.Insert(1, t);
|
|
|
|
Rol32_160(ref hash_e, ref hash_abcd);
|
|
}
|
|
|
|
return hash_abcd;
|
|
}
|
|
|
|
public static V128 Sha1SchedulePart1(V128 w0_3, V128 w4_7, V128 w8_11)
|
|
{
|
|
ulong t2 = w4_7.GetUInt64(0);
|
|
ulong t1 = w0_3.GetUInt64(1);
|
|
|
|
V128 result = new V128(t1, t2);
|
|
|
|
return result ^ (w0_3 ^ w8_11);
|
|
}
|
|
|
|
public static V128 Sha1SchedulePart2(V128 tw0_3, V128 w12_15)
|
|
{
|
|
V128 t = tw0_3 ^ (w12_15 >> 32);
|
|
|
|
uint tE0 = t.GetUInt32(0);
|
|
uint tE1 = t.GetUInt32(1);
|
|
uint tE2 = t.GetUInt32(2);
|
|
uint tE3 = t.GetUInt32(3);
|
|
|
|
return new V128(tE0.Rol(1), tE1.Rol(1), tE2.Rol(1), tE3.Rol(1) ^ tE0.Rol(2));
|
|
}
|
|
|
|
private static void Rol32_160(ref uint y, ref V128 x)
|
|
{
|
|
uint xE3 = x.GetUInt32(3);
|
|
|
|
x <<= 32;
|
|
x.Insert(0, y);
|
|
|
|
y = xE3;
|
|
}
|
|
|
|
private static uint ShaChoose(uint x, uint y, uint z)
|
|
{
|
|
return ((y ^ z) & x) ^ z;
|
|
}
|
|
|
|
private static uint ShaMajority(uint x, uint y, uint z)
|
|
{
|
|
return (x & y) | ((x | y) & z);
|
|
}
|
|
|
|
private static uint ShaParity(uint x, uint y, uint z)
|
|
{
|
|
return x ^ y ^ z;
|
|
}
|
|
|
|
private static uint Rol(this uint value, int count)
|
|
{
|
|
return (value << count) | (value >> (32 - count));
|
|
}
|
|
#endregion
|
|
|
|
#region "Sha256"
|
|
public static V128 HashLower(V128 hash_abcd, V128 hash_efgh, V128 wk)
|
|
{
|
|
return Sha256Hash(hash_abcd, hash_efgh, wk, part1: true);
|
|
}
|
|
|
|
public static V128 HashUpper(V128 hash_efgh, V128 hash_abcd, V128 wk)
|
|
{
|
|
return Sha256Hash(hash_abcd, hash_efgh, wk, part1: false);
|
|
}
|
|
|
|
public static V128 Sha256SchedulePart1(V128 w0_3, V128 w4_7)
|
|
{
|
|
V128 result = new V128();
|
|
|
|
for (int e = 0; e <= 3; e++)
|
|
{
|
|
uint elt = (e <= 2 ? w0_3 : w4_7).GetUInt32(e <= 2 ? e + 1 : 0);
|
|
|
|
elt = elt.Ror(7) ^ elt.Ror(18) ^ elt.Lsr(3);
|
|
|
|
elt += w0_3.GetUInt32(e);
|
|
|
|
result.Insert(e, elt);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
public static V128 Sha256SchedulePart2(V128 w0_3, V128 w8_11, V128 w12_15)
|
|
{
|
|
V128 result = new V128();
|
|
|
|
ulong t1 = w12_15.GetUInt64(1);
|
|
|
|
for (int e = 0; e <= 1; e++)
|
|
{
|
|
uint elt = t1.ULongPart(e);
|
|
|
|
elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10);
|
|
|
|
elt += w0_3.GetUInt32(e) + w8_11.GetUInt32(e + 1);
|
|
|
|
result.Insert(e, elt);
|
|
}
|
|
|
|
t1 = result.GetUInt64(0);
|
|
|
|
for (int e = 2; e <= 3; e++)
|
|
{
|
|
uint elt = t1.ULongPart(e - 2);
|
|
|
|
elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10);
|
|
|
|
elt += w0_3.GetUInt32(e) + (e == 2 ? w8_11 : w12_15).GetUInt32(e == 2 ? 3 : 0);
|
|
|
|
result.Insert(e, elt);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
private static V128 Sha256Hash(V128 x, V128 y, V128 w, bool part1)
|
|
{
|
|
for (int e = 0; e <= 3; e++)
|
|
{
|
|
uint chs = ShaChoose(y.GetUInt32(0),
|
|
y.GetUInt32(1),
|
|
y.GetUInt32(2));
|
|
|
|
uint maj = ShaMajority(x.GetUInt32(0),
|
|
x.GetUInt32(1),
|
|
x.GetUInt32(2));
|
|
|
|
uint t1 = y.GetUInt32(3) + ShaHashSigma1(y.GetUInt32(0)) + chs + w.GetUInt32(e);
|
|
|
|
uint t2 = t1 + x.GetUInt32(3);
|
|
|
|
x.Insert(3, t2);
|
|
|
|
t2 = t1 + ShaHashSigma0(x.GetUInt32(0)) + maj;
|
|
|
|
y.Insert(3, t2);
|
|
|
|
Rol32_256(ref y, ref x);
|
|
}
|
|
|
|
return part1 ? x : y;
|
|
}
|
|
|
|
private static void Rol32_256(ref V128 y, ref V128 x)
|
|
{
|
|
uint yE3 = y.GetUInt32(3);
|
|
uint xE3 = x.GetUInt32(3);
|
|
|
|
y <<= 32;
|
|
x <<= 32;
|
|
|
|
y.Insert(0, xE3);
|
|
x.Insert(0, yE3);
|
|
}
|
|
|
|
private static uint ShaHashSigma0(uint x)
|
|
{
|
|
return x.Ror(2) ^ x.Ror(13) ^ x.Ror(22);
|
|
}
|
|
|
|
private static uint ShaHashSigma1(uint x)
|
|
{
|
|
return x.Ror(6) ^ x.Ror(11) ^ x.Ror(25);
|
|
}
|
|
|
|
private static uint Ror(this uint value, int count)
|
|
{
|
|
return (value >> count) | (value << (32 - count));
|
|
}
|
|
|
|
private static uint Lsr(this uint value, int count)
|
|
{
|
|
return value >> count;
|
|
}
|
|
|
|
private static uint ULongPart(this ulong value, int part)
|
|
{
|
|
return part == 0
|
|
? (uint)(value & 0xFFFFFFFFUL)
|
|
: (uint)(value >> 32);
|
|
}
|
|
#endregion
|
|
|
|
#region "Reverse"
|
|
public static uint ReverseBits8(uint value)
|
|
{
|
|
value = ((value & 0xaa) >> 1) | ((value & 0x55) << 1);
|
|
value = ((value & 0xcc) >> 2) | ((value & 0x33) << 2);
|
|
|
|
return (value >> 4) | ((value & 0x0f) << 4);
|
|
}
|
|
|
|
public static uint ReverseBits32(uint value)
|
|
{
|
|
value = ((value & 0xaaaaaaaa) >> 1) | ((value & 0x55555555) << 1);
|
|
value = ((value & 0xcccccccc) >> 2) | ((value & 0x33333333) << 2);
|
|
value = ((value & 0xf0f0f0f0) >> 4) | ((value & 0x0f0f0f0f) << 4);
|
|
value = ((value & 0xff00ff00) >> 8) | ((value & 0x00ff00ff) << 8);
|
|
|
|
return (value >> 16) | (value << 16);
|
|
}
|
|
|
|
public static ulong ReverseBits64(ulong value)
|
|
{
|
|
value = ((value & 0xaaaaaaaaaaaaaaaa) >> 1 ) | ((value & 0x5555555555555555) << 1 );
|
|
value = ((value & 0xcccccccccccccccc) >> 2 ) | ((value & 0x3333333333333333) << 2 );
|
|
value = ((value & 0xf0f0f0f0f0f0f0f0) >> 4 ) | ((value & 0x0f0f0f0f0f0f0f0f) << 4 );
|
|
value = ((value & 0xff00ff00ff00ff00) >> 8 ) | ((value & 0x00ff00ff00ff00ff) << 8 );
|
|
value = ((value & 0xffff0000ffff0000) >> 16) | ((value & 0x0000ffff0000ffff) << 16);
|
|
|
|
return (value >> 32) | (value << 32);
|
|
}
|
|
|
|
public static uint ReverseBytes16_32(uint value) => (uint)ReverseBytes16_64(value);
|
|
|
|
public static ulong ReverseBytes16_64(ulong value) => ReverseBytes(value, RevSize.Rev16);
|
|
public static ulong ReverseBytes32_64(ulong value) => ReverseBytes(value, RevSize.Rev32);
|
|
|
|
private enum RevSize
|
|
{
|
|
Rev16,
|
|
Rev32,
|
|
Rev64
|
|
}
|
|
|
|
private static ulong ReverseBytes(ulong value, RevSize size)
|
|
{
|
|
value = ((value & 0xff00ff00ff00ff00) >> 8) | ((value & 0x00ff00ff00ff00ff) << 8);
|
|
|
|
if (size == RevSize.Rev16)
|
|
{
|
|
return value;
|
|
}
|
|
|
|
value = ((value & 0xffff0000ffff0000) >> 16) | ((value & 0x0000ffff0000ffff) << 16);
|
|
|
|
if (size == RevSize.Rev32)
|
|
{
|
|
return value;
|
|
}
|
|
|
|
value = ((value & 0xffffffff00000000) >> 32) | ((value & 0x00000000ffffffff) << 32);
|
|
|
|
if (size == RevSize.Rev64)
|
|
{
|
|
return value;
|
|
}
|
|
|
|
throw new ArgumentException(nameof(size));
|
|
}
|
|
#endregion
|
|
}
|
|
}
|