forked from Mirror/Ryujinx
02a6fdcd13
* Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
375 lines
17 KiB
C#
375 lines
17 KiB
C#
//#define Mul
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Mul"), Ignore("Tested: second half of 2018.")]
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public sealed class CpuTestMul : CpuTest
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{
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#if Mul
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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[Test, Description("MADD <Xd>, <Xn>, <Xm>, <Xa>")]
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public void Madd_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
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{
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uint Opcode = 0x9B000000; // MADD X0, X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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AArch64.X((int)Rm, new Bits(Xm));
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AArch64.X((int)Ra, new Bits(Xa));
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Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("MADD <Wd>, <Wn>, <Wm>, <Wa>")]
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public void Madd_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa)
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{
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uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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AArch64.X((int)Ra, new Bits(Wa));
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Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("MSUB <Xd>, <Xn>, <Xm>, <Xa>")]
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public void Msub_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
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{
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uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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AArch64.X((int)Rm, new Bits(Xm));
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AArch64.X((int)Ra, new Bits(Xa));
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Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("MSUB <Wd>, <Wn>, <Wm>, <Wa>")]
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public void Msub_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa)
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{
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uint Opcode = 0x1B008000; // MSUB W0, W0, W0, W0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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AArch64.X((int)Ra, new Bits(Wa));
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Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("SMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Smaddl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
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{
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uint Opcode = 0x9B200000; // SMADDL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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AArch64.X((int)Ra, new Bits(Xa));
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Base.Smaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("UMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Umaddl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
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{
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uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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AArch64.X((int)Ra, new Bits(Xa));
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Base.Umaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("SMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Smsubl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
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{
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uint Opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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AArch64.X((int)Ra, new Bits(Xa));
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Base.Smsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("UMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
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public void Umsubl_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(3u, 31u)] uint Ra,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
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{
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uint Opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0
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Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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AArch64.X((int)Rm, new Bits(Wm));
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AArch64.X((int)Ra, new Bits(Xa));
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Base.Umsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("SMULH <Xd>, <Xn>, <Xm>")]
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public void Smulh_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm)
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{
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uint Opcode = 0x9B407C00; // SMULH X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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AArch64.X((int)Rm, new Bits(Xm));
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Base.Smulh(Op[20, 16], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("UMULH <Xd>, <Xn>, <Xm>")]
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public void Umulh_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(2u, 31u)] uint Rm,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm)
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{
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uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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AArch64.X((int)Rm, new Bits(Xm));
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Base.Umulh(Op[20, 16], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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#endif
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}
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}
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