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RyuKen/Ryujinx/Cpu
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gdkchan be1d01bf7d Shouldn't have undone this
2018-02-15 01:35:44 -03:00
..
Decoder Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
Exceptions Fixes to memory management 2018-02-09 21:13:18 -03:00
Instruction Shouldn't have undone this 2018-02-15 01:35:44 -03:00
Memory Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00
State Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Translation Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
ABitUtils.cs aloha 2018-02-04 20:08:20 -03:00
AOpCodeTable.cs Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
AOptimizations.cs Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
AThread.cs Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00
ATranslatedSub.cs aloha 2018-02-04 20:08:20 -03:00
ATranslator.cs aloha 2018-02-04 20:08:20 -03:00