forked from Mirror/Ryujinx
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
24 lines
363 B
C#
24 lines
363 B
C#
using System;
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namespace ChocolArm64.State
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{
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[Flags]
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enum PState
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{
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TBit = 5,
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EBit = 9,
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VBit = 28,
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CBit = 29,
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ZBit = 30,
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NBit = 31,
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TMask = 1 << TBit,
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EMask = 1 << EBit,
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VMask = 1 << VBit,
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CMask = 1 << CBit,
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ZMask = 1 << ZBit,
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NMask = 1 << NBit
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}
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}
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