forked from Mirror/Ryujinx
c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
44 lines
1.3 KiB
C#
44 lines
1.3 KiB
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdShImm : OpCode32Simd
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{
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public int Immediate { get; private set; }
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public int Shift { get; private set; }
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public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Immediate = (opCode >> 16) & 0x3f;
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var limm = ((opCode >> 1) & 0x40) | Immediate;
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if ((limm & 0x40) == 0b1000000)
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{
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Size = 3;
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Shift = Immediate;
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}
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else if ((limm & 0x60) == 0b0100000)
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{
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Size = 2;
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Shift = Immediate - 32;
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}
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else if ((limm & 0x70) == 0b0010000)
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{
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Size = 1;
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Shift = Immediate - 16;
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}
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else if ((limm & 0x78) == 0b0001000)
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{
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Size = 0;
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Shift = Immediate - 8;
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}
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else
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{
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Instruction = InstDescriptor.Undefined;
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}
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if (GetType() == typeof(OpCode32SimdShImm) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm))
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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