forked from Mirror/Ryujinx
68e15c1a74
* Begin work on A32 SIMD Intrinsics * More instructions, some cleanup. * Intrinsics for Move instructions (zip etc) These pass the existing tests. * Intrinsics for some of Cvt While doing this I noticed that the conversion for int/fp was incorrect in the slow path. I'll fix this in the original repo. * Intrinsics for more Arithmetic instructions. * Intrinsics for Vext * Fix VEXT Intrinsic for double words. * Use InsertPs to move scalar values. * Cleanup, fix VPADD.f32 and VMIN signed integer. * Cleanup, add SSE2 support for scalar insert. Works similarly to the IR scalar insert, but obviously this one works directly on V128. * Minor cleanup. * Enable intrinsic for FP64 to integer conversion. * Address feedback apart from splitting out intrinsic float abs Also: bad VREV encodings as undefined rather than throwing in translation. * Move float abs to helper, fix bug with cvt * Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately. * Get name of variable at compilation rather than string literal. * Use correct double sign mask.
415 lines
14 KiB
C#
415 lines
14 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper32;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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using Func2I = Func<Operand, Operand, Operand>;
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static partial class InstEmit32
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{
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public static void Vceq_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.Equal, false);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareEQFpscr, SoftFloat64.FPCompareEQFpscr, false);
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}
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}
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public static void Vceq_I(ArmEmitterContext context)
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{
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EmitCmpOpI32(context, context.ICompareEqual, context.ICompareEqual, false, false);
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}
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public static void Vceq_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.Equal, true);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareEQFpscr, SoftFloat64.FPCompareEQFpscr, true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareEqual, context.ICompareEqual, true, false);
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}
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}
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public static void Vcge_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.GreaterThanOrEqual, false);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareGEFpscr, SoftFloat64.FPCompareGEFpscr, false);
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}
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}
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public static void Vcge_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitCmpOpI32(context, context.ICompareGreaterOrEqual, context.ICompareGreaterOrEqualUI, false, !op.U);
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}
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public static void Vcge_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.GreaterThanOrEqual, true);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareGEFpscr, SoftFloat64.FPCompareGEFpscr, true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareGreaterOrEqual, context.ICompareGreaterOrEqualUI, true, true);
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}
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}
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public static void Vcgt_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.GreaterThan, false);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareGTFpscr, SoftFloat64.FPCompareGTFpscr, false);
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}
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}
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public static void Vcgt_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitCmpOpI32(context, context.ICompareGreater, context.ICompareGreaterUI, false, !op.U);
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}
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public static void Vcgt_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.GreaterThan, true);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareGTFpscr, SoftFloat64.FPCompareGTFpscr, true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareGreater, context.ICompareGreaterUI, true, true);
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}
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}
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public static void Vcle_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.LessThanOrEqual, true);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareLEFpscr, SoftFloat64.FPCompareLEFpscr, true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareLessOrEqual, context.ICompareLessOrEqualUI, true, true);
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}
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}
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public static void Vclt_Z(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitSse2CmpOpF32(context, CmpCondition.LessThan, true);
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}
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else
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{
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EmitCmpOpF32(context, SoftFloat32.FPCompareLTFpscr, SoftFloat64.FPCompareLTFpscr, true);
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}
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}
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else
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{
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EmitCmpOpI32(context, context.ICompareLess, context.ICompareLessUI, true, true);
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}
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}
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private static void EmitCmpOpF32(
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ArmEmitterContext context,
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_F32_F32_F32_Bool f32,
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_F64_F64_F64_Bool f64,
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bool zero)
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{
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Operand one = Const(1);
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if (zero)
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{
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EmitVectorUnaryOpF32(context, (m) =>
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{
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OperandType type = m.Type;
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if (type == OperandType.FP64)
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{
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return context.Call(f64, m, ConstF(0.0), one);
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}
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else
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{
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return context.Call(f32, m, ConstF(0.0f), one);
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}
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});
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}
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else
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{
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EmitVectorBinaryOpF32(context, (n, m) =>
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{
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OperandType type = n.Type;
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if (type == OperandType.FP64)
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{
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return context.Call(f64, n, m, one);
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}
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else
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{
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return context.Call(f32, n, m, one);
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}
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});
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}
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}
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private static Operand ZerosOrOnes(ArmEmitterContext context, Operand fromBool, OperandType baseType)
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{
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var ones = (baseType == OperandType.I64) ? Const(-1L) : Const(-1);
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return context.ConditionalSelect(fromBool, ones, Const(baseType, 0L));
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}
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private static void EmitCmpOpI32(
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ArmEmitterContext context,
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Func2I signedOp,
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Func2I unsignedOp,
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bool zero,
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bool signed)
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{
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if (zero)
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{
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if (signed)
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{
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EmitVectorUnaryOpSx32(context, (m) =>
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{
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OperandType type = m.Type;
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Operand zeroV = (type == OperandType.I64) ? Const(0L) : Const(0);
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return ZerosOrOnes(context, signedOp(m, zeroV), type);
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});
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}
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else
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{
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EmitVectorUnaryOpZx32(context, (m) =>
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{
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OperandType type = m.Type;
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Operand zeroV = (type == OperandType.I64) ? Const(0L) : Const(0);
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return ZerosOrOnes(context, unsignedOp(m, zeroV), type);
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});
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}
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}
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else
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{
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if (signed)
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{
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EmitVectorBinaryOpSx32(context, (n, m) => ZerosOrOnes(context, signedOp(n, m), n.Type));
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}
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else
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{
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EmitVectorBinaryOpZx32(context, (n, m) => ZerosOrOnes(context, unsignedOp(n, m), n.Type));
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}
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}
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}
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public static void Vcmp(ArmEmitterContext context)
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{
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EmitVcmpOrVcmpe(context, false);
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}
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public static void Vcmpe(ArmEmitterContext context)
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{
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EmitVcmpOrVcmpe(context, true);
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}
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private static void EmitVcmpOrVcmpe(ArmEmitterContext context, bool signalNaNs)
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{
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OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
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bool cmpWithZero = (op.Opc & 2) != 0;
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int sizeF = op.Size & 1;
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if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2))
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{
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CmpCondition cmpOrdered = signalNaNs ? CmpCondition.OrderedS : CmpCondition.OrderedQ;
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bool doubleSize = sizeF != 0;
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int shift = doubleSize ? 1 : 2;
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Operand m = GetVecA32(op.Vm >> shift);
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Operand n = GetVecA32(op.Vd >> shift);
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n = EmitSwapScalar(context, n, op.Vd, doubleSize);
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m = cmpWithZero ? context.VectorZero() : EmitSwapScalar(context, m, op.Vm, doubleSize);
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Operand lblNaN = Label();
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Operand lblEnd = Label();
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if (!doubleSize)
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpss, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicInt(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comissge, n, m);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, n, m);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, n, m);
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EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
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}
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else
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{
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Operand ordMask = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, m, Const((int)cmpOrdered));
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Operand isOrdered = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, ordMask);
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context.BranchIfFalse(lblNaN, isOrdered);
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Operand cf = context.AddIntrinsicInt(Intrinsic.X86Comisdge, n, m);
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Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, n, m);
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Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, n, m);
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EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
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}
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context.Branch(lblEnd);
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context.MarkLabel(lblNaN);
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EmitSetFPSCRFlags(context, Const(3));
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context.MarkLabel(lblEnd);
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}
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else
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{
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OperandType type = sizeF != 0 ? OperandType.FP64 : OperandType.FP32;
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Operand ne = ExtractScalar(context, type, op.Vd);
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Operand me;
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if (cmpWithZero)
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{
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me = sizeF == 0 ? ConstF(0f) : ConstF(0d);
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}
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else
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{
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me = ExtractScalar(context, type, op.Vm);
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}
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Delegate dlg = sizeF != 0
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? (Delegate)new _S32_F64_F64_Bool(SoftFloat64.FPCompare)
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: (Delegate)new _S32_F32_F32_Bool(SoftFloat32.FPCompare);
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Operand nzcv = context.Call(dlg, ne, me, Const(signalNaNs));
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EmitSetFPSCRFlags(context, nzcv);
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}
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}
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private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand nzcv)
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{
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Operand Extract(Operand value, int bit)
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{
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if (bit != 0)
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{
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value = context.ShiftRightUI(value, Const(bit));
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}
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value = context.BitwiseAnd(value, Const(1));
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return value;
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}
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SetFpFlag(context, FPState.VFlag, Extract(nzcv, 0));
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SetFpFlag(context, FPState.CFlag, Extract(nzcv, 1));
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SetFpFlag(context, FPState.ZFlag, Extract(nzcv, 2));
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SetFpFlag(context, FPState.NFlag, Extract(nzcv, 3));
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}
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private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand n, Operand z, Operand c, Operand v)
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{
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SetFpFlag(context, FPState.VFlag, v);
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SetFpFlag(context, FPState.CFlag, c);
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SetFpFlag(context, FPState.ZFlag, z);
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SetFpFlag(context, FPState.NFlag, n);
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}
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private static void EmitSse2CmpOpF32(ArmEmitterContext context, CmpCondition cond, bool zero)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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int sizeF = op.Size & 1;
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Intrinsic inst = (sizeF == 0) ? Intrinsic.X86Cmpps : Intrinsic.X86Cmppd;
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if (zero)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(inst, m, context.VectorZero(), Const((int)cond));
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});
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}
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else
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{
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EmitVectorBinaryOpSimd32(context, (n, m) =>
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{
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return context.AddIntrinsic(inst, n, m, Const((int)cond));
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});
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}
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}
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}
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}
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