forked from Mirror/Ryujinx
Implement CSET and CSETP shader instructions (#4318)
* Implement CSET and CSETP shader instructions * Shader cache version bump * Fix CC.HI
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2747f12591
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6 changed files with 90 additions and 42 deletions
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@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
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private const ushort FileFormatVersionMajor = 1;
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private const ushort FileFormatVersionMinor = 2;
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private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
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private const uint CodeGenVersion = 3939;
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private const uint CodeGenVersion = 4318;
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private const string SharedTocFileName = "shared.toc";
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private const string SharedDataFileName = "shared.data";
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@ -91,6 +91,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Neu = 13,
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Geu = 14,
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T = 15,
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Off = 16,
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Lo = 17,
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Sff = 18,
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Ls = 19,
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@ -54,13 +54,6 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Config.GpuAccessor.Log("Shader instruction Cctlt is not implemented.");
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}
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public static void Cset(EmitterContext context)
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{
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InstCset op = context.GetOp<InstCset>();
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context.Config.GpuAccessor.Log("Shader instruction Cset is not implemented.");
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}
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public static void Cs2r(EmitterContext context)
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{
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InstCs2r op = context.GetOp<InstCs2r>();
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@ -0,0 +1,87 @@
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Cset(EmitterContext context)
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{
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InstCset op = context.GetOp<InstCset>();
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Operand res = GetCondition(context, op.Ccc);
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Operand srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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res = GetPredLogicalOp(context, op.Bop, res, srcPred);
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Operand dest = GetDest(op.Dest);
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if (op.BVal)
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{
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context.Copy(dest, context.ConditionalSelect(res, ConstF(1), Const(0)));
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}
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else
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{
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context.Copy(dest, res);
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}
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// TODO: CC.
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}
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public static void Csetp(EmitterContext context)
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{
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InstCsetp op = context.GetOp<InstCsetp>();
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Operand p0Res = GetCondition(context, op.Ccc);
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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p0Res = GetPredLogicalOp(context, op.Bop, p0Res, srcPred);
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p1Res = GetPredLogicalOp(context, op.Bop, p1Res, srcPred);
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context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
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context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
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// TODO: CC.
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}
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private static Operand GetCondition(EmitterContext context, Ccc cond, int defaultCond = IrConsts.True)
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{
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return cond switch
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{
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Ccc.F => Const(IrConsts.False),
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Ccc.Lt => context.BitwiseExclusiveOr(context.BitwiseAnd(GetNF(), context.BitwiseNot(GetZF())), GetVF()),
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Ccc.Eq => context.BitwiseAnd(context.BitwiseNot(GetNF()), GetZF()),
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Ccc.Le => context.BitwiseExclusiveOr(GetNF(), context.BitwiseOr(GetZF(), GetVF())),
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Ccc.Gt => context.BitwiseNot(context.BitwiseOr(context.BitwiseExclusiveOr(GetNF(), GetVF()), GetZF())),
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Ccc.Ne => context.BitwiseNot(GetZF()),
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Ccc.Ge => context.BitwiseNot(context.BitwiseExclusiveOr(GetNF(), GetVF())),
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Ccc.Num => context.BitwiseNot(context.BitwiseAnd(GetNF(), GetZF())),
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Ccc.Nan => context.BitwiseAnd(GetNF(), GetZF()),
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Ccc.Ltu => context.BitwiseExclusiveOr(GetNF(), GetVF()),
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Ccc.Equ => GetZF(),
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Ccc.Leu => context.BitwiseOr(context.BitwiseExclusiveOr(GetNF(), GetVF()), GetZF()),
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Ccc.Gtu => context.BitwiseExclusiveOr(context.BitwiseNot(GetNF()), context.BitwiseOr(GetVF(), GetZF())),
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Ccc.Neu => context.BitwiseOr(GetNF(), context.BitwiseNot(GetZF())),
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Ccc.Geu => context.BitwiseExclusiveOr(context.BitwiseOr(context.BitwiseNot(GetNF()), GetZF()), GetVF()),
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Ccc.T => Const(IrConsts.True),
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Ccc.Off => context.BitwiseNot(GetVF()),
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Ccc.Lo => context.BitwiseNot(GetCF()),
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Ccc.Sff => context.BitwiseNot(GetNF()),
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Ccc.Ls => context.BitwiseOr(GetZF(), context.BitwiseNot(GetCF())),
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Ccc.Hi => context.BitwiseAnd(GetCF(), context.BitwiseNot(GetZF())),
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Ccc.Sft => GetNF(),
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Ccc.Hs => GetCF(),
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Ccc.Oft => GetVF(),
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Ccc.Rle => context.BitwiseOr(GetNF(), GetZF()),
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Ccc.Rgt => context.BitwiseNot(context.BitwiseOr(GetNF(), GetZF())),
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_ => Const(defaultCond)
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};
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}
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}
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}
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@ -318,21 +318,5 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.BranchIfTrue(label, pred);
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}
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}
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private static Operand GetCondition(EmitterContext context, Ccc cond, int defaultCond = IrConsts.True)
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{
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// TODO: More condition codes, figure out how they work.
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switch (cond)
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{
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case Ccc.Eq:
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case Ccc.Equ:
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return GetZF();
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case Ccc.Ne:
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case Ccc.Neu:
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return context.BitwiseNot(GetZF());
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}
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return Const(defaultCond);
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}
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}
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}
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@ -11,23 +11,6 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Csetp(EmitterContext context)
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{
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InstCsetp op = context.GetOp<InstCsetp>();
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// TODO: Implement that properly.
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Operand p0Res = Const(IrConsts.True);
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand srcPred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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p0Res = GetPredLogicalOp(context, op.Bop, p0Res, srcPred);
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p1Res = GetPredLogicalOp(context, op.Bop, p1Res, srcPred);
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context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
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context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
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}
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public static void IcmpR(EmitterContext context)
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{
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InstIcmpR op = context.GetOp<InstIcmpR>();
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