mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-20 01:06:35 +00:00
Fix EmitScalarUnaryOpF and add SSRA (vector)
This commit is contained in:
parent
30bcb8da33
commit
553f6c2976
3 changed files with 35 additions and 9 deletions
|
@ -251,6 +251,7 @@ namespace ChocolArm64
|
||||||
Set("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
|
Set("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
|
||||||
Set("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
|
Set("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
|
||||||
Set("0x0011110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
|
Set("0x0011110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
|
||||||
|
Set("0x0011110>>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
|
||||||
Set("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
|
Set("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
|
||||||
Set("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
|
Set("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs));
|
||||||
Set("0x00110100000000xx0xxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
|
Set("0x00110100000000xx0xxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs));
|
||||||
|
|
|
@ -207,7 +207,7 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
|
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
|
||||||
{
|
{
|
||||||
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
||||||
|
|
||||||
int SizeF = Op.Size & 1;
|
int SizeF = Op.Size & 1;
|
||||||
|
|
||||||
|
@ -227,7 +227,7 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
if (Opers.HasFlag(OperFlags.Rm))
|
if (Opers.HasFlag(OperFlags.Rm))
|
||||||
{
|
{
|
||||||
EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
|
EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Rm, Index, SizeF);
|
||||||
}
|
}
|
||||||
|
|
||||||
Emit();
|
Emit();
|
||||||
|
|
|
@ -29,7 +29,7 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
int Shift = Op.Imm - (8 << Op.Size);
|
int Shift = Op.Imm - (8 << Op.Size);
|
||||||
|
|
||||||
EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
|
EmitVectorBinaryShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void Shll_V(AILEmitterCtx Context)
|
public static void Shll_V(AILEmitterCtx Context)
|
||||||
|
@ -83,7 +83,22 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
int Shift = (8 << (Op.Size + 1)) - Op.Imm;
|
int Shift = (8 << (Op.Size + 1)) - Op.Imm;
|
||||||
|
|
||||||
EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift);
|
EmitVectorBinaryShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift);
|
||||||
|
}
|
||||||
|
|
||||||
|
public static void Ssra_V(AILEmitterCtx Context)
|
||||||
|
{
|
||||||
|
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
|
||||||
|
|
||||||
|
int Shift = (8 << (Op.Size + 1)) - Op.Imm;
|
||||||
|
|
||||||
|
Action Emit = () =>
|
||||||
|
{
|
||||||
|
Context.Emit(OpCodes.Shr);
|
||||||
|
Context.Emit(OpCodes.Add);
|
||||||
|
};
|
||||||
|
|
||||||
|
EmitVectorTernaryShImmBinarySx(Context, Emit, Shift);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void Ushl_V(AILEmitterCtx Context)
|
public static void Ushl_V(AILEmitterCtx Context)
|
||||||
|
@ -202,17 +217,22 @@ namespace ChocolArm64.Instruction
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
private static void EmitVectorBinaryShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||||
{
|
{
|
||||||
EmitVectorShImmBinaryOp(Context, Emit, Imm, true);
|
EmitVectorShImmBinaryOp(Context, Emit, Imm, false, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
private static void EmitVectorTernaryShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||||
{
|
{
|
||||||
EmitVectorShImmBinaryOp(Context, Emit, Imm, false);
|
EmitVectorShImmBinaryOp(Context, Emit, Imm, true, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void EmitVectorShImmBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
private static void EmitVectorBinaryShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
||||||
|
{
|
||||||
|
EmitVectorShImmBinaryOp(Context, Emit, Imm, false, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
private static void EmitVectorShImmBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Ternary, bool Signed)
|
||||||
{
|
{
|
||||||
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
||||||
|
|
||||||
|
@ -220,6 +240,11 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
|
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
|
||||||
{
|
{
|
||||||
|
if (Ternary)
|
||||||
|
{
|
||||||
|
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
||||||
|
}
|
||||||
|
|
||||||
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
||||||
|
|
||||||
Context.EmitLdc_I4(Imm);
|
Context.EmitLdc_I4(Imm);
|
||||||
|
|
Loading…
Reference in a new issue