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Logic Operations
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parent
e928ec9708
commit
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5 changed files with 42 additions and 9 deletions
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@ -38,7 +38,7 @@
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<PackageVersion Include="Ryujinx.SDL2-CS" Version="2.30.0-build32" />
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<PackageVersion Include="securifybv.ShellLink" Version="0.1.0" />
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<PackageVersion Include="shaderc.net" Version="0.1.0" />
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<PackageVersion Include="SharpMetal" Version="1.0.0-preview18" />
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<PackageVersion Include="SharpMetal" Version="1.0.0-preview20" />
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<PackageVersion Include="SharpZipLib" Version="1.4.2" />
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<PackageVersion Include="Silk.NET.Vulkan" Version="2.21.0" />
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<PackageVersion Include="Silk.NET.Vulkan.Extensions.EXT" Version="2.21.0" />
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@ -663,6 +663,14 @@ namespace Ryujinx.Graphics.Metal
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SignalDirty(DirtyFlags.DepthBias);
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}
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public readonly void UpdateLogicOpState(bool enable, LogicalOp op)
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{
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_currentState.Pipeline.LogicOpEnable = enable;
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_currentState.Pipeline.LogicOp = op.Convert();
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SignalDirty(DirtyFlags.RenderPipeline);
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}
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public readonly void UpdateMultisampleState(MultisampleDescriptor multisample)
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{
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_currentState.Pipeline.AlphaToCoverageEnable = multisample.AlphaToCoverageEnable;
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@ -1,6 +1,7 @@
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using Ryujinx.Common.Logging;
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using Ryujinx.Graphics.GAL;
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using SharpMetal.Metal;
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using System;
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using System.Runtime.Versioning;
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namespace Ryujinx.Graphics.Metal
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@ -112,6 +113,30 @@ namespace Ryujinx.Graphics.Metal
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};
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}
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public static MTLLogicOperation Convert(this LogicalOp op)
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{
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return op switch
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{
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LogicalOp.Clear => MTLLogicOperation.Clear,
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LogicalOp.And => MTLLogicOperation.And,
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LogicalOp.AndReverse => MTLLogicOperation.AndReverse,
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LogicalOp.Copy => MTLLogicOperation.Copy,
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LogicalOp.AndInverted => MTLLogicOperation.AndInverted,
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LogicalOp.Noop => MTLLogicOperation.Noop,
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LogicalOp.Xor => MTLLogicOperation.Xor,
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LogicalOp.Or => MTLLogicOperation.Or,
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LogicalOp.Nor => MTLLogicOperation.Nor,
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LogicalOp.Equiv => MTLLogicOperation.Equivalence,
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LogicalOp.Invert => MTLLogicOperation.Invert,
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LogicalOp.OrReverse => MTLLogicOperation.OrReverse,
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LogicalOp.CopyInverted => MTLLogicOperation.CopyInverted,
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LogicalOp.OrInverted => MTLLogicOperation.OrInverted,
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LogicalOp.Nand => MTLLogicOperation.Nand,
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LogicalOp.Set => MTLLogicOperation.Set,
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_ => LogInvalidAndReturn(op, nameof(LogicalOp), MTLLogicOperation.And)
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};
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}
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public static MTLSamplerMinMagFilter Convert(this MagFilter filter)
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{
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return filter switch
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@ -669,7 +669,7 @@ namespace Ryujinx.Graphics.Metal
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public void SetLogicOpState(bool enable, LogicalOp op)
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{
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// Metal does not support logic operations.
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_encoderStateManager.UpdateLogicOpState(enable, op);
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}
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public void SetMultisampleState(MultisampleDescriptor multisample)
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@ -45,10 +45,9 @@ namespace Ryujinx.Graphics.Metal
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}
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*/
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// Reserved for when API is available.
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public int LogicOp
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public MTLLogicOperation LogicOp
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{
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readonly get => (int)((Internal.Id0 >> 32) & 0xF);
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readonly get => (MTLLogicOperation)((Internal.Id0 >> 32) & 0xF);
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set => Internal.Id0 = (Internal.Id0 & 0xFFFFFFF0FFFFFFFF) | ((ulong)value << 32);
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}
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@ -65,7 +64,6 @@ namespace Ryujinx.Graphics.Metal
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set => Internal.Id0 = (Internal.Id0 & 0xFFFFFFDFFFFFFFFF) | ((value ? 1UL : 0UL) << 37);
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}
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// Reserved for when API is available.
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public bool LogicOpEnable
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{
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readonly get => ((Internal.Id0 >> 38) & 0x1) != 0UL;
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@ -208,9 +206,11 @@ namespace Ryujinx.Graphics.Metal
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}
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}
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renderPipelineDescriptor.SetAlphaToCoverageEnabled(AlphaToCoverageEnable);
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renderPipelineDescriptor.SetAlphaToOneEnabled(AlphaToOneEnable);
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renderPipelineDescriptor.SetRasterizationEnabled(!RasterizerDiscardEnable);
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renderPipelineDescriptor.LogicOperationEnabled = LogicOpEnable;
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renderPipelineDescriptor.LogicOperation = LogicOp;
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renderPipelineDescriptor.AlphaToCoverageEnabled = AlphaToCoverageEnable;
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renderPipelineDescriptor.AlphaToOneEnabled = AlphaToOneEnable;
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renderPipelineDescriptor.RasterizationEnabled = !RasterizerDiscardEnable;
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renderPipelineDescriptor.SampleCount = Math.Max(1, SamplesCount);
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var vertexDescriptor = BuildVertexDescriptor();
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