mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-05 16:21:23 +00:00
43ebd7a9bb
* New shader cache implementation * Remove some debug code * Take transform feedback varying count into account * Create shader cache directory if it does not exist + fragment output map related fixes * Remove debug code * Only check texture descriptors if the constant buffer is bound * Also check CPU VA on GetSpanMapped * Remove more unused code and move cache related code * XML docs + remove more unused methods * Better codegen for TransformFeedbackDescriptor.AsSpan * Support migration from old cache format, remove more unused code Shader cache rebuild now also rewrites the shared toc and data files * Fix migration error with BRX shaders * Add a limit to the async translation queue Avoid async translation threads not being able to keep up and the queue growing very large * Re-create specialization state on recompile This might be required if a new version of the shader translator requires more or less state, or if there is a bug related to the GPU state access * Make shader cache more error resilient * Add some missing XML docs and move GpuAccessor docs to the interface/use inheritdoc * Address early PR feedback * Fix rebase * Remove IRenderer.CompileShader and IShader interface, replace with new ShaderSource struct passed to CreateProgram directly * Handle some missing exceptions * Make shader cache purge delete both old and new shader caches * Register textures on new specialization state * Translate and compile shaders in forward order (eliminates diffs due to different binding numbers) * Limit in-flight shader compilation to the maximum number of compilation threads * Replace ParallelDiskCacheLoader state changed event with a callback function * Better handling for invalid constant buffer 1 data length * Do not create the old cache directory structure if the old cache does not exist * Constant buffer use should be per-stage. This change will invalidate existing new caches (file format version was incremented) * Replace rectangle texture with just coordinate normalization * Skip incompatible shaders that are missing texture information, instead of crashing This is required if we, for example, support new texture instruction to the shader translator, and then they allow access to textures that were not accessed before. In this scenario, the old cache entry is no longer usable * Fix coordinates normalization on cubemap textures * Check if title ID is null before combining shader cache path * More robust constant buffer address validation on spec state * More robust constant buffer address validation on spec state (2) * Regenerate shader cache with one stream, rather than one per shader. * Only create shader cache directory during initialization * Logging improvements * Proper shader program disposal * PR feedback, and add a comment on serialized structs * XML docs for RegisterTexture Co-authored-by: riperiperi <rhy3756547@hotmail.com>
337 lines
No EOL
12 KiB
C#
337 lines
No EOL
12 KiB
C#
using Ryujinx.Graphics.Shader.CodeGen.Glsl;
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.StructuredIr;
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using Ryujinx.Graphics.Shader.Translation.Optimizations;
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using System;
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using System.Linq;
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using System.Numerics;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Translation
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{
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public static class Translator
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{
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private const int HeaderSize = 0x50;
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internal struct FunctionCode
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{
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public Operation[] Code { get; }
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public FunctionCode(Operation[] code)
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{
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Code = code;
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}
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}
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public static TranslatorContext CreateContext(ulong address, IGpuAccessor gpuAccessor, TranslationOptions options)
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{
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return DecodeShader(address, gpuAccessor, options);
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}
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internal static ShaderProgram Translate(FunctionCode[] functions, ShaderConfig config)
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{
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var cfgs = new ControlFlowGraph[functions.Length];
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var frus = new RegisterUsage.FunctionRegisterUsage[functions.Length];
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for (int i = 0; i < functions.Length; i++)
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{
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cfgs[i] = ControlFlowGraph.Create(functions[i].Code);
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if (i != 0)
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{
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frus[i] = RegisterUsage.RunPass(cfgs[i]);
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}
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}
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Function[] funcs = new Function[functions.Length];
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for (int i = 0; i < functions.Length; i++)
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{
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var cfg = cfgs[i];
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int inArgumentsCount = 0;
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int outArgumentsCount = 0;
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if (i != 0)
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{
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var fru = frus[i];
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inArgumentsCount = fru.InArguments.Length;
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outArgumentsCount = fru.OutArguments.Length;
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}
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if (cfg.Blocks.Length != 0)
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{
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RegisterUsage.FixupCalls(cfg.Blocks, frus);
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Dominance.FindDominators(cfg);
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Dominance.FindDominanceFrontiers(cfg.Blocks);
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Ssa.Rename(cfg.Blocks);
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Optimizer.RunPass(cfg.Blocks, config);
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Rewriter.RunPass(cfg.Blocks, config);
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}
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funcs[i] = new Function(cfg.Blocks, $"fun{i}", false, inArgumentsCount, outArgumentsCount);
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}
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StructuredProgramInfo sInfo = StructuredProgram.MakeStructuredProgram(funcs, config);
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ShaderProgramInfo info = new ShaderProgramInfo(
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config.GetConstantBufferDescriptors(),
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config.GetStorageBufferDescriptors(),
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config.GetTextureDescriptors(),
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config.GetImageDescriptors(),
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config.Stage,
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config.UsedFeatures.HasFlag(FeatureFlags.InstanceId),
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config.UsedFeatures.HasFlag(FeatureFlags.RtLayer),
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config.ClipDistancesWritten,
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config.OmapTargets);
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return config.Options.TargetLanguage switch
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{
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TargetLanguage.Glsl => new ShaderProgram(info, TargetLanguage.Glsl, GlslGenerator.Generate(sInfo, config)),
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_ => throw new NotImplementedException(config.Options.TargetLanguage.ToString())
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};
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}
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private static TranslatorContext DecodeShader(ulong address, IGpuAccessor gpuAccessor, TranslationOptions options)
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{
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ShaderConfig config;
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DecodedProgram program;
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ulong maxEndAddress = 0;
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if ((options.Flags & TranslationFlags.Compute) != 0)
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{
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config = new ShaderConfig(gpuAccessor, options);
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program = Decoder.Decode(config, address);
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}
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else
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{
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config = new ShaderConfig(new ShaderHeader(gpuAccessor, address), gpuAccessor, options);
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program = Decoder.Decode(config, address + HeaderSize);
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}
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foreach (DecodedFunction function in program)
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{
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foreach (Block block in function.Blocks)
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{
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if (maxEndAddress < block.EndAddress)
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{
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maxEndAddress = block.EndAddress;
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}
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}
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}
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config.SizeAdd((int)maxEndAddress + (options.Flags.HasFlag(TranslationFlags.Compute) ? 0 : HeaderSize));
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return new TranslatorContext(address, program, config);
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}
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internal static FunctionCode[] EmitShader(DecodedProgram program, ShaderConfig config, bool initializeOutputs, out int initializationOperations)
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{
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initializationOperations = 0;
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FunctionMatch.RunPass(program);
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foreach (DecodedFunction function in program.OrderBy(x => x.Address).Where(x => !x.IsCompilerGenerated))
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{
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program.AddFunctionAndSetId(function);
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}
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FunctionCode[] functions = new FunctionCode[program.FunctionsWithIdCount];
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for (int index = 0; index < functions.Length; index++)
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{
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EmitterContext context = new EmitterContext(program, config, index != 0);
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if (initializeOutputs && index == 0)
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{
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EmitOutputsInitialization(context, config);
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initializationOperations = context.OperationsCount;
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}
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DecodedFunction function = program.GetFunctionById(index);
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foreach (Block block in function.Blocks)
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{
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context.CurrBlock = block;
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context.MarkLabel(context.GetLabel(block.Address));
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EmitOps(context, block);
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}
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functions[index] = new FunctionCode(context.GetOperations());
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}
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return functions;
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}
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private static void EmitOutputsInitialization(EmitterContext context, ShaderConfig config)
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{
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// Compute has no output attributes, and fragment is the last stage, so we
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// don't need to initialize outputs on those stages.
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if (config.Stage == ShaderStage.Compute || config.Stage == ShaderStage.Fragment)
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{
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return;
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}
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if (config.Stage == ShaderStage.Vertex)
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{
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InitializeOutput(context, AttributeConsts.PositionX, perPatch: false);
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}
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UInt128 usedAttributes = context.Config.NextInputAttributesComponents;
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while (usedAttributes != UInt128.Zero)
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{
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int index = usedAttributes.TrailingZeroCount();
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int vecIndex = index / 4;
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usedAttributes &= ~UInt128.Pow2(index);
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// We don't need to initialize passthrough attributes.
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if ((context.Config.PassthroughAttributes & (1 << vecIndex)) != 0)
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{
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continue;
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}
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InitializeOutputComponent(context, AttributeConsts.UserAttributeBase + index * 4, perPatch: false);
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}
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UInt128 usedAttributesPerPatch = context.Config.NextInputAttributesPerPatchComponents;
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while (usedAttributesPerPatch != UInt128.Zero)
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{
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int index = usedAttributesPerPatch.TrailingZeroCount();
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InitializeOutputComponent(context, AttributeConsts.UserAttributeBase + index * 4, perPatch: true);
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usedAttributesPerPatch &= ~UInt128.Pow2(index);
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}
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if (config.NextUsesFixedFuncAttributes)
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{
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for (int i = 0; i < 4 + AttributeConsts.TexCoordCount; i++)
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{
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int index = config.GetFreeUserAttribute(isOutput: true, i);
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if (index < 0)
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{
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break;
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}
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InitializeOutput(context, AttributeConsts.UserAttributeBase + index * 16, perPatch: false);
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config.SetOutputUserAttributeFixedFunc(index);
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}
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}
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}
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private static void InitializeOutput(EmitterContext context, int baseAttr, bool perPatch)
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{
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for (int c = 0; c < 4; c++)
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{
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int attrOffset = baseAttr + c * 4;
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context.Copy(perPatch ? AttributePerPatch(attrOffset) : Attribute(attrOffset), ConstF(c == 3 ? 1f : 0f));
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}
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}
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private static void InitializeOutputComponent(EmitterContext context, int attrOffset, bool perPatch)
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{
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int c = (attrOffset >> 2) & 3;
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context.Copy(perPatch ? AttributePerPatch(attrOffset) : Attribute(attrOffset), ConstF(c == 3 ? 1f : 0f));
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}
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private static void EmitOps(EmitterContext context, Block block)
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{
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for (int opIndex = 0; opIndex < block.OpCodes.Count; opIndex++)
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{
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InstOp op = block.OpCodes[opIndex];
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if (context.Config.Options.Flags.HasFlag(TranslationFlags.DebugMode))
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{
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string instName;
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if (op.Emitter != null)
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{
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instName = op.Name.ToString();
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}
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else
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{
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instName = "???";
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context.Config.GpuAccessor.Log($"Invalid instruction at 0x{op.Address:X6} (0x{op.RawOpCode:X16}).");
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}
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string dbgComment = $"0x{op.Address:X6}: 0x{op.RawOpCode:X16} {instName}";
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context.Add(new CommentNode(dbgComment));
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}
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InstConditional opConditional = new InstConditional(op.RawOpCode);
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bool noPred = op.Props.HasFlag(InstProps.NoPred);
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if (!noPred && opConditional.Pred == RegisterConsts.PredicateTrueIndex && opConditional.PredInv)
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{
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continue;
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}
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Operand predSkipLbl = null;
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if (Decoder.IsPopBranch(op.Name))
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{
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// If the instruction is a SYNC or BRK instruction with only one
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// possible target address, then the instruction is basically
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// just a simple branch, we can generate code similar to branch
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// instructions, with the condition check on the branch itself.
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noPred = block.SyncTargets.Count <= 1;
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}
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else if (op.Name == InstName.Bra)
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{
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noPred = true;
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}
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if (!(opConditional.Pred == RegisterConsts.PredicateTrueIndex || noPred))
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{
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Operand label;
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if (opIndex == block.OpCodes.Count - 1 && block.HasNext())
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{
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label = context.GetLabel(block.Successors[0].Address);
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}
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else
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{
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label = Label();
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predSkipLbl = label;
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}
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Operand pred = Register(opConditional.Pred, RegisterType.Predicate);
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if (opConditional.PredInv)
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{
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context.BranchIfTrue(label, pred);
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}
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else
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{
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context.BranchIfFalse(label, pred);
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}
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}
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context.CurrOp = op;
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op.Emitter?.Invoke(context);
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if (predSkipLbl != null)
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{
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context.MarkLabel(predSkipLbl);
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}
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}
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}
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}
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} |