mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-20 01:56:34 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
253 lines
No EOL
8 KiB
C#
253 lines
No EOL
8 KiB
C#
using ARMeilleure.Decoders;
|
|
using ARMeilleure.Diagnostics;
|
|
using ARMeilleure.Instructions;
|
|
using ARMeilleure.IntermediateRepresentation;
|
|
using ARMeilleure.Memory;
|
|
using ARMeilleure.State;
|
|
using System;
|
|
using System.Collections.Concurrent;
|
|
using System.Threading;
|
|
|
|
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
|
|
|
|
namespace ARMeilleure.Translation
|
|
{
|
|
public class Translator : ITranslator
|
|
{
|
|
private const ulong CallFlag = InstEmitFlowHelper.CallFlag;
|
|
|
|
private MemoryManager _memory;
|
|
|
|
private ConcurrentDictionary<ulong, TranslatedFunction> _funcs;
|
|
|
|
private PriorityQueue<ulong> _backgroundQueue;
|
|
|
|
private AutoResetEvent _backgroundTranslatorEvent;
|
|
|
|
private volatile int _threadCount;
|
|
|
|
public Translator(MemoryManager memory)
|
|
{
|
|
_memory = memory;
|
|
|
|
_funcs = new ConcurrentDictionary<ulong, TranslatedFunction>();
|
|
|
|
_backgroundQueue = new PriorityQueue<ulong>(2);
|
|
|
|
_backgroundTranslatorEvent = new AutoResetEvent(false);
|
|
}
|
|
|
|
private void TranslateQueuedSubs()
|
|
{
|
|
while (_threadCount != 0)
|
|
{
|
|
if (_backgroundQueue.TryDequeue(out ulong address))
|
|
{
|
|
TranslatedFunction func = Translate(address, ExecutionMode.Aarch64, highCq: true);
|
|
|
|
_funcs.AddOrUpdate(address, func, (key, oldFunc) => func);
|
|
}
|
|
else
|
|
{
|
|
_backgroundTranslatorEvent.WaitOne();
|
|
}
|
|
}
|
|
}
|
|
|
|
public void Execute(IExecutionContext ctx, ulong address)
|
|
{
|
|
State.ExecutionContext context = (State.ExecutionContext)ctx;
|
|
|
|
if (Interlocked.Increment(ref _threadCount) == 1)
|
|
{
|
|
Thread backgroundTranslatorThread = new Thread(TranslateQueuedSubs);
|
|
|
|
backgroundTranslatorThread.Priority = ThreadPriority.Lowest;
|
|
backgroundTranslatorThread.Start();
|
|
}
|
|
|
|
Statistics.InitializeTimer();
|
|
|
|
NativeInterface.RegisterThread(context, _memory);
|
|
|
|
do
|
|
{
|
|
address = ExecuteSingle(context, address);
|
|
}
|
|
while (context.Running && (address & ~1UL) != 0);
|
|
|
|
NativeInterface.UnregisterThread();
|
|
|
|
if (Interlocked.Decrement(ref _threadCount) == 0)
|
|
{
|
|
_backgroundTranslatorEvent.Set();
|
|
}
|
|
}
|
|
|
|
public ulong ExecuteSingle(State.ExecutionContext context, ulong address)
|
|
{
|
|
TranslatedFunction func = GetOrTranslate(address, context.ExecutionMode);
|
|
|
|
Statistics.StartTimer();
|
|
|
|
ulong nextAddr = func.Execute(context);
|
|
|
|
Statistics.StopTimer(address);
|
|
|
|
return nextAddr;
|
|
}
|
|
|
|
private TranslatedFunction GetOrTranslate(ulong address, ExecutionMode mode)
|
|
{
|
|
// TODO: Investigate how we should handle code at unaligned addresses.
|
|
// Currently, those low bits are used to store special flags.
|
|
bool isCallTarget = (address & CallFlag) != 0;
|
|
|
|
address &= ~CallFlag;
|
|
|
|
if (!_funcs.TryGetValue(address, out TranslatedFunction func))
|
|
{
|
|
func = Translate(address, mode, highCq: false);
|
|
|
|
_funcs.TryAdd(address, func);
|
|
}
|
|
else if (isCallTarget && func.ShouldRejit())
|
|
{
|
|
_backgroundQueue.Enqueue(0, address);
|
|
|
|
_backgroundTranslatorEvent.Set();
|
|
}
|
|
|
|
return func;
|
|
}
|
|
|
|
private TranslatedFunction Translate(ulong address, ExecutionMode mode, bool highCq)
|
|
{
|
|
ArmEmitterContext context = new ArmEmitterContext(_memory, Aarch32Mode.User);
|
|
|
|
Logger.StartPass(PassName.Decoding);
|
|
|
|
Block[] blocks = highCq
|
|
? Decoder.DecodeFunction (_memory, address, mode)
|
|
: Decoder.DecodeBasicBlock(_memory, address, mode);
|
|
|
|
Logger.EndPass(PassName.Decoding);
|
|
|
|
Logger.StartPass(PassName.Translation);
|
|
|
|
EmitSynchronization(context);
|
|
|
|
if (blocks[0].Address != address)
|
|
{
|
|
context.Branch(context.GetLabel(address));
|
|
}
|
|
|
|
ControlFlowGraph cfg = EmitAndGetCFG(context, blocks);
|
|
|
|
Logger.EndPass(PassName.Translation);
|
|
|
|
Logger.StartPass(PassName.RegisterUsage);
|
|
|
|
RegisterUsage.RunPass(cfg, isCompleteFunction: false);
|
|
|
|
Logger.EndPass(PassName.RegisterUsage);
|
|
|
|
OperandType[] argTypes = new OperandType[] { OperandType.I64 };
|
|
|
|
CompilerOptions options = highCq
|
|
? CompilerOptions.HighCq
|
|
: CompilerOptions.None;
|
|
|
|
GuestFunction func = Compiler.Compile<GuestFunction>(cfg, argTypes, OperandType.I64, options);
|
|
|
|
return new TranslatedFunction(func, rejit: !highCq);
|
|
}
|
|
|
|
private static ControlFlowGraph EmitAndGetCFG(ArmEmitterContext context, Block[] blocks)
|
|
{
|
|
for (int blkIndex = 0; blkIndex < blocks.Length; blkIndex++)
|
|
{
|
|
Block block = blocks[blkIndex];
|
|
|
|
context.CurrBlock = block;
|
|
|
|
context.MarkLabel(context.GetLabel(block.Address));
|
|
|
|
for (int opcIndex = 0; opcIndex < block.OpCodes.Count; opcIndex++)
|
|
{
|
|
OpCode opCode = block.OpCodes[opcIndex];
|
|
|
|
context.CurrOp = opCode;
|
|
|
|
bool isLastOp = opcIndex == block.OpCodes.Count - 1;
|
|
|
|
if (isLastOp && block.Branch != null && block.Branch.Address <= block.Address)
|
|
{
|
|
EmitSynchronization(context);
|
|
}
|
|
|
|
Operand lblPredicateSkip = null;
|
|
|
|
if (opCode is OpCode32 op && op.Cond < Condition.Al)
|
|
{
|
|
lblPredicateSkip = Label();
|
|
|
|
InstEmitFlowHelper.EmitCondBranch(context, lblPredicateSkip, op.Cond.Invert());
|
|
}
|
|
|
|
if (opCode.Instruction.Emitter != null)
|
|
{
|
|
opCode.Instruction.Emitter(context);
|
|
}
|
|
else
|
|
{
|
|
throw new InvalidOperationException($"Invalid instruction \"{opCode.Instruction.Name}\".");
|
|
}
|
|
|
|
if (lblPredicateSkip != null)
|
|
{
|
|
context.MarkLabel(lblPredicateSkip);
|
|
|
|
// If this is the last op on the block, and there's no "next" block
|
|
// after this one, then we have to return right now, with the address
|
|
// of the next instruction to be executed (in the case that the condition
|
|
// is false, and the branch was not taken, as all basic blocks should end
|
|
// with some kind of branch).
|
|
if (isLastOp && block.Next == null)
|
|
{
|
|
context.Return(Const(opCode.Address + (ulong)opCode.OpCodeSizeInBytes));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return context.GetControlFlowGraph();
|
|
}
|
|
|
|
private static void EmitSynchronization(EmitterContext context)
|
|
{
|
|
long countOffs = NativeContext.GetCounterOffset();
|
|
|
|
Operand countAddr = context.Add(context.LoadArgument(OperandType.I64, 0), Const(countOffs));
|
|
|
|
Operand count = context.Load(OperandType.I32, countAddr);
|
|
|
|
Operand lblNonZero = Label();
|
|
Operand lblExit = Label();
|
|
|
|
context.BranchIfTrue(lblNonZero, count);
|
|
|
|
context.Call(new _Void(NativeInterface.CheckSynchronization));
|
|
|
|
context.Branch(lblExit);
|
|
|
|
context.MarkLabel(lblNonZero);
|
|
|
|
count = context.Subtract(count, Const(1));
|
|
|
|
context.Store(countAddr, count);
|
|
|
|
context.MarkLabel(lblExit);
|
|
}
|
|
}
|
|
} |