mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-28 05:54:03 +00:00
59ddb26628
* chore: replace `ByteMemoryPool` usage with `MemoryOwner<byte>` * refactor: `PixelConverter.ConvertR4G4ToR4G4B4A4()` - rename old `outputSpan` to `outputSpanUInt16`, reuse same output `Span<byte>` as newly-freed name `outputSpan` * eliminate temporary buffer allocations * chore, perf: use MemoryOwner<byte> instead of IMemoryOwner<byte>
396 lines
13 KiB
C#
396 lines
13 KiB
C#
using Ryujinx.Common.Memory;
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using Ryujinx.Memory;
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using System;
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using System.Runtime.CompilerServices;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Graphics.Device
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{
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/// <summary>
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/// Device memory manager.
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/// </summary>
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public class DeviceMemoryManager : IWritableBlock
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{
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private const int PtLvl0Bits = 10;
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private const int PtLvl1Bits = 10;
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public const int PtPageBits = 12;
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private const ulong PtLvl0Size = 1UL << PtLvl0Bits;
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private const ulong PtLvl1Size = 1UL << PtLvl1Bits;
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public const ulong PageSize = 1UL << PtPageBits;
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private const ulong PtLvl0Mask = PtLvl0Size - 1;
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private const ulong PtLvl1Mask = PtLvl1Size - 1;
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public const ulong PageMask = PageSize - 1;
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private const int PtLvl0Bit = PtPageBits + PtLvl1Bits;
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private const int PtLvl1Bit = PtPageBits;
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private const int AddressSpaceBits = PtPageBits + PtLvl1Bits + PtLvl0Bits;
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public const ulong PteUnmapped = ulong.MaxValue;
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private readonly ulong[][] _pageTable;
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private readonly IVirtualMemoryManager _physical;
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/// <summary>
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/// Creates a new instance of the GPU memory manager.
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/// </summary>
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/// <param name="physicalMemory">Physical memory that this memory manager will map into</param>
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public DeviceMemoryManager(IVirtualMemoryManager physicalMemory)
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{
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_physical = physicalMemory;
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_pageTable = new ulong[PtLvl0Size][];
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}
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/// <summary>
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/// Reads data from GPU mapped memory.
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/// </summary>
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/// <typeparam name="T">Type of the data</typeparam>
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/// <param name="va">GPU virtual address where the data is located</param>
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/// <returns>The data at the specified memory location</returns>
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public T Read<T>(ulong va) where T : unmanaged
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{
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int size = Unsafe.SizeOf<T>();
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if (IsContiguous(va, size))
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{
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return _physical.Read<T>(Translate(va));
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}
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else
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{
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Span<byte> data = new byte[size];
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ReadImpl(va, data);
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return MemoryMarshal.Cast<byte, T>(data)[0];
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}
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}
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/// <summary>
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/// Gets a read-only span of data from GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address where the data is located</param>
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/// <param name="size">Size of the data</param>
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/// <returns>The span of the data at the specified memory location</returns>
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public ReadOnlySpan<byte> GetSpan(ulong va, int size)
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{
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if (IsContiguous(va, size))
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{
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return _physical.GetSpan(Translate(va), size);
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}
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else
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{
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Span<byte> data = new byte[size];
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ReadImpl(va, data);
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return data;
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}
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}
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/// <summary>
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/// Reads data from a possibly non-contiguous region of GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address of the data</param>
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/// <param name="data">Span to write the read data into</param>
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private void ReadImpl(ulong va, Span<byte> data)
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{
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if (data.Length == 0)
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{
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return;
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}
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int offset = 0, size;
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if ((va & PageMask) != 0)
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{
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ulong pa = Translate(va);
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size = Math.Min(data.Length, (int)PageSize - (int)(va & PageMask));
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if (pa != PteUnmapped && _physical.IsMapped(pa))
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{
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_physical.GetSpan(pa, size).CopyTo(data[..size]);
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}
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offset += size;
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}
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for (; offset < data.Length; offset += size)
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{
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ulong pa = Translate(va + (ulong)offset);
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size = Math.Min(data.Length - offset, (int)PageSize);
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if (pa != PteUnmapped && _physical.IsMapped(pa))
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{
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_physical.GetSpan(pa, size).CopyTo(data.Slice(offset, size));
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}
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}
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}
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/// <summary>
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/// Gets a writable region from GPU mapped memory.
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/// </summary>
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/// <param name="va">Start address of the range</param>
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/// <param name="size">Size in bytes to be range</param>
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/// <returns>A writable region with the data at the specified memory location</returns>
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public WritableRegion GetWritableRegion(ulong va, int size)
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{
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if (IsContiguous(va, size))
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{
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return _physical.GetWritableRegion(Translate(va), size, tracked: true);
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}
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else
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{
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MemoryOwner<byte> memoryOwner = MemoryOwner<byte>.Rent(size);
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ReadImpl(va, memoryOwner.Span);
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return new WritableRegion(this, va, memoryOwner, tracked: true);
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}
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}
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/// <summary>
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/// Writes data to GPU mapped memory.
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/// </summary>
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/// <typeparam name="T">Type of the data</typeparam>
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/// <param name="va">GPU virtual address to write the value into</param>
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/// <param name="value">The value to be written</param>
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public void Write<T>(ulong va, T value) where T : unmanaged
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{
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Write(va, MemoryMarshal.Cast<T, byte>(MemoryMarshal.CreateSpan(ref value, 1)));
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}
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/// <summary>
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/// Writes data to GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address to write the data into</param>
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/// <param name="data">The data to be written</param>
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public void Write(ulong va, ReadOnlySpan<byte> data)
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{
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if (IsContiguous(va, data.Length))
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{
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_physical.Write(Translate(va), data);
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}
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else
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{
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int offset = 0, size;
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if ((va & PageMask) != 0)
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{
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ulong pa = Translate(va);
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size = Math.Min(data.Length, (int)PageSize - (int)(va & PageMask));
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if (pa != PteUnmapped && _physical.IsMapped(pa))
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{
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_physical.Write(pa, data[..size]);
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}
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offset += size;
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}
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for (; offset < data.Length; offset += size)
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{
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ulong pa = Translate(va + (ulong)offset);
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size = Math.Min(data.Length - offset, (int)PageSize);
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if (pa != PteUnmapped && _physical.IsMapped(pa))
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{
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_physical.Write(pa, data.Slice(offset, size));
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}
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}
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}
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}
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/// <summary>
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/// Writes data to GPU mapped memory without write tracking.
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/// </summary>
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/// <param name="va">GPU virtual address to write the data into</param>
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/// <param name="data">The data to be written</param>
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public void WriteUntracked(ulong va, ReadOnlySpan<byte> data)
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{
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throw new NotSupportedException();
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}
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/// <summary>
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/// Maps a given range of pages to the specified CPU virtual address.
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/// </summary>
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/// <remarks>
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/// All addresses and sizes must be page aligned.
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/// </remarks>
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="va">GPU virtual address to be mapped</param>
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/// <param name="kind">Kind of the resource located at the mapping</param>
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public void Map(ulong pa, ulong va, ulong size)
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{
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lock (_pageTable)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PackPte(pa + offset));
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}
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}
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}
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/// <summary>
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/// Unmaps a given range of pages at the specified GPU virtual memory region.
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/// </summary>
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/// <param name="va">GPU virtual address to unmap</param>
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/// <param name="size">Size in bytes of the region being unmapped</param>
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public void Unmap(ulong va, ulong size)
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{
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lock (_pageTable)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PteUnmapped);
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}
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}
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}
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/// <summary>
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/// Checks if a region of GPU mapped memory is contiguous.
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/// </summary>
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/// <param name="va">GPU virtual address of the region</param>
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/// <param name="size">Size of the region</param>
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/// <returns>True if the region is contiguous, false otherwise</returns>
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private bool IsContiguous(ulong va, int size)
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{
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if (!ValidateAddress(va) || GetPte(va) == PteUnmapped)
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{
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return false;
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}
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ulong endVa = (va + (ulong)size + PageMask) & ~PageMask;
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va &= ~PageMask;
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int pages = (int)((endVa - va) / PageSize);
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for (int page = 0; page < pages - 1; page++)
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{
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if (!ValidateAddress(va + PageSize) || GetPte(va + PageSize) == PteUnmapped)
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{
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return false;
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}
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if (Translate(va) + PageSize != Translate(va + PageSize))
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{
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return false;
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}
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va += PageSize;
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}
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return true;
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}
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/// <summary>
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/// Validates a GPU virtual address.
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/// </summary>
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/// <param name="va">Address to validate</param>
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/// <returns>True if the address is valid, false otherwise</returns>
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private static bool ValidateAddress(ulong va)
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{
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return va < (1UL << AddressSpaceBits);
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}
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/// <summary>
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/// Checks if a given page is mapped.
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/// </summary>
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/// <param name="va">GPU virtual address of the page to check</param>
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/// <returns>True if the page is mapped, false otherwise</returns>
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public bool IsMapped(ulong va)
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{
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return Translate(va) != PteUnmapped;
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}
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/// <summary>
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/// Translates a GPU virtual address to a CPU virtual address.
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/// </summary>
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/// <param name="va">GPU virtual address to be translated</param>
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/// <returns>CPU virtual address, or <see cref="PteUnmapped"/> if unmapped</returns>
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public ulong Translate(ulong va)
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{
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if (!ValidateAddress(va))
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{
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return PteUnmapped;
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}
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ulong pte = GetPte(va);
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if (pte == PteUnmapped)
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{
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return PteUnmapped;
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}
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return UnpackPaFromPte(pte) + (va & PageMask);
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}
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/// <summary>
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/// Gets the Page Table entry for a given GPU virtual address.
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/// </summary>
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/// <param name="va">GPU virtual address</param>
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/// <returns>Page table entry (CPU virtual address)</returns>
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private ulong GetPte(ulong va)
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{
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ulong l0 = (va >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (va >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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return PteUnmapped;
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}
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return _pageTable[l0][l1];
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}
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/// <summary>
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/// Sets a Page Table entry at a given GPU virtual address.
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/// </summary>
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/// <param name="va">GPU virtual address</param>
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/// <param name="pte">Page table entry (CPU virtual address)</param>
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private void SetPte(ulong va, ulong pte)
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{
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ulong l0 = (va >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (va >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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_pageTable[l0] = new ulong[PtLvl1Size];
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for (ulong index = 0; index < PtLvl1Size; index++)
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{
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_pageTable[l0][index] = PteUnmapped;
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}
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}
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_pageTable[l0][l1] = pte;
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}
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/// <summary>
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/// Creates a page table entry from a physical address and kind.
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/// </summary>
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/// <param name="pa">Physical address</param>
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/// <returns>Page table entry</returns>
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private static ulong PackPte(ulong pa)
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{
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return pa;
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}
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/// <summary>
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/// Unpacks physical address from a page table entry.
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/// </summary>
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/// <param name="pte">Page table entry</param>
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/// <returns>Physical address</returns>
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private static ulong UnpackPaFromPte(ulong pte)
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{
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return pte;
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}
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}
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}
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