citra/src/core/core.cpp

79 lines
1.7 KiB
C++
Raw Normal View History

// Copyright 2014 Citra Emulator Project
// Licensed under GPLv2
// Refer to the license.txt file included.
#include "common/common_types.h"
#include "core/core.h"
#include "core/settings.h"
#include "core/arm/disassembler/arm_disasm.h"
#include "core/arm/interpreter/arm_interpreter.h"
#include "core/arm/dyncom/arm_dyncom.h"
#include "core/hle/hle.h"
#include "core/hle/kernel/thread.h"
#include "core/hw/hw.h"
namespace Core {
2014-11-18 13:48:11 +00:00
static u64 last_ticks = 0; ///< Last CPU ticks
static ARM_Disasm* disasm = nullptr; ///< ARM disassembler
ARM_Interface* g_app_core = nullptr; ///< ARM11 application core
ARM_Interface* g_sys_core = nullptr; ///< ARM11 system (OS) core
2013-09-27 02:01:09 +00:00
/// Run the core CPU loop
void RunLoop(int tight_loop) {
g_app_core->Run(tight_loop);
HW::Update();
if (HLE::g_reschedule) {
Kernel::Reschedule();
}
2013-09-27 02:01:09 +00:00
}
/// Step the CPU one instruction
void SingleStep() {
RunLoop(1);
}
2013-09-27 02:01:09 +00:00
/// Halt the core
void Halt(const char *msg) {
// TODO(ShizZy): ImplementMe
2013-09-27 02:01:09 +00:00
}
/// Kill the core
void Stop() {
// TODO(ShizZy): ImplementMe
}
/// Initialize the core
int Init() {
2014-04-11 02:45:40 +00:00
NOTICE_LOG(MASTER_LOG, "initialized OK");
2014-11-18 13:48:11 +00:00
disasm = new ARM_Disasm();
g_sys_core = new ARM_Interpreter();
switch (Settings::values.cpu_core) {
case CPU_FastInterpreter:
g_app_core = new ARM_DynCom();
break;
case CPU_Interpreter:
default:
g_app_core = new ARM_Interpreter();
break;
}
2014-11-18 13:48:11 +00:00
last_ticks = Core::g_app_core->GetTicks();
return 0;
}
void Shutdown() {
2014-11-18 13:48:11 +00:00
delete disasm;
delete g_app_core;
delete g_sys_core;
2014-04-11 02:45:40 +00:00
NOTICE_LOG(MASTER_LOG, "shutdown OK");
}
} // namespace