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armemu: Simplify SSAT/SSAT16/SXTB/SXTAB

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This commit is contained in:
Lioncash 2014-12-28 12:19:31 -05:00
parent 9f5b53f9ff
commit 6ce2a38ec4
1 changed files with 46 additions and 69 deletions
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59
src/core/arm/interpreter/armemu.cpp
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@ -6274,29 +6274,13 @@ L_stm_s_takeabort:
}
printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n");
break;
case 0x6a: {
ARMword Rm;
int ror = -1;
switch (BITS(4, 11)) {
case 0x07:
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0x01:
case 0xf3:
//ichfly
//SSAT16
case 0x6a: // SSAT, SSAT16, SXTB, and SXTAB
{
const u8 op2 = BITS(5, 7);
// SSAT16
if (op2 == 0x01) {
const u8 rd_idx = BITS(12, 15);
const u8 rn_idx = BITS(0, 3);
const u8 num_bits = BITS(16, 19) + 1;
@ -6324,32 +6308,25 @@ L_stm_s_takeabort:
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16);
return 1;
}
else if (op2 == 0x03) {
const u8 rotation = BITS(10, 11) * 8;
u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF);
if (rm & 0x80)
rm |= 0xffffff00;
default:
break;
}
if (ror == -1) {
if (BITS(4, 6) == 0x7) {
printf("Unhandled v6 insn: ssat\n");
return 0;
}
break;
}
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF);
if (Rm & 0x80)
Rm |= 0xffffff00;
// SXTB, otherwise SXTAB
if (BITS(16, 19) == 0xf)
/* SXTB */
state->Reg[BITS(12, 15)] = Rm;
state->Reg[BITS(12, 15)] = rm;
else
/* SXTAB */
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
return 1;
}
else {
printf("Unimplemented op: SSAT");
}
}
break;
case 0x6b: // REV, REV16, SXTH, and SXTAH
{