Mirror/citra
1
0
Fork 0
mirror of https://github.com/PabloMK7/citra.git synced 2024-11-20 06:24:17 +00:00
Code Issues Projects Releases Packages Wiki Activity

Shader: Remove OutputRegisters struct

Browse source
This commit is contained in:
Yuri Kunde Schlesner 2016-12-17 14:38:03 -08:00
parent 9ea5eacf91
commit 6fa3687afc
4 changed files with 17 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/video_core/command_processor.cpp
View file

@ -152,8 +152,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
Shader::UnitState shader_unit; Shader::UnitState shader_unit;
shader_unit.LoadInputVertex(immediate_input, regs.vs.num_input_attributes + 1); shader_unit.LoadInputVertex(immediate_input, regs.vs.num_input_attributes + 1);
shader_engine->Run(shader_unit, regs.vs.main_offset); shader_engine->Run(shader_unit, regs.vs.main_offset);
Shader::OutputVertex output_vertex = auto output_vertex = Shader::OutputVertex::FromRegisters(
shader_unit.output_registers.ToVertex(regs.vs); shader_unit.registers.output, regs, regs.vs.output_mask);
// Send to renderer // Send to renderer
using Pica::Shader::OutputVertex; using Pica::Shader::OutputVertex;
@ -291,7 +291,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
shader_engine->Run(shader_unit, regs.vs.main_offset); shader_engine->Run(shader_unit, regs.vs.main_offset);
// Retrieve vertex from register data // Retrieve vertex from register data
output_vertex = shader_unit.output_registers.ToVertex(regs.vs); output_vertex = Shader::OutputVertex::FromRegisters(shader_unit.registers.output,
regs, regs.vs.output_mask);
if (is_indexed) { if (is_indexed) {
vertex_cache[vertex_cache_pos] = output_vertex; vertex_cache[vertex_cache_pos] = output_vertex;

11
src/video_core/shader/shader.cpp
View file

@ -19,7 +19,8 @@ namespace Pica {
namespace Shader { namespace Shader {
OutputVertex OutputRegisters::ToVertex(const Regs::ShaderConfig& config) const { OutputVertex OutputVertex::FromRegisters(Math::Vec4<float24> output_regs[16], const Regs& regs,
u32 output_mask) {
// Setup output data // Setup output data
OutputVertex ret; OutputVertex ret;
// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to // TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
@ -27,13 +28,13 @@ OutputVertex OutputRegisters::ToVertex(const Regs::ShaderConfig& config) const {
unsigned index = 0; unsigned index = 0;
for (unsigned i = 0; i < 7; ++i) { for (unsigned i = 0; i < 7; ++i) {
if (index >= g_state.regs.vs_output_total) if (index >= regs.vs_output_total)
break; break;
if ((config.output_mask & (1 << i)) == 0) if ((output_mask & (1 << i)) == 0)
continue; continue;
const auto& output_register_map = g_state.regs.vs_output_attributes[index]; const auto& output_register_map = regs.vs_output_attributes[index];
u32 semantics[4] = {output_register_map.map_x, output_register_map.map_y, u32 semantics[4] = {output_register_map.map_x, output_register_map.map_y,
output_register_map.map_z, output_register_map.map_w}; output_register_map.map_z, output_register_map.map_w};
@ -41,7 +42,7 @@ OutputVertex OutputRegisters::ToVertex(const Regs::ShaderConfig& config) const {
for (unsigned comp = 0; comp < 4; ++comp) { for (unsigned comp = 0; comp < 4; ++comp) {
float24* out = ((float24*)&ret) + semantics[comp]; float24* out = ((float24*)&ret) + semantics[comp];
if (semantics[comp] != Regs::VSOutputAttributes::INVALID) { if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
*out = value[i][comp]; *out = output_regs[i][comp];
} else { } else {
// Zero output so that attributes which aren't output won't have denormals in them, // Zero output so that attributes which aren't output won't have denormals in them,
// which would slow us down later. // which would slow us down later.

17
src/video_core/shader/shader.h
View file

@ -73,19 +73,13 @@ struct OutputVertex {
ret.Lerp(factor, v1); ret.Lerp(factor, v1);
return ret; return ret;
} }
static OutputVertex FromRegisters(Math::Vec4<float24> output_regs[16], const Regs& regs,
u32 output_mask);
}; };
static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD"); static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size"); static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
struct OutputRegisters {
OutputRegisters() = default;
alignas(16) Math::Vec4<float24> value[16];
OutputVertex ToVertex(const Regs::ShaderConfig& config) const;
};
static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
/** /**
* This structure contains the state information that needs to be unique for a shader unit. The 3DS * This structure contains the state information that needs to be unique for a shader unit. The 3DS
* has four shader units that process shaders in parallel. At the present, Citra only implements a * has four shader units that process shaders in parallel. At the present, Citra only implements a
@ -98,11 +92,10 @@ struct UnitState {
// required to be 16-byte aligned. // required to be 16-byte aligned.
alignas(16) Math::Vec4<float24> input[16]; alignas(16) Math::Vec4<float24> input[16];
alignas(16) Math::Vec4<float24> temporary[16]; alignas(16) Math::Vec4<float24> temporary[16];
alignas(16) Math::Vec4<float24> output[16];
} registers; } registers;
static_assert(std::is_pod<Registers>::value, "Structure is not POD"); static_assert(std::is_pod<Registers>::value, "Structure is not POD");
OutputRegisters output_registers;
bool conditional_code[2]; bool conditional_code[2];
// Two Address registers and one loop counter // Two Address registers and one loop counter
@ -128,7 +121,7 @@ struct UnitState {
static size_t OutputOffset(const DestRegister& reg) { static size_t OutputOffset(const DestRegister& reg) {
switch (reg.GetRegisterType()) { switch (reg.GetRegisterType()) {
case RegisterType::Output: case RegisterType::Output:
return offsetof(UnitState, output_registers.value) + return offsetof(UnitState, registers.output) +
reg.GetIndex() * sizeof(Math::Vec4<float24>); reg.GetIndex() * sizeof(Math::Vec4<float24>);
case RegisterType::Temporary: case RegisterType::Temporary:

4
src/video_core/shader/shader_interpreter.cpp
View file

@ -175,7 +175,7 @@ static void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData
float24* dest = float24* dest =
(instr.common.dest.Value() < 0x10) (instr.common.dest.Value() < 0x10)
? &state.output_registers.value[instr.common.dest.Value().GetIndex()][0] ? &state.registers.output[instr.common.dest.Value().GetIndex()][0]
: (instr.common.dest.Value() < 0x20) : (instr.common.dest.Value() < 0x20)
? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0] ? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
: dummy_vec4_float24; : dummy_vec4_float24;
@ -518,7 +518,7 @@ static void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData
float24* dest = float24* dest =
(instr.mad.dest.Value() < 0x10) (instr.mad.dest.Value() < 0x10)
? &state.output_registers.value[instr.mad.dest.Value().GetIndex()][0] ? &state.registers.output[instr.mad.dest.Value().GetIndex()][0]
: (instr.mad.dest.Value() < 0x20) : (instr.mad.dest.Value() < 0x20)
? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0] ? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
: dummy_vec4_float24; : dummy_vec4_float24;