mirror of
https://github.com/PabloMK7/citra.git
synced 2024-11-26 01:14:04 +00:00
Extracted the attribute setup and draw commands into their own functions
This commit is contained in:
Huw Pascoe
parent
15c7641bef
commit
b3b34a1e76
1 changed files with 222 additions and 217 deletions
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@ -119,6 +119,224 @@ static void WriteUniformFloatReg(ShaderRegs& config, Shader::ShaderSetup& setup,
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}
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}
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}
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}
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static void LoadDefaultVertexAttributes(u32 register_value) {
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auto& regs = g_state.regs;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = register_value;
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// Default attributes are written in a packed format such that four float24 values are encoded
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// in three 32-bit numbers.
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// We write to internal memory once a full such vector is written.
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if (default_attr_counter >= 3) {
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default_attr_counter = 0;
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auto& setup = regs.pipeline.vs_default_attributes_setup;
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if (setup.index >= 16) {
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LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
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return;
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}
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Math::Vec4<float24> attribute;
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// NOTE: The destination component order indeed is "backwards"
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attribute.w = float24::FromRaw(default_attr_write_buffer[0] >> 8);
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attribute.z = float24::FromRaw(((default_attr_write_buffer[0] & 0xFF) << 16) |
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((default_attr_write_buffer[1] >> 16) & 0xFFFF));
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attribute.y = float24::FromRaw(((default_attr_write_buffer[1] & 0xFFFF) << 8) |
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((default_attr_write_buffer[2] >> 24) & 0xFF));
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attribute.x = float24::FromRaw(default_attr_write_buffer[2] & 0xFFFFFF);
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LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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attribute.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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if (setup.index < 15) {
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g_state.input_default_attributes.attr[setup.index] = attribute;
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setup.index++;
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} else {
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// Put each attribute into an immediate input buffer. When all specified immediate
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// attributes are present, the Vertex Shader is invoked and everything is sent to
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// the primitive assembler.
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auto& immediate_input = g_state.immediate.input_vertex;
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auto& immediate_attribute_id = g_state.immediate.current_attribute;
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immediate_input.attr[immediate_attribute_id] = attribute;
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if (immediate_attribute_id < regs.pipeline.max_input_attrib_index) {
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immediate_attribute_id += 1;
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} else {
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MICROPROFILE_SCOPE(GPU_Drawing);
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immediate_attribute_id = 0;
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auto* shader_engine = Shader::GetEngine();
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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static_cast<void*>(&immediate_input));
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Shader::UnitState shader_unit;
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Shader::AttributeBuffer output{};
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shader_unit.LoadInput(regs.vs, immediate_input);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, output);
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// Send to geometry pipeline
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if (g_state.immediate.reset_geometry_pipeline) {
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g_state.geometry_pipeline.Reconfigure();
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g_state.immediate.reset_geometry_pipeline = false;
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}
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ASSERT(!g_state.geometry_pipeline.NeedIndexInput());
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g_state.geometry_pipeline.Setup(shader_engine);
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g_state.geometry_pipeline.SubmitVertex(output);
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// TODO: If drawing after every immediate mode triangle kills performance,
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// change it to flush triangles whenever a drawing config register changes
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// See: https://github.com/citra-emu/citra/pull/2866#issuecomment-327011550
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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}
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}
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}
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}
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static void Draw(u32 command_id) {
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MICROPROFILE_SCOPE(GPU_Drawing);
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auto& regs = g_state.regs;
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#if PICA_LOG_TEV
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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#endif
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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// Processes information about internal vertex attributes to figure out how a vertex is
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// loaded.
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// Later, these can be compiled and cached.
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const u32 base_address = regs.pipeline.vertex_attributes.GetPhysicalBaseAddress();
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VertexLoader loader(regs.pipeline);
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// Load vertices
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bool is_indexed = (command_id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
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const auto& index_info = regs.pipeline.index_array;
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const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
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const u16* index_address_16 = reinterpret_cast<const u16*>(index_address_8);
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bool index_u16 = index_info.format != 0;
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PrimitiveAssembler<Shader::OutputVertex>& primitive_assembler = g_state.primitive_assembler;
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if (g_debug_context && g_debug_context->recorder) {
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for (int i = 0; i < 3; ++i) {
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const auto texture = regs.texturing.GetTextures()[i];
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if (!texture.enabled)
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continue;
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u8* texture_data = Memory::GetPhysicalPointer(texture.config.GetPhysicalAddress());
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g_debug_context->recorder->MemoryAccessed(
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texture_data, Pica::TexturingRegs::NibblesPerPixel(texture.format) *
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texture.config.width / 2 * texture.config.height,
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texture.config.GetPhysicalAddress());
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}
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}
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DebugUtils::MemoryAccessTracker memory_accesses;
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// Simple circular-replacement vertex cache
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// The size has been tuned for optimal balance between hit-rate and the cost of lookup
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const size_t VERTEX_CACHE_SIZE = 32;
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std::array<u16, VERTEX_CACHE_SIZE> vertex_cache_ids;
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std::array<Shader::AttributeBuffer, VERTEX_CACHE_SIZE> vertex_cache;
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Shader::AttributeBuffer vs_output;
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unsigned int vertex_cache_pos = 0;
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vertex_cache_ids.fill(-1);
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auto* shader_engine = Shader::GetEngine();
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Shader::UnitState shader_unit;
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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g_state.geometry_pipeline.Reconfigure();
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g_state.geometry_pipeline.Setup(shader_engine);
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if (g_state.geometry_pipeline.NeedIndexInput())
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ASSERT(is_indexed);
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for (unsigned int index = 0; index < regs.pipeline.num_vertices; ++index) {
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// Indexed rendering doesn't use the start offset
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unsigned int vertex = is_indexed
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? (index_u16 ? index_address_16[index] : index_address_8[index])
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: (index + regs.pipeline.vertex_offset);
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// -1 is a common special value used for primitive restart. Since it's unknown if
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// the PICA supports it, and it would mess up the caching, guard against it here.
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ASSERT(vertex != -1);
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bool vertex_cache_hit = false;
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if (is_indexed) {
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if (g_state.geometry_pipeline.NeedIndexInput()) {
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g_state.geometry_pipeline.SubmitIndex(vertex);
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continue;
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}
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if (g_debug_context && Pica::g_debug_context->recorder) {
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int size = index_u16 ? 2 : 1;
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memory_accesses.AddAccess(base_address + index_info.offset + size * index, size);
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}
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for (unsigned int i = 0; i < VERTEX_CACHE_SIZE; ++i) {
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if (vertex == vertex_cache_ids[i]) {
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vs_output = vertex_cache[i];
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vertex_cache_hit = true;
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break;
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}
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}
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}
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if (!vertex_cache_hit) {
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// Initialize data for the current vertex
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Shader::AttributeBuffer input;
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loader.LoadVertex(base_address, index, vertex, input, memory_accesses);
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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(void*)&input);
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shader_unit.LoadInput(regs.vs, input);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, vs_output);
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if (is_indexed) {
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vertex_cache[vertex_cache_pos] = vs_output;
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vertex_cache_ids[vertex_cache_pos] = vertex;
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vertex_cache_pos = (vertex_cache_pos + 1) % VERTEX_CACHE_SIZE;
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}
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}
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// Send to geometry pipeline
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g_state.geometry_pipeline.SubmitVertex(vs_output);
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}
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for (auto& range : memory_accesses.ranges) {
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g_debug_context->recorder->MemoryAccessed(Memory::GetPhysicalPointer(range.first),
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range.second, range.first);
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}
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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}
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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auto& regs = g_state.regs;
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@ -168,95 +386,9 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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// Load default vertex input attributes
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// Load default vertex input attributes
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235): {
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235):
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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LoadDefaultVertexAttributes(value);
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = value;
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// Default attributes are written in a packed format such that four float24 values are
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// encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if (default_attr_counter >= 3) {
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default_attr_counter = 0;
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auto& setup = regs.pipeline.vs_default_attributes_setup;
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if (setup.index >= 16) {
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LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
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break;
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}
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Math::Vec4<float24> attribute;
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// NOTE: The destination component order indeed is "backwards"
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attribute.w = float24::FromRaw(default_attr_write_buffer[0] >> 8);
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attribute.z = float24::FromRaw(((default_attr_write_buffer[0] & 0xFF) << 16) |
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((default_attr_write_buffer[1] >> 16) & 0xFFFF));
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attribute.y = float24::FromRaw(((default_attr_write_buffer[1] & 0xFFFF) << 8) |
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((default_attr_write_buffer[2] >> 24) & 0xFF));
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attribute.x = float24::FromRaw(default_attr_write_buffer[2] & 0xFFFFFF);
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LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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attribute.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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if (setup.index < 15) {
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g_state.input_default_attributes.attr[setup.index] = attribute;
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setup.index++;
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} else {
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// Put each attribute into an immediate input buffer. When all specified immediate
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// attributes are present, the Vertex Shader is invoked and everything is sent to
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// the primitive assembler.
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auto& immediate_input = g_state.immediate.input_vertex;
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auto& immediate_attribute_id = g_state.immediate.current_attribute;
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immediate_input.attr[immediate_attribute_id] = attribute;
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if (immediate_attribute_id < regs.pipeline.max_input_attrib_index) {
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immediate_attribute_id += 1;
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} else {
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MICROPROFILE_SCOPE(GPU_Drawing);
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immediate_attribute_id = 0;
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auto* shader_engine = Shader::GetEngine();
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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static_cast<void*>(&immediate_input));
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Shader::UnitState shader_unit;
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Shader::AttributeBuffer output{};
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shader_unit.LoadInput(regs.vs, immediate_input);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, output);
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// Send to geometry pipeline
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if (g_state.immediate.reset_geometry_pipeline) {
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g_state.geometry_pipeline.Reconfigure();
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g_state.immediate.reset_geometry_pipeline = false;
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}
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ASSERT(!g_state.geometry_pipeline.NeedIndexInput());
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g_state.geometry_pipeline.Setup(shader_engine);
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g_state.geometry_pipeline.SubmitVertex(output);
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// TODO: If drawing after every immediate mode triangle kills performance,
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// change it to flush triangles whenever a drawing config register changes
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// See: https://github.com/citra-emu/citra/pull/2866#issuecomment-327011550
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch,
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nullptr);
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}
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}
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}
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}
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break;
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break;
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}
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case PICA_REG_INDEX(pipeline.gpu_mode):
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case PICA_REG_INDEX(pipeline.gpu_mode):
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// This register likely just enables vertex processing and doesn't need any special handling
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// This register likely just enables vertex processing and doesn't need any special handling
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@ -275,136 +407,9 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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// It seems like these trigger vertex rendering
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed): {
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed):
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MICROPROFILE_SCOPE(GPU_Drawing);
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Draw(id);
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#if PICA_LOG_TEV
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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#endif
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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// Processes information about internal vertex attributes to figure out how a vertex is
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// loaded.
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// Later, these can be compiled and cached.
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const u32 base_address = regs.pipeline.vertex_attributes.GetPhysicalBaseAddress();
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VertexLoader loader(regs.pipeline);
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||||||
|
|
||||||
// Load vertices
|
|
||||||
bool is_indexed = (id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
|
|
||||||
|
|
||||||
const auto& index_info = regs.pipeline.index_array;
|
|
||||||
const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
|
|
||||||
const u16* index_address_16 = reinterpret_cast<const u16*>(index_address_8);
|
|
||||||
bool index_u16 = index_info.format != 0;
|
|
||||||
|
|
||||||
PrimitiveAssembler<Shader::OutputVertex>& primitive_assembler = g_state.primitive_assembler;
|
|
||||||
|
|
||||||
if (g_debug_context && g_debug_context->recorder) {
|
|
||||||
for (int i = 0; i < 3; ++i) {
|
|
||||||
const auto texture = regs.texturing.GetTextures()[i];
|
|
||||||
if (!texture.enabled)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
u8* texture_data = Memory::GetPhysicalPointer(texture.config.GetPhysicalAddress());
|
|
||||||
g_debug_context->recorder->MemoryAccessed(
|
|
||||||
texture_data, Pica::TexturingRegs::NibblesPerPixel(texture.format) *
|
|
||||||
texture.config.width / 2 * texture.config.height,
|
|
||||||
texture.config.GetPhysicalAddress());
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
DebugUtils::MemoryAccessTracker memory_accesses;
|
|
||||||
|
|
||||||
// Simple circular-replacement vertex cache
|
|
||||||
// The size has been tuned for optimal balance between hit-rate and the cost of lookup
|
|
||||||
const size_t VERTEX_CACHE_SIZE = 32;
|
|
||||||
std::array<u16, VERTEX_CACHE_SIZE> vertex_cache_ids;
|
|
||||||
std::array<Shader::AttributeBuffer, VERTEX_CACHE_SIZE> vertex_cache;
|
|
||||||
Shader::AttributeBuffer vs_output;
|
|
||||||
|
|
||||||
unsigned int vertex_cache_pos = 0;
|
|
||||||
vertex_cache_ids.fill(-1);
|
|
||||||
|
|
||||||
auto* shader_engine = Shader::GetEngine();
|
|
||||||
Shader::UnitState shader_unit;
|
|
||||||
|
|
||||||
shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
|
|
||||||
|
|
||||||
g_state.geometry_pipeline.Reconfigure();
|
|
||||||
g_state.geometry_pipeline.Setup(shader_engine);
|
|
||||||
if (g_state.geometry_pipeline.NeedIndexInput())
|
|
||||||
ASSERT(is_indexed);
|
|
||||||
|
|
||||||
for (unsigned int index = 0; index < regs.pipeline.num_vertices; ++index) {
|
|
||||||
// Indexed rendering doesn't use the start offset
|
|
||||||
unsigned int vertex =
|
|
||||||
is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index])
|
|
||||||
: (index + regs.pipeline.vertex_offset);
|
|
||||||
|
|
||||||
// -1 is a common special value used for primitive restart. Since it's unknown if
|
|
||||||
// the PICA supports it, and it would mess up the caching, guard against it here.
|
|
||||||
ASSERT(vertex != -1);
|
|
||||||
|
|
||||||
bool vertex_cache_hit = false;
|
|
||||||
|
|
||||||
if (is_indexed) {
|
|
||||||
if (g_state.geometry_pipeline.NeedIndexInput()) {
|
|
||||||
g_state.geometry_pipeline.SubmitIndex(vertex);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (g_debug_context && Pica::g_debug_context->recorder) {
|
|
||||||
int size = index_u16 ? 2 : 1;
|
|
||||||
memory_accesses.AddAccess(base_address + index_info.offset + size * index,
|
|
||||||
size);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (unsigned int i = 0; i < VERTEX_CACHE_SIZE; ++i) {
|
|
||||||
if (vertex == vertex_cache_ids[i]) {
|
|
||||||
vs_output = vertex_cache[i];
|
|
||||||
vertex_cache_hit = true;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!vertex_cache_hit) {
|
|
||||||
// Initialize data for the current vertex
|
|
||||||
Shader::AttributeBuffer input;
|
|
||||||
loader.LoadVertex(base_address, index, vertex, input, memory_accesses);
|
|
||||||
|
|
||||||
// Send to vertex shader
|
|
||||||
if (g_debug_context)
|
|
||||||
g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
|
|
||||||
(void*)&input);
|
|
||||||
shader_unit.LoadInput(regs.vs, input);
|
|
||||||
shader_engine->Run(g_state.vs, shader_unit);
|
|
||||||
shader_unit.WriteOutput(regs.vs, vs_output);
|
|
||||||
|
|
||||||
if (is_indexed) {
|
|
||||||
vertex_cache[vertex_cache_pos] = vs_output;
|
|
||||||
vertex_cache_ids[vertex_cache_pos] = vertex;
|
|
||||||
vertex_cache_pos = (vertex_cache_pos + 1) % VERTEX_CACHE_SIZE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// Send to geometry pipeline
|
|
||||||
g_state.geometry_pipeline.SubmitVertex(vs_output);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (auto& range : memory_accesses.ranges) {
|
|
||||||
g_debug_context->recorder->MemoryAccessed(Memory::GetPhysicalPointer(range.first),
|
|
||||||
range.second, range.first);
|
|
||||||
}
|
|
||||||
|
|
||||||
VideoCore::g_renderer->Rasterizer()->DrawTriangles();
|
|
||||||
if (g_debug_context) {
|
|
||||||
g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
|
|
||||||
}
|
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
|
||||||
|
|
||||||
case PICA_REG_INDEX(gs.bool_uniforms):
|
case PICA_REG_INDEX(gs.bool_uniforms):
|
||||||
WriteUniformBoolReg(g_state.gs, g_state.regs.gs.bool_uniforms.Value());
|
WriteUniformBoolReg(g_state.gs, g_state.regs.gs.bool_uniforms.Value());
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue