mirror of
https://github.com/PabloMK7/citra.git
synced 2024-11-24 08:24:18 +00:00
-converted tabs to spaces
-moved scratchpad memory out of MemArena
This commit is contained in:
bunnei
parent
81b61ee720
commit
e05be0145c
2 changed files with 144 additions and 148 deletions
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@ -33,74 +33,71 @@
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namespace Memory {
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u8* g_base = NULL; ///< The base pointer to the auto-mirrored arena.
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u8* g_base = NULL; ///< The base pointer to the auto-mirrored arena.
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MemArena g_arena; ///< The MemArena class
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MemArena g_arena; ///< The MemArena class
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u8* g_bootrom = NULL; ///< Bootrom memory (super secret code/data @ 0x8000) pointer
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u8* g_fcram = NULL; ///< Main memory (FCRAM) pointer
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u8* g_vram = NULL; ///< Video memory (VRAM) pointer
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u8* g_scratchpad = NULL; ///< [Hack] Seperate mem for stack space because I don't know where this goes
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u8* g_bootrom = NULL; ///< Bootrom physical memory
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u8* g_fcram = NULL; ///< Main memory (FCRAM) pointer
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u8* g_vram = NULL; ///< Video memory (VRAM) pointer
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u8* g_scratchpad = NULL; ///< Scratchpad memory - Used for main thread stack
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u8* g_physical_bootrom = NULL; ///< Bootrom physical memory (super secret code/data @ 0x8000)
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u8* g_uncached_bootrom = NULL;
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u8* g_physical_fcram = NULL; ///< Main physical memory (FCRAM)
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u8* g_physical_vram = NULL; ///< Video physical memory (VRAM)
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u8* g_physical_scratchpad = NULL; ///< Scratchpad memory used for main thread stack
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u8* g_physical_bootrom = NULL; ///< Bootrom physical memory
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u8* g_uncached_bootrom = NULL;
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u8* g_physical_fcram = NULL; ///< Main physical memory (FCRAM)
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u8* g_physical_vram = NULL; ///< Video physical memory (VRAM)
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u8* g_physical_scratchpad = NULL; ///< Scratchpad memory used for main thread stack
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// We don't declare the IO region in here since its handled by other means.
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static MemoryView g_views[] =
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{
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{&g_scratchpad, &g_physical_scratchpad, 0x00000000, MEM_SCRATCHPAD_SIZE, 0 },
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// {&g_bootrom, &g_physical_bootrom, 0x00000000, MEM_BOOTROM_SIZE, 0},
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// {NULL, &g_uncached_bootrom, 0x00010000, MEM_BOOTROM_SIZE, MV_MIRROR_PREVIOUS},
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// {NULL, NULL, 0x17E00000, MEM_MPCORE_PRIV_SIZE, 0},
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{&g_vram, &g_physical_vram, MEM_VRAM_VADDR, MEM_VRAM_SIZE, MV_IS_PRIMARY_RAM},
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// {NULL, NULL, 0x1FF00000, MEM_DSP_SIZE, 0},
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// {NULL, NULL, 0x1FF80000, MEM_AXI_WRAM_SIZE, 0},
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{&g_fcram, &g_physical_fcram, MEM_FCRAM_VADDR, MEM_FCRAM_SIZE, MV_IS_PRIMARY_RAM},
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static MemoryView g_views[] = {
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{ &g_vram, &g_physical_vram, MEM_VRAM_VADDR, MEM_VRAM_SIZE, 0 },
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{ &g_fcram, &g_physical_fcram, MEM_FCRAM_VADDR, MEM_FCRAM_SIZE, MV_IS_PRIMARY_RAM },
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};
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/*static MemoryView views[] =
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{
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{&m_pScratchPad, &m_pPhysicalScratchPad, 0x00010000, SCRATCHPAD_SIZE, 0},
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{NULL, &m_pUncachedScratchPad, 0x40010000, SCRATCHPAD_SIZE, MV_MIRROR_PREVIOUS},
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{&m_pVRAM, &m_pPhysicalVRAM, 0x04000000, 0x00800000, 0},
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{NULL, &m_pUncachedVRAM, 0x44000000, 0x00800000, MV_MIRROR_PREVIOUS},
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{&m_pRAM, &m_pPhysicalRAM, 0x08000000, g_MemorySize, MV_IS_PRIMARY_RAM}, // only from 0x08800000 is it usable (last 24 megs)
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{NULL, &m_pUncachedRAM, 0x48000000, g_MemorySize, MV_MIRROR_PREVIOUS | MV_IS_PRIMARY_RAM},
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{NULL, &m_pKernelRAM, 0x88000000, g_MemorySize, MV_MIRROR_PREVIOUS | MV_IS_PRIMARY_RAM},
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{&m_pScratchPad, &m_pPhysicalScratchPad, 0x00010000, SCRATCHPAD_SIZE, 0},
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{NULL, &m_pUncachedScratchPad, 0x40010000, SCRATCHPAD_SIZE, MV_MIRROR_PREVIOUS},
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{&m_pVRAM, &m_pPhysicalVRAM, 0x04000000, 0x00800000, 0},
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{NULL, &m_pUncachedVRAM, 0x44000000, 0x00800000, MV_MIRROR_PREVIOUS},
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{&m_pRAM, &m_pPhysicalRAM, 0x08000000, g_MemorySize, MV_IS_PRIMARY_RAM}, // only from 0x08800000 is it usable (last 24 megs)
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{NULL, &m_pUncachedRAM, 0x48000000, g_MemorySize, MV_MIRROR_PREVIOUS | MV_IS_PRIMARY_RAM},
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{NULL, &m_pKernelRAM, 0x88000000, g_MemorySize, MV_MIRROR_PREVIOUS | MV_IS_PRIMARY_RAM},
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// TODO: There are a few swizzled mirrors of VRAM, not sure about the best way to
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// implement those.
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// TODO: There are a few swizzled mirrors of VRAM, not sure about the best way to
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// implement those.
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};*/
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static const int kNumMemViews = sizeof(g_views) / sizeof(MemoryView); ///< Number of mem views
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static const int kNumMemViews = sizeof(g_views) / sizeof(MemoryView); ///< Number of mem views
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void Init() {
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int flags = 0;
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int flags = 0;
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for (size_t i = 0; i < ARRAY_SIZE(g_views); i++) {
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if (g_views[i].flags & MV_IS_PRIMARY_RAM)
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g_views[i].size = MEM_FCRAM_SIZE;
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}
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for (size_t i = 0; i < ARRAY_SIZE(g_views); i++) {
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if (g_views[i].flags & MV_IS_PRIMARY_RAM)
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g_views[i].size = MEM_FCRAM_SIZE;
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}
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g_base = MemoryMap_Setup(g_views, kNumMemViews, flags, &g_arena);
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g_base = MemoryMap_Setup(g_views, kNumMemViews, flags, &g_arena);
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NOTICE_LOG(MEMMAP, "Memory system initialized. RAM at %p (mirror at 0 @ %p)", g_fcram,
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g_physical_fcram);
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g_scratchpad = new u8[MEM_SCRATCHPAD_SIZE];
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NOTICE_LOG(MEMMAP, "Memory system initialized. RAM at %p (mirror at 0 @ %p)", g_fcram,
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g_physical_fcram);
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}
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void Shutdown() {
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u32 flags = 0;
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MemoryMap_Shutdown(g_views, kNumMemViews, flags, &g_arena);
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g_arena.ReleaseSpace();
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g_base = NULL;
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NOTICE_LOG(MEMMAP, "Memory system shut down.");
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u32 flags = 0;
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MemoryMap_Shutdown(g_views, kNumMemViews, flags, &g_arena);
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g_arena.ReleaseSpace();
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delete[] g_scratchpad;
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g_base = NULL;
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g_scratchpad = NULL;
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NOTICE_LOG(MEMMAP, "Memory system shut down.");
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}
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@ -29,157 +29,156 @@
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namespace Memory {
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template <typename T>
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inline void ReadFromHardware(T &var, const u32 addr)
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{
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// TODO: Figure out the fastest order of tests for both read and write (they are probably different).
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// TODO: Make sure this represents the mirrors in a correct way.
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inline void ReadFromHardware(T &var, const u32 addr) {
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// TODO: Figure out the fastest order of tests for both read and write (they are probably different).
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// TODO: Make sure this represents the mirrors in a correct way.
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// Could just do a base-relative read, too.... TODO
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// Could just do a base-relative read, too.... TODO
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if ((addr & 0x3E000000) == 0x08000000) {
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var = *((const T*)&g_fcram[addr & MEM_FCRAM_MASK]);
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if ((addr & 0x3E000000) == 0x08000000) {
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var = *((const T*)&g_fcram[addr & MEM_FCRAM_MASK]);
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// Scratchpad memory
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// Scratchpad memory
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} else if (addr > MEM_SCRATCHPAD_VADDR && addr <= (MEM_SCRATCHPAD_VADDR + MEM_SCRATCHPAD_SIZE)) {
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var = *((const T*)&g_scratchpad[addr & MEM_SCRATCHPAD_MASK]);
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}
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/*else if ((addr & 0x3F800000) == 0x04000000) {
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var = *((const T*)&m_pVRAM[addr & VRAM_MASK]);
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}*/
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else {
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_assert_msg_(MEMMAP, false, "unknown hardware read");
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// WARN_LOG(MEMMAP, "ReadFromHardware: Invalid addr %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
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}
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/*else if ((addr & 0x3F800000) == 0x04000000) {
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var = *((const T*)&m_pVRAM[addr & VRAM_MASK]);
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}*/
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else {
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_assert_msg_(MEMMAP, false, "unknown hardware read");
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// WARN_LOG(MEMMAP, "ReadFromHardware: Invalid addr %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
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}
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}
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template <typename T>
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inline void WriteToHardware(u32 addr, const T data) {
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NOTICE_LOG(MEMMAP, "Test1 %08X", addr);
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// ExeFS:/.code is loaded here:
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if ((addr & 0xFFF00000) == 0x00100000) {
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// TODO(ShizZy): This is dumb... handle correctly. From 3DBrew:
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// http://3dbrew.org/wiki/Memory_layout#ARM11_User-land_memory_regions
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// The ExeFS:/.code is loaded here, executables must be loaded to the 0x00100000 region when
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// the exheader "special memory" flag is clear. The 0x03F00000-byte size restriction only
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// applies when this flag is clear. Executables are usually loaded to 0x14000000 when the
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// exheader "special memory" flag is set, however this address can be arbitrary.
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*(T*)&g_fcram[addr & MEM_FCRAM_MASK] = data;
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NOTICE_LOG(MEMMAP, "Test2");
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NOTICE_LOG(MEMMAP, "Test1 %08X", addr);
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// ExeFS:/.code is loaded here:
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if ((addr & 0xFFF00000) == 0x00100000) {
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// TODO(ShizZy): This is dumb... handle correctly. From 3DBrew:
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// http://3dbrew.org/wiki/Memory_layout#ARM11_User-land_memory_regions
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// The ExeFS:/.code is loaded here, executables must be loaded to the 0x00100000 region when
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// the exheader "special memory" flag is clear. The 0x03F00000-byte size restriction only
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// applies when this flag is clear. Executables are usually loaded to 0x14000000 when the
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// exheader "special memory" flag is set, however this address can be arbitrary.
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*(T*)&g_fcram[addr & MEM_FCRAM_MASK] = data;
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NOTICE_LOG(MEMMAP, "Test2");
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// Scratchpad memory
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} else if (addr > MEM_SCRATCHPAD_VADDR && addr <= (MEM_SCRATCHPAD_VADDR + MEM_SCRATCHPAD_SIZE)) {
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*(T*)&g_scratchpad[addr & MEM_SCRATCHPAD_MASK] = data;
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// Heap mapped by ControlMemory:
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} else if ((addr & 0x3E000000) == 0x08000000) {
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// TODO(ShizZy): Writes to this virtual address should be put in physical memory at FCRAM + GSP
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// heap size... the following is writing to FCRAM + 0, which is actually supposed to be the
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// application's GSP heap
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*(T*)&g_fcram[addr & MEM_FCRAM_MASK] = data;
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} else if ((addr & 0xFF000000) == 0x14000000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to GSP heap");
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} else if ((addr & 0xFFF00000) == 0x1EC00000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to IO registers");
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} else if ((addr & 0xFF000000) == 0x1F000000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to VRAM");
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} else if ((addr & 0xFFF00000) == 0x1FF00000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to DSP memory");
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} else if ((addr & 0xFFFF0000) == 0x1FF80000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory");
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} else if ((addr & 0xFFFFF000) == 0x1FF81000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to shared page");
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} else {
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_assert_msg_(MEMMAP, false, "unknown hardware write");
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}
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// Heap mapped by ControlMemory:
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} else if ((addr & 0x3E000000) == 0x08000000) {
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// TODO(ShizZy): Writes to this virtual address should be put in physical memory at FCRAM + GSP
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// heap size... the following is writing to FCRAM + 0, which is actually supposed to be the
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// application's GSP heap
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*(T*)&g_fcram[addr & MEM_FCRAM_MASK] = data;
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} else if ((addr & 0xFF000000) == 0x14000000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to GSP heap");
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} else if ((addr & 0xFFF00000) == 0x1EC00000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to IO registers");
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} else if ((addr & 0xFF000000) == 0x1F000000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to VRAM");
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} else if ((addr & 0xFFF00000) == 0x1FF00000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to DSP memory");
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} else if ((addr & 0xFFFF0000) == 0x1FF80000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory");
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} else if ((addr & 0xFFFFF000) == 0x1FF81000) {
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_assert_msg_(MEMMAP, false, "umimplemented write to shared page");
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} else {
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_assert_msg_(MEMMAP, false, "unknown hardware write");
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}
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}
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bool IsValidAddress(const u32 addr) {
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if ((addr & 0x3E000000) == 0x08000000) {
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return true;
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} else if ((addr & 0x3F800000) == 0x04000000) {
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return true;
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} else if ((addr & 0xBFFF0000) == 0x00010000) {
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return true;
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} else if ((addr & 0x3F000000) >= 0x08000000 && (addr & 0x3F000000) < 0x08000000 + MEM_FCRAM_MASK) {
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return true;
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} else {
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return false;
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}
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if ((addr & 0x3E000000) == 0x08000000) {
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return true;
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} else if ((addr & 0x3F800000) == 0x04000000) {
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return true;
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} else if ((addr & 0xBFFF0000) == 0x00010000) {
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return true;
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} else if ((addr & 0x3F000000) >= 0x08000000 && (addr & 0x3F000000) < 0x08000000 + MEM_FCRAM_MASK) {
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return true;
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} else {
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return false;
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}
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}
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u8 *GetPointer(const u32 addr) {
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// TODO(bunnei): Just a stub for now... ImplementMe!
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if ((addr & 0x3E000000) == 0x08000000) {
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return g_fcram + (addr & MEM_FCRAM_MASK);
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}
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//else if ((addr & 0x3F800000) == 0x04000000) {
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// return g_vram + (addr & MEM_VRAM_MASK);
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//}
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//else if ((addr & 0x3F000000) >= 0x08000000 && (addr & 0x3F000000) < 0x08000000 + g_MemorySize) {
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// return m_pRAM + (addr & g_MemoryMask);
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//}
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else {
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//ERROR_LOG(MEMMAP, "Unknown GetPointer %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
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ERROR_LOG(MEMMAP, "Unknown GetPointer %08x", addr);
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static bool reported = false;
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//if (!reported) {
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// Reporting::ReportMessage("Unknown GetPointer %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
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// reported = true;
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//}
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//if (!g_Config.bIgnoreBadMemAccess) {
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// Core_EnableStepping(true);
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// host->SetDebugMode(true);
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//}
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return 0;
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}
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// TODO(bunnei): Just a stub for now... ImplementMe!
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if ((addr & 0x3E000000) == 0x08000000) {
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return g_fcram + (addr & MEM_FCRAM_MASK);
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}
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//else if ((addr & 0x3F800000) == 0x04000000) {
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// return g_vram + (addr & MEM_VRAM_MASK);
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//}
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//else if ((addr & 0x3F000000) >= 0x08000000 && (addr & 0x3F000000) < 0x08000000 + g_MemorySize) {
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// return m_pRAM + (addr & g_MemoryMask);
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//}
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else {
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//ERROR_LOG(MEMMAP, "Unknown GetPointer %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
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ERROR_LOG(MEMMAP, "Unknown GetPointer %08x", addr);
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static bool reported = false;
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//if (!reported) {
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// Reporting::ReportMessage("Unknown GetPointer %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
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// reported = true;
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//}
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//if (!g_Config.bIgnoreBadMemAccess) {
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// Core_EnableStepping(true);
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// host->SetDebugMode(true);
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//}
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return 0;
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}
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}
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u8 Read8(const u32 addr) {
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u8 _var = 0;
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ReadFromHardware<u8>(_var, addr);
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return (u8)_var;
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u8 _var = 0;
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ReadFromHardware<u8>(_var, addr);
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return (u8)_var;
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}
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u16 Read16(const u32 addr) {
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u16_le _var = 0;
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ReadFromHardware<u16_le>(_var, addr);
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return (u16)_var;
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u16_le _var = 0;
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ReadFromHardware<u16_le>(_var, addr);
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return (u16)_var;
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}
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u32 Read32(const u32 addr) {
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u32_le _var = 0;
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ReadFromHardware<u32_le>(_var, addr);
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return _var;
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u32_le _var = 0;
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ReadFromHardware<u32_le>(_var, addr);
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return _var;
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}
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u64 Read64(const u32 addr) {
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u64_le _var = 0;
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ReadFromHardware<u64_le>(_var, addr);
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return _var;
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u64_le _var = 0;
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ReadFromHardware<u64_le>(_var, addr);
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return _var;
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}
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u32 Read8_ZX(const u32 addr) {
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return (u32)Read8(addr);
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return (u32)Read8(addr);
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}
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u32 Read16_ZX(const u32 addr) {
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return (u32)Read16(addr);
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return (u32)Read16(addr);
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}
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void Write8(const u32 addr, const u8 data) {
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WriteToHardware<u8>(addr, data);
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WriteToHardware<u8>(addr, data);
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}
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void Write16(const u32 addr, const u16 data) {
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WriteToHardware<u16_le>(addr, data);
|
||||
WriteToHardware<u16_le>(addr, data);
|
||||
}
|
||||
|
||||
void Write32(const u32 addr, const u32 data) {
|
||||
WriteToHardware<u32_le>(addr, data);
|
||||
WriteToHardware<u32_le>(addr, data);
|
||||
}
|
||||
|
||||
void Write64(const u32 addr, const u64 data) {
|
||||
WriteToHardware<u64_le>(addr, data);
|
||||
WriteToHardware<u64_le>(addr, data);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
|
|
|||
Loading…
Reference in a new issue