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citra/src/core/arm
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mailwl 2efc1c9348 Fix BLX LR opcode interpretation
2016-04-09 19:11:02 +03:00
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disassembler ARM_Disasm::DisassembleMemHalf: actually use width in determining opcode name 2016-01-19 18:42:16 +01:00
dyncom Fix BLX LR opcode interpretation 2016-04-09 19:11:02 +03:00
skyeye_common armstate: Correct FIQ register banking 2016-03-21 18:56:27 -04:00
arm_interface.h arm_interface: Make GetNumInstructions const 2015-12-06 15:07:59 -05:00