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https://github.com/PabloMK7/citra.git
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260 lines
8.6 KiB
C++
260 lines
8.6 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <cstddef>
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#include <string>
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#include <vector>
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#include "common/common_types.h"
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#include "core/mmio.h"
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namespace Kernel {
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class Process;
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}
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namespace Memory {
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// Are defined in a system header
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#undef PAGE_SIZE
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#undef PAGE_MASK
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/**
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* Page size used by the ARM architecture. This is the smallest granularity with which memory can
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* be mapped.
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*/
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const u32 PAGE_SIZE = 0x1000;
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const u32 PAGE_MASK = PAGE_SIZE - 1;
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const int PAGE_BITS = 12;
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const std::size_t PAGE_TABLE_NUM_ENTRIES = 1 << (32 - PAGE_BITS);
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enum class PageType {
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/// Page is unmapped and should cause an access error.
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Unmapped,
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/// Page is mapped to regular memory. This is the only type you can get pointers to.
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Memory,
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/// Page is mapped to regular memory, but also needs to check for rasterizer cache flushing and
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/// invalidation
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RasterizerCachedMemory,
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/// Page is mapped to a I/O region. Writing and reading to this page is handled by functions.
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Special,
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};
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struct SpecialRegion {
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VAddr base;
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u32 size;
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MMIORegionPointer handler;
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};
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/**
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* A (reasonably) fast way of allowing switchable and remappable process address spaces. It loosely
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* mimics the way a real CPU page table works, but instead is optimized for minimal decoding and
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* fetching requirements when accessing. In the usual case of an access to regular memory, it only
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* requires an indexed fetch and a check for NULL.
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*/
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struct PageTable {
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/**
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* Array of memory pointers backing each page. An entry can only be non-null if the
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* corresponding entry in the `attributes` array is of type `Memory`.
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*/
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std::array<u8*, PAGE_TABLE_NUM_ENTRIES> pointers;
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/**
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* Contains MMIO handlers that back memory regions whose entries in the `attribute` array is of
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* type `Special`.
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*/
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std::vector<SpecialRegion> special_regions;
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/**
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* Array of fine grained page attributes. If it is set to any value other than `Memory`, then
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* the corresponding entry in `pointers` MUST be set to null.
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*/
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std::array<PageType, PAGE_TABLE_NUM_ENTRIES> attributes;
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};
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/// Physical memory regions as seen from the ARM11
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enum : PAddr {
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/// IO register area
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IO_AREA_PADDR = 0x10100000,
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IO_AREA_SIZE = 0x00400000, ///< IO area size (4MB)
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IO_AREA_PADDR_END = IO_AREA_PADDR + IO_AREA_SIZE,
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/// MPCore internal memory region
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MPCORE_RAM_PADDR = 0x17E00000,
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MPCORE_RAM_SIZE = 0x00002000, ///< MPCore internal memory size (8KB)
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MPCORE_RAM_PADDR_END = MPCORE_RAM_PADDR + MPCORE_RAM_SIZE,
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/// Video memory
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VRAM_PADDR = 0x18000000,
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VRAM_SIZE = 0x00600000, ///< VRAM size (6MB)
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VRAM_PADDR_END = VRAM_PADDR + VRAM_SIZE,
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/// New 3DS additional memory. Supposedly faster than regular FCRAM. Part of it can be used by
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/// applications and system modules if mapped via the ExHeader.
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N3DS_EXTRA_RAM_PADDR = 0x1F000000,
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N3DS_EXTRA_RAM_SIZE = 0x00400000, ///< New 3DS additional memory size (4MB)
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N3DS_EXTRA_RAM_PADDR_END = N3DS_EXTRA_RAM_PADDR + N3DS_EXTRA_RAM_SIZE,
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/// DSP memory
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DSP_RAM_PADDR = 0x1FF00000,
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DSP_RAM_SIZE = 0x00080000, ///< DSP memory size (512KB)
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DSP_RAM_PADDR_END = DSP_RAM_PADDR + DSP_RAM_SIZE,
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/// AXI WRAM
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AXI_WRAM_PADDR = 0x1FF80000,
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AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size (512KB)
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AXI_WRAM_PADDR_END = AXI_WRAM_PADDR + AXI_WRAM_SIZE,
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/// Main FCRAM
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FCRAM_PADDR = 0x20000000,
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FCRAM_SIZE = 0x08000000, ///< FCRAM size on the Old 3DS (128MB)
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FCRAM_N3DS_SIZE = 0x10000000, ///< FCRAM size on the New 3DS (256MB)
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FCRAM_PADDR_END = FCRAM_PADDR + FCRAM_SIZE,
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FCRAM_N3DS_PADDR_END = FCRAM_PADDR + FCRAM_N3DS_SIZE,
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};
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/// Virtual user-space memory regions
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enum : VAddr {
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/// Where the application text, data and bss reside.
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PROCESS_IMAGE_VADDR = 0x00100000,
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PROCESS_IMAGE_MAX_SIZE = 0x03F00000,
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PROCESS_IMAGE_VADDR_END = PROCESS_IMAGE_VADDR + PROCESS_IMAGE_MAX_SIZE,
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/// Area where IPC buffers are mapped onto.
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IPC_MAPPING_VADDR = 0x04000000,
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IPC_MAPPING_SIZE = 0x04000000,
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IPC_MAPPING_VADDR_END = IPC_MAPPING_VADDR + IPC_MAPPING_SIZE,
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/// Application heap (includes stack).
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HEAP_VADDR = 0x08000000,
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HEAP_SIZE = 0x08000000,
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HEAP_VADDR_END = HEAP_VADDR + HEAP_SIZE,
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/// Area where shared memory buffers are mapped onto.
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SHARED_MEMORY_VADDR = 0x10000000,
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SHARED_MEMORY_SIZE = 0x04000000,
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SHARED_MEMORY_VADDR_END = SHARED_MEMORY_VADDR + SHARED_MEMORY_SIZE,
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/// Maps 1:1 to an offset in FCRAM. Used for HW allocations that need to be linear in physical
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/// memory.
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LINEAR_HEAP_VADDR = 0x14000000,
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LINEAR_HEAP_SIZE = 0x08000000,
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LINEAR_HEAP_VADDR_END = LINEAR_HEAP_VADDR + LINEAR_HEAP_SIZE,
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/// Maps 1:1 to New 3DS additional memory
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N3DS_EXTRA_RAM_VADDR = 0x1E800000,
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N3DS_EXTRA_RAM_VADDR_END = N3DS_EXTRA_RAM_VADDR + N3DS_EXTRA_RAM_SIZE,
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/// Maps 1:1 to the IO register area.
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IO_AREA_VADDR = 0x1EC00000,
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IO_AREA_VADDR_END = IO_AREA_VADDR + IO_AREA_SIZE,
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/// Maps 1:1 to VRAM.
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VRAM_VADDR = 0x1F000000,
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VRAM_VADDR_END = VRAM_VADDR + VRAM_SIZE,
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/// Maps 1:1 to DSP memory.
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DSP_RAM_VADDR = 0x1FF00000,
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DSP_RAM_VADDR_END = DSP_RAM_VADDR + DSP_RAM_SIZE,
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/// Read-only page containing kernel and system configuration values.
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CONFIG_MEMORY_VADDR = 0x1FF80000,
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CONFIG_MEMORY_SIZE = 0x00001000,
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CONFIG_MEMORY_VADDR_END = CONFIG_MEMORY_VADDR + CONFIG_MEMORY_SIZE,
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/// Usually read-only page containing mostly values read from hardware.
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SHARED_PAGE_VADDR = 0x1FF81000,
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SHARED_PAGE_SIZE = 0x00001000,
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SHARED_PAGE_VADDR_END = SHARED_PAGE_VADDR + SHARED_PAGE_SIZE,
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/// Area where TLS (Thread-Local Storage) buffers are allocated.
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TLS_AREA_VADDR = 0x1FF82000,
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TLS_ENTRY_SIZE = 0x200,
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/// Equivalent to LINEAR_HEAP_VADDR, but expanded to cover the extra memory in the New 3DS.
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NEW_LINEAR_HEAP_VADDR = 0x30000000,
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NEW_LINEAR_HEAP_SIZE = 0x10000000,
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NEW_LINEAR_HEAP_VADDR_END = NEW_LINEAR_HEAP_VADDR + NEW_LINEAR_HEAP_SIZE,
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};
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extern std::array<u8, Memory::FCRAM_N3DS_SIZE> fcram;
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/// Determines if the given VAddr is valid for the specified process.
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bool IsValidVirtualAddress(const Kernel::Process& process, VAddr vaddr);
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bool IsValidPhysicalAddress(PAddr paddr);
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u8 Read8(VAddr addr);
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u16 Read16(VAddr addr);
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u32 Read32(VAddr addr);
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u64 Read64(VAddr addr);
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void Write8(VAddr addr, u8 data);
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void Write16(VAddr addr, u16 data);
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void Write32(VAddr addr, u32 data);
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void Write64(VAddr addr, u64 data);
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void ReadBlock(const Kernel::Process& process, VAddr src_addr, void* dest_buffer, std::size_t size);
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void WriteBlock(const Kernel::Process& process, VAddr dest_addr, const void* src_buffer,
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std::size_t size);
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void ZeroBlock(const Kernel::Process& process, VAddr dest_addr, const std::size_t size);
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void CopyBlock(const Kernel::Process& process, VAddr dest_addr, VAddr src_addr, std::size_t size);
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void CopyBlock(const Kernel::Process& src_process, const Kernel::Process& dest_process,
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VAddr src_addr, VAddr dest_addr, std::size_t size);
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u8* GetPointer(VAddr vaddr);
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std::string ReadCString(VAddr vaddr, std::size_t max_length);
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/**
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* Gets a pointer to the memory region beginning at the specified physical address.
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*/
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u8* GetPhysicalPointer(PAddr address);
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/**
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* Mark each page touching the region as cached.
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*/
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void RasterizerMarkRegionCached(PAddr start, u32 size, bool cached);
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/**
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* Flushes any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerFlushRegion(PAddr start, u32 size);
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/**
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* Invalidates any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerInvalidateRegion(PAddr start, u32 size);
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/**
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* Flushes and invalidates any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerFlushAndInvalidateRegion(PAddr start, u32 size);
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enum class FlushMode {
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/// Write back modified surfaces to RAM
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Flush,
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/// Remove region from the cache
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Invalidate,
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/// Write back modified surfaces to RAM, and also remove them from the cache
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FlushAndInvalidate,
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};
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/**
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* Flushes and invalidates any externally cached rasterizer resources touching the given virtual
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* address region.
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*/
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void RasterizerFlushVirtualRegion(VAddr start, u32 size, FlushMode mode);
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class MemorySystem {
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public:
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/// Currently active page table
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void SetCurrentPageTable(PageTable* page_table);
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PageTable* GetCurrentPageTable();
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/// Gets offset in FCRAM from a pointer inside FCRAM range
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u32 GetFCRAMOffset(u8* pointer);
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};
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} // namespace Memory
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