embassy/embassy-stm32/src/gpio.rs

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#![macro_use]
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use core::convert::Infallible;
use core::marker::PhantomData;
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use embassy::util::Unborrow;
use embassy_hal_common::{unborrow, unsafe_impl_unborrow};
use embedded_hal::digital::v2::{toggleable, InputPin, OutputPin, StatefulOutputPin};
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use crate::pac;
use crate::pac::gpio::{self, vals};
use crate::peripherals;
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/// Pull setting for an input.
#[derive(Debug, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Pull {
None,
Up,
Down,
}
#[cfg(gpio_v2)]
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impl From<Pull> for vals::Pupdr {
fn from(pull: Pull) -> Self {
use Pull::*;
match pull {
None => vals::Pupdr::FLOATING,
Up => vals::Pupdr::PULLUP,
Down => vals::Pupdr::PULLDOWN,
}
}
}
/// Speed settings
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Speed {
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Low,
Medium,
#[cfg(not(any(syscfg_f0, gpio_v1)))]
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High,
VeryHigh,
}
#[cfg(gpio_v1)]
impl From<Speed> for vals::Mode {
fn from(speed: Speed) -> Self {
use Speed::*;
match speed {
Low => vals::Mode::OUTPUT2,
Medium => vals::Mode::OUTPUT,
VeryHigh => vals::Mode::OUTPUT50,
}
}
}
#[cfg(gpio_v2)]
impl From<Speed> for vals::Ospeedr {
fn from(speed: Speed) -> Self {
use Speed::*;
match speed {
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Low => vals::Ospeedr::LOWSPEED,
Medium => vals::Ospeedr::MEDIUMSPEED,
#[cfg(not(syscfg_f0))]
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High => vals::Ospeedr::HIGHSPEED,
VeryHigh => vals::Ospeedr::VERYHIGHSPEED,
}
}
}
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/// GPIO input driver.
pub struct Input<'d, T: Pin> {
pub(crate) pin: T,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Pin> Input<'d, T> {
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pub fn new(pin: impl Unborrow<Target = T> + 'd, pull: Pull) -> Self {
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unborrow!(pin);
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cortex_m::interrupt::free(|_| unsafe {
let r = pin.block();
let n = pin.pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
match pull {
Pull::Up => r.bsrr().write(|w| w.set_bs(n, true)),
Pull::Down => r.bsrr().write(|w| w.set_br(n, true)),
Pull::None => {}
}
if pull == Pull::None {
r.cr(crlh)
.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
} else {
r.cr(crlh)
.modify(|w| w.set_cnf(n % 8, vals::Cnf::ALTPUSHPULL));
}
r.cr(crlh).modify(|w| w.set_mode(n % 8, vals::Mode::INPUT));
}
#[cfg(gpio_v2)]
{
r.pupdr().modify(|w| w.set_pupdr(n, pull.into()));
r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
}
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});
Self {
pin,
phantom: PhantomData,
}
}
}
impl<'d, T: Pin> Drop for Input<'d, T> {
fn drop(&mut self) {
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cortex_m::interrupt::free(|_| unsafe {
let r = self.pin.block();
let n = self.pin.pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
r.cr(crlh)
.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
}
#[cfg(gpio_v2)]
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r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
});
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}
}
impl<'d, T: Pin> InputPin for Input<'d, T> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
self.is_low().map(|v| !v)
}
fn is_low(&self) -> Result<bool, Self::Error> {
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let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as _) };
Ok(state == vals::Idr::LOW)
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}
}
/// Digital input or output level.
#[derive(Debug, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Level {
Low,
High,
}
/// GPIO output driver.
pub struct Output<'d, T: Pin> {
pub(crate) pin: T,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Pin> Output<'d, T> {
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pub fn new(pin: impl Unborrow<Target = T> + 'd, initial_output: Level, speed: Speed) -> Self {
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unborrow!(pin);
match initial_output {
Level::High => pin.set_high(),
Level::Low => pin.set_low(),
}
cortex_m::interrupt::free(|_| unsafe {
let r = pin.block();
let n = pin.pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
r.cr(crlh).modify(|w| w.set_cnf(n % 8, vals::Cnf::PUSHPULL));
r.cr(crlh).modify(|w| w.set_mode(n % 8, speed.into()));
}
#[cfg(gpio_v2)]
{
r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
pin.set_speed(speed);
r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
}
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});
Self {
pin,
phantom: PhantomData,
}
}
}
impl<'d, T: Pin> Drop for Output<'d, T> {
fn drop(&mut self) {
cortex_m::interrupt::free(|_| unsafe {
let r = self.pin.block();
let n = self.pin.pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
r.cr(crlh)
.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
r.cr(crlh).modify(|w| w.set_mode(n % 8, vals::Mode::INPUT));
}
#[cfg(gpio_v2)]
{
r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
}
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});
}
}
impl<'d, T: Pin> OutputPin for Output<'d, T> {
type Error = Infallible;
/// Set the output as high.
fn set_high(&mut self) -> Result<(), Self::Error> {
self.pin.set_high();
Ok(())
}
/// Set the output as low.
fn set_low(&mut self) -> Result<(), Self::Error> {
self.pin.set_low();
Ok(())
}
}
impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
/// Is the output pin set as high?
fn is_set_high(&self) -> Result<bool, Self::Error> {
self.is_set_low().map(|v| !v)
}
/// Is the output pin set as low?
fn is_set_low(&self) -> Result<bool, Self::Error> {
let state = unsafe { self.pin.block().odr().read().odr(self.pin.pin() as _) };
Ok(state == vals::Odr::LOW)
}
}
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impl<'d, T: Pin> toggleable::Default for Output<'d, T> {}
/// GPIO output open-drain driver.
pub struct OutputOpenDrain<'d, T: Pin> {
pub(crate) pin: T,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Pin> OutputOpenDrain<'d, T> {
pub fn new(
pin: impl Unborrow<Target = T> + 'd,
initial_output: Level,
speed: Speed,
pull: Pull,
) -> Self {
unborrow!(pin);
match initial_output {
Level::High => pin.set_high(),
Level::Low => pin.set_low(),
}
cortex_m::interrupt::free(|_| unsafe {
let r = pin.block();
let n = pin.pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
match pull {
Pull::Up => r.bsrr().write(|w| w.set_bs(n, true)),
Pull::Down => r.bsrr().write(|w| w.set_br(n, true)),
Pull::None => {}
}
r.cr(crlh).modify(|w| w.set_mode(n % 8, speed.into()));
r.cr(crlh)
.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
}
#[cfg(gpio_v2)]
{
r.pupdr().modify(|w| w.set_pupdr(n, pull.into()));
r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPENDRAIN));
pin.set_speed(speed);
r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
}
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});
Self {
pin,
phantom: PhantomData,
}
}
}
impl<'d, T: Pin> Drop for OutputOpenDrain<'d, T> {
fn drop(&mut self) {
cortex_m::interrupt::free(|_| unsafe {
let r = self.pin.block();
let n = self.pin.pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if n < 8 { 0 } else { 1 };
r.cr(crlh)
.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
r.cr(crlh).modify(|w| w.set_mode(n % 8, vals::Mode::INPUT));
}
#[cfg(gpio_v2)]
{
r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
}
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});
}
}
impl<'d, T: Pin> OutputPin for OutputOpenDrain<'d, T> {
type Error = Infallible;
/// Set the output as high.
fn set_high(&mut self) -> Result<(), Self::Error> {
self.pin.set_high();
Ok(())
}
/// Set the output as low.
fn set_low(&mut self) -> Result<(), Self::Error> {
self.pin.set_low();
Ok(())
}
}
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impl<'d, T: Pin> InputPin for OutputOpenDrain<'d, T> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
}
fn is_low(&self) -> Result<bool, Self::Error> {
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// NOTE(safety) Atomic read
let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as usize) };
Ok(state == vals::Idr::LOW)
}
}
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pub(crate) mod sealed {
use super::*;
/// Alternate function type settings
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum AFType {
// InputFloating,
// InputPullUp,
// InputPullDown,
OutputPushPull,
OutputOpenDrain,
}
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pub trait Pin {
fn pin_port(&self) -> u8;
#[inline]
fn _pin(&self) -> u8 {
self.pin_port() % 16
}
#[inline]
fn _port(&self) -> u8 {
self.pin_port() / 16
}
#[inline]
fn block(&self) -> gpio::Gpio {
pac::GPIO(self._port() as _)
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}
/// Set the output as high.
#[inline]
fn set_high(&self) {
unsafe {
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let n = self._pin() as _;
self.block().bsrr().write(|w| w.set_bs(n, true));
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}
}
/// Set the output as low.
#[inline]
fn set_low(&self) {
unsafe {
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let n = self._pin() as _;
self.block().bsrr().write(|w| w.set_br(n, true));
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}
}
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#[cfg(gpio_v1)]
unsafe fn set_as_af(&self, _af_num: u8, af_type: AFType) {
// F1 uses the AFIO register for remapping.
// For now, this is not implemented, so af_num is ignored
// _af_num should be zero here, since it is not set by stm32-data
let r = self.block();
let n = self._pin() as usize;
let crlh = if n < 8 { 0 } else { 1 };
match af_type {
// TODO: Do we need to configure input AF pins differently?
AFType::OutputPushPull => {
r.cr(crlh).modify(|w| {
w.set_mode(n % 8, vals::Mode::OUTPUT50);
w.set_cnf(n % 8, vals::Cnf::ALTPUSHPULL);
});
}
AFType::OutputOpenDrain => {
r.cr(crlh).modify(|w| {
w.set_mode(n % 8, vals::Mode::OUTPUT50);
w.set_cnf(n % 8, vals::Cnf::ALTOPENDRAIN);
});
}
}
}
#[cfg(gpio_v2)]
unsafe fn set_as_af(&self, af_num: u8, af_type: AFType) {
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let pin = self._pin() as usize;
let block = self.block();
block
.afr(pin / 8)
.modify(|w| w.set_afr(pin % 8, vals::Afr(af_num)));
match af_type {
AFType::OutputPushPull => {
block.otyper().modify(|w| w.set_ot(pin, vals::Ot::PUSHPULL))
}
AFType::OutputOpenDrain => block
.otyper()
.modify(|w| w.set_ot(pin, vals::Ot::OPENDRAIN)),
}
block
.pupdr()
.modify(|w| w.set_pupdr(pin, vals::Pupdr::FLOATING));
block
.moder()
.modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE));
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}
unsafe fn set_as_analog(&self) {
let pin = self._pin() as usize;
let block = self.block();
#[cfg(gpio_v1)]
{
let crlh = if pin < 8 { 0 } else { 1 };
block
.cr(crlh)
.modify(|w| w.set_cnf(pin % 8, vals::Cnf::PUSHPULL));
block
.cr(crlh)
.modify(|w| w.set_mode(pin % 8, vals::Mode::INPUT));
}
#[cfg(gpio_v2)]
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block
.moder()
.modify(|w| w.set_moder(pin, vals::Moder::ANALOG));
}
#[cfg(gpio_v2)]
unsafe fn set_speed(&self, speed: Speed) {
let pin = self._pin() as usize;
self.block()
.ospeedr()
.modify(|w| w.set_ospeedr(pin, speed.into()));
}
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}
pub trait OptionalPin {}
}
pub trait Pin: sealed::Pin + Sized {
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type ExtiChannel: crate::exti::Channel;
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/// Number of the pin within the port (0..31)
#[inline]
fn pin(&self) -> u8 {
self._pin()
}
/// Port of the pin
#[inline]
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fn port(&self) -> u8 {
self._port()
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}
/// Convert from concrete pin type PX_XX to type erased `AnyPin`.
#[inline]
fn degrade(self) -> AnyPin {
AnyPin {
pin_port: self.pin_port(),
}
}
}
// Type-erased GPIO pin
pub struct AnyPin {
pin_port: u8,
}
impl AnyPin {
#[inline]
pub unsafe fn steal(pin_port: u8) -> Self {
Self { pin_port }
}
#[inline]
fn _port(&self) -> u8 {
self.pin_port / 16
}
#[inline]
pub fn block(&self) -> gpio::Gpio {
pac::GPIO(self._port() as _)
}
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}
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unsafe_impl_unborrow!(AnyPin);
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impl Pin for AnyPin {
type ExtiChannel = crate::exti::AnyChannel;
}
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impl sealed::Pin for AnyPin {
#[inline]
fn pin_port(&self) -> u8 {
self.pin_port
}
}
// ====================
pub trait OptionalPin: sealed::OptionalPin + Sized {
type Pin: Pin;
fn pin(&self) -> Option<&Self::Pin>;
fn pin_mut(&mut self) -> Option<&mut Self::Pin>;
/// Convert from concrete pin type PX_XX to type erased `Option<AnyPin>`.
#[inline]
fn degrade_optional(mut self) -> Option<AnyPin> {
self.pin_mut()
.map(|pin| unsafe { core::ptr::read(pin) }.degrade())
}
}
impl<T: Pin> sealed::OptionalPin for T {}
impl<T: Pin> OptionalPin for T {
type Pin = T;
#[inline]
fn pin(&self) -> Option<&T> {
Some(self)
}
#[inline]
fn pin_mut(&mut self) -> Option<&mut T> {
Some(self)
}
}
#[derive(Clone, Copy, Debug)]
pub struct NoPin;
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unsafe_impl_unborrow!(NoPin);
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impl sealed::OptionalPin for NoPin {}
impl OptionalPin for NoPin {
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type Pin = AnyPin;
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#[inline]
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fn pin(&self) -> Option<&AnyPin> {
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None
}
#[inline]
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fn pin_mut(&mut self) -> Option<&mut AnyPin> {
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None
}
}
// ====================
crate::pac::pins!(
($pin_name:ident, $port_name:ident, $port_num:expr, $pin_num:expr, $exti_ch:ident) => {
impl Pin for peripherals::$pin_name {
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type ExtiChannel = peripherals::$exti_ch;
}
impl sealed::Pin for peripherals::$pin_name {
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#[inline]
fn pin_port(&self) -> u8 {
$port_num * 16 + $pin_num
}
}
};
);
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pub(crate) unsafe fn init() {
crate::pac::gpio_rcc! {
($en_reg:ident) => {
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crate::pac::RCC.$en_reg().modify(|reg| {
crate::pac::gpio_rcc! {
($name:ident, $clock:ident, $en_reg, $rst_reg:ident, $en_fn:ident, $rst_fn:ident) => {
reg.$en_fn(true);
};
}
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});
};
}
}