2022-08-19 11:51:42 +02:00
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use core::marker::PhantomData;
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use embassy_hal_common::into_ref;
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use pac::i2c;
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use crate::{pac, peripherals, Peripheral};
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/// I2C error
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// I2C abort with error
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Abort(u32),
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/// User passed in a read buffer that was 0 length
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InvalidReadBufferLength,
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/// User passed in a write buffer that was 0 length
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InvalidWriteBufferLength,
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/// Target i2c address is out of range
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AddressOutOfRange(u16),
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/// Target i2c address is reserved
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AddressReserved(u16),
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}
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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pub struct Config {
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pub frequency: u32,
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pub sda_pullup: bool,
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pub scl_pullup: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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frequency: 100_000,
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sda_pullup: false,
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scl_pullup: false,
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}
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}
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}
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2022-08-19 14:15:43 +02:00
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const TX_FIFO_SIZE: u8 = 16;
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const RX_FIFO_SIZE: u8 = 16;
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2022-08-19 11:51:42 +02:00
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pub struct I2c<'d, T: Instance, M: Mode> {
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phantom: PhantomData<(&'d mut T, M)>,
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}
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2022-08-19 14:15:43 +02:00
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impl<'d, T: Instance> I2c<'d, T, Blocking> {
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pub fn new_blocking(
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2022-08-19 11:51:42 +02:00
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(_peri, scl, sda);
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assert!(config.frequency <= 1_000_000);
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assert!(config.frequency > 0);
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let p = T::regs();
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unsafe {
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p.ic_enable().write(|w| w.set_enable(false));
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2022-08-19 14:15:43 +02:00
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// Select controller mode & speed
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2022-08-19 11:51:42 +02:00
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p.ic_con().write(|w| {
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2022-08-19 14:15:43 +02:00
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// Always use "fast" mode (<= 400 kHz, works fine for standard
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// mode too)
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2022-08-19 11:51:42 +02:00
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w.set_speed(i2c::vals::Speed::FAST);
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w.set_master_mode(true);
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w.set_ic_slave_disable(true);
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w.set_ic_restart_en(true);
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w.set_tx_empty_ctrl(true);
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});
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2022-08-19 14:15:43 +02:00
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// by a register value of 0.
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2022-08-19 11:51:42 +02:00
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p.ic_tx_tl().write(|w| w.set_tx_tl(0));
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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// Configure SCL & SDA pins
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scl.io().ctrl().write(|w| w.set_funcsel(3));
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sda.io().ctrl().write(|w| w.set_funcsel(3));
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scl.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_pue(config.scl_pullup);
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});
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sda.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_pue(config.sda_pullup);
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});
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// Configure baudrate
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2022-08-19 14:15:43 +02:00
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// There are some subtleties to I2C timing which we are completely
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// ignoring here See:
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// https://github.com/raspberrypi/pico-sdk/blob/bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7/src/rp2_common/hardware_i2c/i2c.c#L69
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2022-08-19 11:51:42 +02:00
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let clk_base = crate::clocks::clk_sys_freq();
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let period = (clk_base + config.frequency / 2) / config.frequency;
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let lcnt = period * 3 / 5; // spend 3/5 (60%) of the period low
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let hcnt = period - lcnt; // and 2/5 (40%) of the period high
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// Check for out-of-range divisors:
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assert!(hcnt <= 0xffff);
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assert!(lcnt <= 0xffff);
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assert!(hcnt >= 8);
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assert!(lcnt >= 8);
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// Per I2C-bus specification a device in standard or fast mode must
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2022-08-19 14:15:43 +02:00
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// internally provide a hold time of at least 300ns for the SDA
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// signal to bridge the undefined region of the falling edge of SCL.
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// A smaller hold time of 120ns is used for fast mode plus.
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2022-08-19 11:51:42 +02:00
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let sda_tx_hold_count = if config.frequency < 1_000_000 {
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2022-08-19 14:15:43 +02:00
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// sda_tx_hold_count = clk_base [cycles/s] * 300ns * (1s /
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// 1e9ns) Reduce 300/1e9 to 3/1e7 to avoid numbers that don't
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// fit in uint. Add 1 to avoid division truncation.
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2022-08-19 11:51:42 +02:00
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((clk_base * 3) / 10_000_000) + 1
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} else {
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// fast mode plus requires a clk_base > 32MHz
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assert!(clk_base >= 32_000_000);
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2022-08-19 14:15:43 +02:00
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// sda_tx_hold_count = clk_base [cycles/s] * 120ns * (1s /
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// 1e9ns) Reduce 120/1e9 to 3/25e6 to avoid numbers that don't
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// fit in uint. Add 1 to avoid division truncation.
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2022-08-19 11:51:42 +02:00
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((clk_base * 3) / 25_000_000) + 1
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};
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assert!(sda_tx_hold_count <= lcnt - 2);
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p.ic_fs_scl_hcnt().write(|w| w.set_ic_fs_scl_hcnt(hcnt as u16));
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p.ic_fs_scl_lcnt().write(|w| w.set_ic_fs_scl_lcnt(lcnt as u16));
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p.ic_fs_spklen()
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.write(|w| w.set_ic_fs_spklen(if lcnt < 16 { 1 } else { (lcnt / 16) as u8 }));
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p.ic_sda_hold()
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.write(|w| w.set_ic_sda_tx_hold(sda_tx_hold_count as u16));
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// Enable I2C block
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p.ic_enable().write(|w| w.set_enable(true));
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}
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Self { phantom: PhantomData }
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}
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}
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2022-08-19 14:15:43 +02:00
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impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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/// Number of bytes currently in the RX FIFO
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#[inline]
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pub fn rx_fifo_used(&self) -> u8 {
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unsafe { T::regs().ic_rxflr().read().rxflr() }
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}
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/// Remaining capacity in the RX FIFO
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#[inline]
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pub fn rx_fifo_free(&self) -> u8 {
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RX_FIFO_SIZE - self.rx_fifo_used()
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}
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/// RX FIFO is empty
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#[inline]
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pub fn rx_fifo_empty(&self) -> bool {
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self.rx_fifo_used() == 0
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}
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/// Number of bytes currently in the TX FIFO
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#[inline]
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pub fn tx_fifo_used(&self) -> u8 {
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unsafe { T::regs().ic_txflr().read().txflr() }
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}
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/// Remaining capacity in the TX FIFO
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#[inline]
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pub fn tx_fifo_free(&self) -> u8 {
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TX_FIFO_SIZE - self.tx_fifo_used()
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}
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/// TX FIFO is at capacity
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#[inline]
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pub fn tx_fifo_full(&self) -> bool {
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self.tx_fifo_free() == 0
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}
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fn setup(addr: u16) -> Result<(), Error> {
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if addr >= 0x80 {
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return Err(Error::AddressOutOfRange(addr));
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}
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if i2c_reserved_addr(addr) {
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return Err(Error::AddressReserved(addr));
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}
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let p = T::regs();
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unsafe {
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p.ic_enable().write(|w| w.set_enable(false));
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p.ic_tar().write(|w| w.set_ic_tar(addr));
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p.ic_enable().write(|w| w.set_enable(true));
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}
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Ok(())
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}
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fn read_and_clear_abort_reason(&mut self) -> Option<u32> {
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let p = T::regs();
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unsafe {
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let abort_reason = p.ic_tx_abrt_source().read().0;
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if abort_reason != 0 {
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// Note clearing the abort flag also clears the reason, and this
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// instance of flag is clear-on-read! Note also the
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// IC_CLR_TX_ABRT register always reads as 0.
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p.ic_clr_tx_abrt().read();
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Some(abort_reason)
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} else {
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None
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}
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}
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}
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fn read_blocking_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
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if buffer.is_empty() {
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return Err(Error::InvalidReadBufferLength);
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}
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let p = T::regs();
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let lastindex = buffer.len() - 1;
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for (i, byte) in buffer.iter_mut().enumerate() {
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let first = i == 0;
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let last = i == lastindex;
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// NOTE(unsafe) We have &mut self
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unsafe {
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// wait until there is space in the FIFO to write the next byte
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while self.tx_fifo_full() {}
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p.ic_data_cmd().write(|w| {
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if restart && first {
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w.set_restart(true);
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} else {
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w.set_restart(false);
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}
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if send_stop && last {
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w.set_stop(true);
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} else {
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w.set_stop(false);
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}
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w.cmd()
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});
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while p.ic_rxflr().read().rxflr() == 0 {
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if let Some(abort_reason) = self.read_and_clear_abort_reason() {
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return Err(Error::Abort(abort_reason));
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}
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}
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*byte = p.ic_data_cmd().read().dat();
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}
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}
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Ok(())
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}
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fn write_blocking_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
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if bytes.is_empty() {
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return Err(Error::InvalidWriteBufferLength);
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}
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let p = T::regs();
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for (i, byte) in bytes.iter().enumerate() {
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let last = i == bytes.len() - 1;
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// NOTE(unsafe) We have &mut self
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unsafe {
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p.ic_data_cmd().write(|w| {
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if send_stop && last {
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w.set_stop(true);
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} else {
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w.set_stop(false);
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}
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w.set_dat(*byte);
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});
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// Wait until the transmission of the address/data from the
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// internal shift register has completed. For this to function
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// correctly, the TX_EMPTY_CTRL flag in IC_CON must be set. The
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// TX_EMPTY_CTRL flag was set in i2c_init.
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while !p.ic_raw_intr_stat().read().tx_empty() {}
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let abort_reason = self.read_and_clear_abort_reason();
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if abort_reason.is_some() || (send_stop && last) {
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// If the transaction was aborted or if it completed
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// successfully wait until the STOP condition has occured.
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while !p.ic_raw_intr_stat().read().stop_det() {}
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p.ic_clr_stop_det().read().clr_stop_det();
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}
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// Note the hardware issues a STOP automatically on an abort
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// condition. Note also the hardware clears RX FIFO as well as
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// TX on abort, ecause we set hwparam
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// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
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if let Some(abort_reason) = abort_reason {
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return Err(Error::Abort(abort_reason));
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}
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}
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}
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Ok(())
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}
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// ========================= Blocking public API
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// =========================
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pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.read_blocking_internal(buffer, false, true)
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// Automatic Stop
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}
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pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, true)
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}
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pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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self.write_blocking_internal(bytes, false)?;
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self.read_blocking_internal(buffer, true, true)
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// Automatic Stop
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}
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}
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// impl<'d, T: Instance> I2c<'d, T, Async> { // ========================= //
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// Async public API // =========================
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// pub async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(),
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// Error> { if bytes.is_empty() { self.write_blocking_internal(address,
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// bytes, true) } else { self.write_dma_internal(address, bytes,
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// true, true).await } }
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// pub async fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) ->
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// Result<(), Error> { if bytes.is_empty() { return
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// Err(Error::ZeroLengthTransfer); } let mut iter = bytes.iter();
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// let mut first = true; let mut current = iter.next(); while let
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// Some(c) = current { let next = iter.next(); let is_last =
|
|
|
|
// next.is_none();
|
|
|
|
|
|
|
|
// self.write_dma_internal(address, c, first, is_last).await?;
|
|
|
|
// first = false;
|
|
|
|
// current = next;
|
|
|
|
// } Ok(())
|
|
|
|
// }
|
|
|
|
|
|
|
|
// pub async fn read(&mut self, address: u8, buffer: &mut [u8]) ->
|
|
|
|
// Result<(), Error> { if buffer.is_empty() {
|
|
|
|
// self.read_blocking_internal(address, buffer, false) } else {
|
|
|
|
// self.read_dma_internal(address, buffer, false).await } }
|
|
|
|
|
|
|
|
// pub async fn write_read(&mut self, address: u8, bytes: &[u8], buffer:
|
|
|
|
// &mut [u8]) -> Result<(), Error> { if bytes.is_empty() {
|
|
|
|
// self.write_blocking_internal(address, bytes, false)?; } else {
|
|
|
|
// self.write_dma_internal(address, bytes, true, true).await?; }
|
|
|
|
|
|
|
|
// if buffer.is_empty() { self.read_blocking_internal(address, buffer,
|
|
|
|
// true)?; } else { self.read_dma_internal(address, buffer,
|
|
|
|
// true).await?; }
|
|
|
|
|
|
|
|
// Ok(())
|
|
|
|
// }
|
|
|
|
// }
|
|
|
|
|
|
|
|
mod eh02 {
|
|
|
|
use super::*;
|
|
|
|
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_read(address, buffer)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_write(address, bytes)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
|
|
self.blocking_write_read(address, bytes, buffer)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn i2c_reserved_addr(addr: u16) -> bool {
|
|
|
|
(addr & 0x78) == 0 || (addr & 0x78) == 0x78
|
|
|
|
}
|
|
|
|
|
2022-08-19 11:51:42 +02:00
|
|
|
mod sealed {
|
|
|
|
pub trait Instance {}
|
|
|
|
pub trait Mode {}
|
|
|
|
|
|
|
|
pub trait SdaPin<T: Instance> {}
|
|
|
|
pub trait SclPin<T: Instance> {}
|
|
|
|
}
|
|
|
|
|
|
|
|
pub trait Mode: sealed::Mode {}
|
|
|
|
|
|
|
|
macro_rules! impl_mode {
|
|
|
|
($name:ident) => {
|
|
|
|
impl sealed::Mode for $name {}
|
|
|
|
impl Mode for $name {}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2022-08-19 14:15:43 +02:00
|
|
|
pub struct Blocking;
|
|
|
|
pub struct Async;
|
2022-08-19 11:51:42 +02:00
|
|
|
|
2022-08-19 14:15:43 +02:00
|
|
|
impl_mode!(Blocking);
|
|
|
|
impl_mode!(Async);
|
2022-08-19 11:51:42 +02:00
|
|
|
|
|
|
|
pub trait Instance: sealed::Instance {
|
|
|
|
fn regs() -> pac::i2c::I2c;
|
|
|
|
}
|
|
|
|
|
|
|
|
macro_rules! impl_instance {
|
|
|
|
($type:ident, $irq:ident) => {
|
|
|
|
impl sealed::Instance for peripherals::$type {}
|
|
|
|
impl Instance for peripherals::$type {
|
|
|
|
fn regs() -> pac::i2c::I2c {
|
|
|
|
pac::$type
|
|
|
|
}
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
impl_instance!(I2C0, I2c0);
|
|
|
|
impl_instance!(I2C1, I2c1);
|
|
|
|
|
|
|
|
pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + crate::gpio::Pin {}
|
|
|
|
pub trait SclPin<T: Instance>: sealed::SclPin<T> + crate::gpio::Pin {}
|
|
|
|
|
|
|
|
macro_rules! impl_pin {
|
|
|
|
($pin:ident, $instance:ident, $function:ident) => {
|
|
|
|
impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
|
|
|
|
impl $function<peripherals::$instance> for peripherals::$pin {}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
impl_pin!(PIN_0, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_1, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_2, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_3, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_4, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_5, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_6, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_7, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_8, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_9, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_10, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_11, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_12, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_13, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_14, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_15, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_16, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_17, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_18, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_19, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_20, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_21, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_22, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_23, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_24, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_25, I2C0, SclPin);
|
|
|
|
impl_pin!(PIN_26, I2C1, SdaPin);
|
|
|
|
impl_pin!(PIN_27, I2C1, SclPin);
|
|
|
|
impl_pin!(PIN_28, I2C0, SdaPin);
|
|
|
|
impl_pin!(PIN_29, I2C0, SclPin);
|