usb: merge Control logic into main code.
Now that control stuff is called from just one place, there's no need to keep it as a separate struct.
This commit is contained in:
Dario Nieuwenhuis
parent
7ed462a657
commit
02ae1138e1
2 changed files with 86 additions and 168 deletions
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@ -1,7 +1,6 @@
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use core::mem;
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use super::types::*;
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use crate::driver::{self, EndpointError};
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/// Control request type.
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#[repr(u8)]
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@ -194,125 +193,3 @@ pub trait ControlHandler {
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None
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}
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}
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/// Typestate representing a ControlPipe in the DATA IN stage
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct DataInStage {
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pub(crate) length: usize,
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}
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/// Typestate representing a ControlPipe in the DATA OUT stage
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct DataOutStage {
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length: usize,
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}
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/// Typestate representing a ControlPipe in the STATUS stage
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct StatusStage {}
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) enum Setup {
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DataIn(Request, DataInStage),
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DataOut(Request, DataOutStage),
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}
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pub(crate) struct ControlPipe<C: driver::ControlPipe> {
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control: C,
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}
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impl<C: driver::ControlPipe> ControlPipe<C> {
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pub(crate) fn new(control: C) -> Self {
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ControlPipe { control }
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}
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pub(crate) async fn setup(&mut self) -> Setup {
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let req = self.control.setup().await;
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trace!("control request: {:02x}", req);
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match (req.direction, req.length) {
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(UsbDirection::Out, n) => Setup::DataOut(
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req,
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DataOutStage {
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length: usize::from(n),
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},
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),
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(UsbDirection::In, n) => Setup::DataIn(
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req,
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DataInStage {
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length: usize::from(n),
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},
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),
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}
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}
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pub(crate) async fn data_out<'a>(
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&mut self,
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buf: &'a mut [u8],
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stage: DataOutStage,
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) -> Result<(&'a [u8], StatusStage), EndpointError> {
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if stage.length == 0 {
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Ok((&[], StatusStage {}))
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} else {
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let req_length = stage.length;
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let max_packet_size = self.control.max_packet_size();
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let mut total = 0;
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for chunk in buf.chunks_mut(max_packet_size) {
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let size = self.control.data_out(chunk).await?;
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total += size;
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if size < max_packet_size || total == req_length {
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break;
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}
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}
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let res = &buf[0..total];
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#[cfg(feature = "defmt")]
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trace!(" control out data: {:02x}", res);
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#[cfg(not(feature = "defmt"))]
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trace!(" control out data: {:02x?}", res);
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Ok((res, StatusStage {}))
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}
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}
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pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
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#[cfg(feature = "defmt")]
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trace!(" control in accept {:02x}", buf);
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#[cfg(not(feature = "defmt"))]
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trace!(" control in accept {:02x?}", buf);
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let req_len = stage.length;
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let len = buf.len().min(req_len);
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let max_packet_size = self.control.max_packet_size();
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let need_zlp = len != req_len && (len % usize::from(max_packet_size)) == 0;
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let mut chunks = buf[0..len]
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.chunks(max_packet_size)
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.chain(need_zlp.then(|| -> &[u8] { &[] }));
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while let Some(chunk) = chunks.next() {
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match self.control.data_in(chunk, chunks.size_hint().0 == 0).await {
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Ok(()) => {}
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Err(e) => {
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warn!("control accept_in failed: {:?}", e);
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return;
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}
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}
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}
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}
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pub(crate) fn accept(&mut self, _: StatusStage) {
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trace!(" control accept");
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self.control.accept();
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}
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pub(crate) fn reject(&mut self) {
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trace!(" control reject");
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self.control.reject();
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}
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}
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@ -16,6 +16,7 @@ use embassy::util::{select, Either};
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use heapless::Vec;
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use crate::descriptor_reader::foreach_endpoint;
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use crate::driver::ControlPipe;
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use self::control::*;
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use self::descriptor::*;
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@ -101,7 +102,7 @@ struct Interface<'d> {
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pub struct UsbDevice<'d, D: Driver<'d>> {
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control_buf: &'d mut [u8],
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control: ControlPipe<D::ControlPipe>,
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control: D::ControlPipe,
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inner: Inner<'d, D>,
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}
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@ -144,7 +145,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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Self {
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control_buf,
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control: ControlPipe::new(control),
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control,
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inner: Inner {
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bus,
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config,
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@ -192,52 +193,12 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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}
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}
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loop {
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while !self.inner.suspended {
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let control_fut = self.control.setup();
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let bus_fut = self.inner.bus.poll();
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match select(bus_fut, control_fut).await {
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Either::First(evt) => {
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self.inner.handle_bus_event(evt);
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if self.inner.suspended {
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return;
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}
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}
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Either::Second(req) => match req {
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Setup::DataIn(req, mut stage) => {
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// If we don't have an address yet, respond with max 1 packet.
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// The host doesn't know our EP0 max packet size yet, and might assume
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// a full-length packet is a short packet, thinking we're done sending data.
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// See https://github.com/hathach/tinyusb/issues/184
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const DEVICE_DESCRIPTOR_LEN: u8 = 18;
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if self.inner.pending_address == 0
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&& self.inner.config.max_packet_size_0 < DEVICE_DESCRIPTOR_LEN
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&& (self.inner.config.max_packet_size_0 as usize) < stage.length
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{
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trace!("received control req while not addressed: capping response to 1 packet.");
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stage.length = self.inner.config.max_packet_size_0 as _;
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}
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match self.inner.handle_control_in(req, &mut self.control_buf) {
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InResponse::Accepted(data) => self.control.accept_in(data, stage).await,
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InResponse::Rejected => self.control.reject(),
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}
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}
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Setup::DataOut(req, stage) => {
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let (data, stage) =
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match self.control.data_out(self.control_buf, stage).await {
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Ok(data) => data,
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Err(_) => {
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warn!("usb: failed to read CONTROL OUT data stage.");
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return;
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}
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};
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match self.inner.handle_control_out(req, data) {
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OutResponse::Accepted => self.control.accept(stage),
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OutResponse::Rejected => self.control.reject(),
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}
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}
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},
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Either::First(evt) => self.inner.handle_bus_event(evt),
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Either::Second(req) => self.handle_control(req).await,
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}
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}
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}
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@ -288,6 +249,86 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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Err(RemoteWakeupError::InvalidState)
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}
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}
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async fn handle_control(&mut self, req: Request) {
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trace!("control request: {:02x}", req);
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match req.direction {
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UsbDirection::In => self.handle_control_in(req).await,
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UsbDirection::Out => self.handle_control_out(req).await,
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}
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}
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async fn handle_control_in(&mut self, req: Request) {
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let mut resp_length = req.length as usize;
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let max_packet_size = self.control.max_packet_size();
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// If we don't have an address yet, respond with max 1 packet.
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// The host doesn't know our EP0 max packet size yet, and might assume
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// a full-length packet is a short packet, thinking we're done sending data.
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// See https://github.com/hathach/tinyusb/issues/184
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const DEVICE_DESCRIPTOR_LEN: usize = 18;
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if self.inner.pending_address == 0
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&& max_packet_size < DEVICE_DESCRIPTOR_LEN
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&& (max_packet_size as usize) < resp_length
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{
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trace!("received control req while not addressed: capping response to 1 packet.");
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resp_length = max_packet_size;
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}
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match self.inner.handle_control_in(req, &mut self.control_buf) {
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InResponse::Accepted(data) => {
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let len = data.len().min(resp_length);
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let need_zlp = len != resp_length && (len % usize::from(max_packet_size)) == 0;
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let mut chunks = data[0..len]
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.chunks(max_packet_size)
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.chain(need_zlp.then(|| -> &[u8] { &[] }));
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while let Some(chunk) = chunks.next() {
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match self.control.data_in(chunk, chunks.size_hint().0 == 0).await {
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Ok(()) => {}
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Err(e) => {
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warn!("control accept_in failed: {:?}", e);
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return;
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}
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}
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}
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}
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InResponse::Rejected => self.control.reject(),
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}
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}
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async fn handle_control_out(&mut self, req: Request) {
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let req_length = req.length as usize;
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let max_packet_size = self.control.max_packet_size();
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let mut total = 0;
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for chunk in self.control_buf[..req_length].chunks_mut(max_packet_size) {
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let size = match self.control.data_out(chunk).await {
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Ok(x) => x,
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Err(e) => {
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warn!("usb: failed to read CONTROL OUT data stage: {:?}", e);
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return;
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}
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};
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total += size;
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if size < max_packet_size || total == req_length {
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break;
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}
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}
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let data = &self.control_buf[0..total];
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#[cfg(feature = "defmt")]
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trace!(" control out data: {:02x}", data);
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#[cfg(not(feature = "defmt"))]
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trace!(" control out data: {:02x?}", data);
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match self.inner.handle_control_out(req, data) {
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OutResponse::Accepted => self.control.accept(),
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OutResponse::Rejected => self.control.reject(),
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}
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}
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}
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impl<'d, D: Driver<'d>> Inner<'d, D> {
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