Refactor async I2C transfers to use frame options
This commit is contained in:
Sebastian Goll
parent
746ded94b1
commit
0885c102d3
1 changed files with 183 additions and 158 deletions
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@ -459,7 +459,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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});
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}
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async fn write_with_stop(&mut self, address: u8, write: &[u8], send_stop: bool) -> Result<(), Error>
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async fn write_frame(&mut self, address: u8, write: &[u8], frame: FrameOptions) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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@ -487,74 +487,76 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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})
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});
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Self::enable_interrupts();
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// Send a START condition
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T::regs().cr1().modify(|reg| {
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reg.set_start(true);
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});
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let state = T::state();
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// Wait until START condition was generated
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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if frame.send_start() {
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// Send a START condition
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Self::enable_interrupts();
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T::regs().cr1().modify(|reg| {
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reg.set_start(true);
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});
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.start() {
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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// Wait until START condition was generated
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.start() {
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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}
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}
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}
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})
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.await?;
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})
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.await?;
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// Also wait until signalled we're master and everything is waiting for us
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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// Also wait until signalled we're master and everything is waiting for us
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(_) => {
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let sr2 = T::regs().sr2().read();
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if !sr2.msl() && !sr2.busy() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(_) => {
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let sr2 = T::regs().sr2().read();
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if !sr2.msl() && !sr2.busy() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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}
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}
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}
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})
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.await?;
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})
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.await?;
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// Set up current address, we're trying to talk to
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Self::enable_interrupts();
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T::regs().dr().write(|reg| reg.set_dr(address << 1));
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// Set up current address, we're trying to talk to
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Self::enable_interrupts();
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T::regs().dr().write(|reg| reg.set_dr(address << 1));
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.addr() {
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// Clear the ADDR condition by reading SR2.
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T::regs().sr2().read();
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Poll::Ready(Ok(()))
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} else {
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// If we need to go around, then re-enable the interrupts, otherwise nothing
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// can wake us up and we'll hang.
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Self::enable_interrupts();
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Poll::Pending
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.addr() {
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// Clear the ADDR condition by reading SR2.
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T::regs().sr2().read();
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Poll::Ready(Ok(()))
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} else {
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// If we need to go around, then re-enable the interrupts, otherwise nothing
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// can wake us up and we'll hang.
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Self::enable_interrupts();
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Poll::Pending
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}
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}
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}
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}
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})
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.await?;
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})
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.await?;
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}
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Self::enable_interrupts();
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let poll_error = poll_fn(|cx| {
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state.waker.register(cx.waker());
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@ -591,7 +593,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.btf() {
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if send_stop {
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if frame.send_stop() {
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T::regs().cr1().modify(|w| {
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w.set_stop(true);
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});
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@ -606,6 +608,21 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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})
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.await?;
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if frame.send_stop() {
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// Wait for STOP condition to transmit.
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Self::enable_interrupts();
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poll_fn(|cx| {
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T::state().waker.register(cx.waker());
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// TODO: error interrupts are enabled here, should we additional check for and return errors?
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if T::regs().cr1().read().stop() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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})
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.await?;
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}
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drop(on_drop);
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// Fallthrough is success
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@ -617,26 +634,24 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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self.write_with_stop(address, write, true).await?;
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// Wait for STOP condition to transmit.
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Self::enable_interrupts();
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poll_fn(|cx| {
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T::state().waker.register(cx.waker());
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// TODO: error interrupts are enabled here, should we additional check for and return errors?
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if T::regs().cr1().read().stop() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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})
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.await?;
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self.write_frame(address, write, FrameOptions::FirstAndLastFrame)
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.await?;
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Ok(())
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}
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/// Read.
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pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
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where
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RXDMA: crate::i2c::RxDma<T>,
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{
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self.read_frame(address, buffer, FrameOptions::FirstAndLastFrame)
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.await?;
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Ok(())
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}
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async fn read_frame(&mut self, address: u8, buffer: &mut [u8], frame: FrameOptions) -> Result<(), Error>
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where
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RXDMA: crate::i2c::RxDma<T>,
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{
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@ -667,98 +682,99 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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})
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});
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Self::enable_interrupts();
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if frame.send_start() {
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// Send a START condition and set ACK bit
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Self::enable_interrupts();
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T::regs().cr1().modify(|reg| {
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reg.set_start(true);
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reg.set_ack(true);
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});
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// Send a START condition and set ACK bit
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T::regs().cr1().modify(|reg| {
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reg.set_start(true);
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reg.set_ack(true);
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});
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// Wait until START condition was generated
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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// Wait until START condition was generated
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.start() {
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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}
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}
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})
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.await?;
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// Also wait until signalled we're master and everything is waiting for us
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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// blocking read didn’t have a check_and_clear call here, but blocking write did so
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// I’m adding it here in case that was an oversight.
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(_) => {
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let sr2 = T::regs().sr2().read();
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if !sr2.msl() && !sr2.busy() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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}
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}
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})
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.await?;
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// Set up current address, we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr((address << 1) + 1));
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// Wait for the address to be acknowledged
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.addr() {
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// 18.3.8: When a single byte must be received: the NACK must be programmed during EV6
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// event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag.
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if buffer_len == 1 {
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T::regs().cr1().modify(|w| {
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w.set_ack(false);
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});
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.start() {
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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}
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}
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})
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.await?;
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})
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.await?;
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// Clear ADDR condition by reading SR2
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T::regs().sr2().read();
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// Also wait until signalled we're master and everything is waiting for us
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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// blocking read didn’t have a check_and_clear call here, but blocking write did so
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// I’m adding it here in case that was an oversight.
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(_) => {
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let sr2 = T::regs().sr2().read();
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if !sr2.msl() && !sr2.busy() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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}
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}
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})
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.await?;
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// Set up current address, we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr((address << 1) + 1));
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// Wait for the address to be acknowledged
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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match Self::check_and_clear_error_flags() {
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Err(e) => Poll::Ready(Err(e)),
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Ok(sr1) => {
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if sr1.addr() {
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// 18.3.8: When a single byte must be received: the NACK must be programmed during EV6
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// event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag.
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if buffer_len == 1 && frame.send_nack() {
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T::regs().cr1().modify(|w| {
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w.set_ack(false);
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});
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}
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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}
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}
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})
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.await?;
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// Clear ADDR condition by reading SR2
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T::regs().sr2().read();
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}
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// 18.3.8: When a single byte must be received: [snip] Then the
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// user can program the STOP condition either after clearing ADDR flag, or in the
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// DMA Transfer Complete interrupt routine.
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if buffer_len == 1 {
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if buffer_len == 1 && frame.send_stop() {
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T::regs().cr1().modify(|w| {
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w.set_stop(true);
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});
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} else {
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} else if buffer_len != 1 && frame.send_nack() {
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// If, in the I2C_CR2 register, the LAST bit is set, I2C
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// automatically sends a NACK after the next byte following EOT_1. The user can
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// generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
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T::regs().cr2().modify(|w| {
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w.set_last(true);
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})
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});
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}
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// Wait for bytes to be received, or an error to occur.
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@ -777,18 +793,27 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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_ => Ok(()),
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}?;
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// Wait for the STOP to be sent (STOP bit cleared).
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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// TODO: error interrupts are enabled here, should we additional check for and return errors?
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if T::regs().cr1().read().stop() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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if frame.send_stop() {
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if buffer_len != 1 {
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T::regs().cr1().modify(|w| {
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w.set_stop(true);
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});
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}
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})
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.await?;
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// Wait for the STOP to be sent (STOP bit cleared).
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Self::enable_interrupts();
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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// TODO: error interrupts are enabled here, should we additional check for and return errors?
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if T::regs().cr1().read().stop() {
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Poll::Pending
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} else {
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Poll::Ready(Ok(()))
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}
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})
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.await?;
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}
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drop(on_drop);
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// Fallthrough is success
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@ -801,8 +826,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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RXDMA: crate::i2c::RxDma<T>,
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TXDMA: crate::i2c::TxDma<T>,
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{
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self.write_with_stop(address, write, false).await?;
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self.read(address, read).await
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self.write_frame(address, write, FrameOptions::FirstFrame).await?;
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self.read_frame(address, read, FrameOptions::FirstAndLastFrame).await
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}
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}
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