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Refactor async I2C transfers to use frame options

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This commit is contained in:
Sebastian Goll 2024-03-20 20:11:59 +01:00
parent 746ded94b1
commit 0885c102d3
1 changed files with 183 additions and 158 deletions
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77
embassy-stm32/src/i2c/v1.rs
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@ -459,7 +459,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
});
}
async fn write_with_stop(&mut self, address: u8, write: &[u8], send_stop: bool) -> Result<(), Error>
async fn write_frame(&mut self, address: u8, write: &[u8], frame: FrameOptions) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
@ -487,15 +487,15 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
})
});
Self::enable_interrupts();
let state = T::state();
if frame.send_start() {
// Send a START condition
Self::enable_interrupts();
T::regs().cr1().modify(|reg| {
reg.set_start(true);
});
let state = T::state();
// Wait until START condition was generated
poll_fn(|cx| {
state.waker.register(cx.waker());
@ -555,6 +555,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
})
.await?;
}
Self::enable_interrupts();
let poll_error = poll_fn(|cx| {
state.waker.register(cx.waker());
@ -591,7 +593,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
Err(e) => Poll::Ready(Err(e)),
Ok(sr1) => {
if sr1.btf() {
if send_stop {
if frame.send_stop() {
T::regs().cr1().modify(|w| {
w.set_stop(true);
});
@ -606,19 +608,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
})
.await?;
drop(on_drop);
// Fallthrough is success
Ok(())
}
/// Write.
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.write_with_stop(address, write, true).await?;
if frame.send_stop() {
// Wait for STOP condition to transmit.
Self::enable_interrupts();
poll_fn(|cx| {
@ -631,12 +621,37 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
})
.await?;
}
drop(on_drop);
// Fallthrough is success
Ok(())
}
/// Write.
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
self.write_frame(address, write, FrameOptions::FirstAndLastFrame)
.await?;
Ok(())
}
/// Read.
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
self.read_frame(address, buffer, FrameOptions::FirstAndLastFrame)
.await?;
Ok(())
}
async fn read_frame(&mut self, address: u8, buffer: &mut [u8], frame: FrameOptions) -> Result<(), Error>
where
RXDMA: crate::i2c::RxDma<T>,
{
@ -667,9 +682,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
})
});
Self::enable_interrupts();
if frame.send_start() {
// Send a START condition and set ACK bit
Self::enable_interrupts();
T::regs().cr1().modify(|reg| {
reg.set_start(true);
reg.set_ack(true);
@ -728,7 +743,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
if sr1.addr() {
// 18.3.8: When a single byte must be received: the NACK must be programmed during EV6
// event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag.
if buffer_len == 1 {
if buffer_len == 1 && frame.send_nack() {
T::regs().cr1().modify(|w| {
w.set_ack(false);
});
@ -744,21 +759,22 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// Clear ADDR condition by reading SR2
T::regs().sr2().read();
}
// 18.3.8: When a single byte must be received: [snip] Then the
// user can program the STOP condition either after clearing ADDR flag, or in the
// DMA Transfer Complete interrupt routine.
if buffer_len == 1 {
if buffer_len == 1 && frame.send_stop() {
T::regs().cr1().modify(|w| {
w.set_stop(true);
});
} else {
} else if buffer_len != 1 && frame.send_nack() {
// If, in the I2C_CR2 register, the LAST bit is set, I2C
// automatically sends a NACK after the next byte following EOT_1. The user can
// generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
T::regs().cr2().modify(|w| {
w.set_last(true);
})
});
}
// Wait for bytes to be received, or an error to occur.
@ -777,6 +793,13 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
_ => Ok(()),
}?;
if frame.send_stop() {
if buffer_len != 1 {
T::regs().cr1().modify(|w| {
w.set_stop(true);
});
}
// Wait for the STOP to be sent (STOP bit cleared).
Self::enable_interrupts();
poll_fn(|cx| {
@ -789,6 +812,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
})
.await?;
}
drop(on_drop);
// Fallthrough is success
@ -801,8 +826,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
RXDMA: crate::i2c::RxDma<T>,
TXDMA: crate::i2c::TxDma<T>,
{
self.write_with_stop(address, write, false).await?;
self.read(address, read).await
self.write_frame(address, write, FrameOptions::FirstFrame).await?;
self.read_frame(address, read, FrameOptions::FirstAndLastFrame).await
}
}