Merge #768
768: nrf/usb: fix control out transfers getting corrupted due to ep0rcvout sticking from earlier. r=Dirbaio a=Dirbaio bors r+ Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This commit is contained in:
commit
13bcb5ffb6
3 changed files with 19 additions and 27 deletions
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@ -9,7 +9,6 @@ use embassy::interrupt::InterruptExt;
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use embassy::util::Unborrow;
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::unborrow;
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use embassy_usb::control::Request;
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use embassy_usb::driver::{self, EndpointError, Event, Unsupported};
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use embassy_usb::types::{EndpointAddress, EndpointInfo, EndpointType, UsbDirection};
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use futures::future::poll_fn;
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@ -526,10 +525,6 @@ unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, Endpo
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return Err(EndpointError::BufferOverflow);
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}
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if i == 0 {
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regs.events_ep0datadone.reset();
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}
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let epout = [
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®s.epout0,
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®s.epout1,
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@ -640,7 +635,7 @@ pub struct ControlPipe<'d, T: Instance> {
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}
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impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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type SetupFuture<'a> = impl Future<Output = Request> + 'a where Self: 'a;
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type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
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type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
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type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
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@ -652,11 +647,11 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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async move {
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let regs = T::regs();
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// Reset shorts
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regs.shorts.write(|w| w);
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// Wait for SETUP packet
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regs.intenset.write(|w| {
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w.ep0setup().set();
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w.ep0datadone().set()
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});
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regs.intenset.write(|w| w.ep0setup().set());
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poll_fn(|cx| {
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EP0_WAKER.register(cx.waker());
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let regs = T::regs();
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@ -668,8 +663,6 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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})
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.await;
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// Reset shorts
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regs.shorts.write(|w| w);
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regs.events_ep0setup.reset();
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let mut buf = [0; 8];
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@ -682,14 +675,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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buf[6] = regs.wlengthl.read().wlengthl().bits();
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buf[7] = regs.wlengthh.read().wlengthh().bits();
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let req = Request::parse(&buf);
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if req.direction == UsbDirection::Out {
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regs.tasks_ep0rcvout
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.write(|w| w.tasks_ep0rcvout().set_bit());
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}
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req
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buf
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}
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}
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@ -697,6 +683,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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async move {
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let regs = T::regs();
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regs.events_ep0datadone.reset();
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// This starts a RX on EP0. events_ep0datadone notifies when done.
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regs.tasks_ep0rcvout
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.write(|w| w.tasks_ep0rcvout().set_bit());
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// Wait until ready
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regs.intenset.write(|w| {
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w.usbreset().set();
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@ -728,13 +720,13 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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async move {
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let regs = T::regs();
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regs.events_ep0datadone.reset();
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unsafe {
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write_dma::<T>(0, buf);
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}
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regs.shorts
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.write(|w| w.ep0datadone_ep0status().bit(last_packet));
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// This starts a TX on EP0. events_ep0datadone notifies when done.
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unsafe { write_dma::<T>(0, buf) }
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regs.intenset.write(|w| {
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w.usbreset().set();
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w.ep0setup().set();
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@ -1,7 +1,5 @@
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use core::future::Future;
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use crate::control::Request;
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use super::types::*;
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/// Driver for a specific USB peripheral. Implement this to add support for a new hardware
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@ -146,7 +144,7 @@ pub trait EndpointOut: Endpoint {
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}
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pub trait ControlPipe {
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type SetupFuture<'a>: Future<Output = Request> + 'a
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type SetupFuture<'a>: Future<Output = [u8; 8]> + 'a
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where
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Self: 'a;
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type DataOutFuture<'a>: Future<Output = Result<usize, EndpointError>> + 'a
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@ -246,7 +246,9 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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}
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}
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async fn handle_control(&mut self, req: Request) {
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async fn handle_control(&mut self, req: [u8; 8]) {
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let req = Request::parse(&req);
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trace!("control request: {:02x}", req);
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match req.direction {
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