stm32/rcc: unify f0, f1, f3.
This commit is contained in:
Dario Nieuwenhuis
parent
ccd2c574c3
commit
1860e22693
6 changed files with 137 additions and 525 deletions
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@ -68,7 +68,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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critical-section = "1.1"
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#stm32-metapac = { version = "15" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8" }
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vcell = "0.1.3"
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bxcan = "0.7.0"
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nb = "1.0.0"
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@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8", default-features = false, features = ["metadata"]}
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[features]
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@ -1,232 +0,0 @@
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::Pllsrc;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv, Sw as Sysclk,
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};
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(8_000_000);
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum PllSource {
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HSE,
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HSI,
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#[cfg(rcc_f0v4)]
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HSI48,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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pub src: PllSource,
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/// PLL pre-divider.
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///
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/// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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}
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/// Clocks configutation
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#[non_exhaustive]
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pub struct Config {
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pub hsi: bool,
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pub hse: Option<Hse>,
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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pub sys: Sysclk,
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pub pll: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub ls: super::LsConfig,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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hsi: true,
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hse: None,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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sys: Sysclk::HSI,
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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}
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}
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}
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/// Initialize and Set the clock frequencies
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pub(crate) unsafe fn init(config: Config) {
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// Configure HSI
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let hsi = match config.hsi {
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false => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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true => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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Some(HSI_FREQ)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// configure HSI48
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#[cfg(crs)]
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let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
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#[cfg(not(crs))]
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let hsi48: Option<Hertz> = None;
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// Enable PLL
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let pll = config.pll.map(|pll| {
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let (src_val, src_freq) = match pll.src {
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#[cfg(not(any(rcc_f0v1, rcc_f0v2)))]
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PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
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#[cfg(any(rcc_f0v1, rcc_f0v2))]
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PllSource::HSI => {
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if pll.prediv != PllPreDiv::DIV2 {
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panic!("if PLL source is HSI, PLL prediv must be 2.");
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}
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(Pllsrc::HSI_DIV2, unwrap!(hsi))
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}
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PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
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#[cfg(rcc_f0v4)]
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PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
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};
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let in_freq = src_freq / pll.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let out_freq = in_freq * pll.mul;
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assert!(max::PLL_OUT.contains(&out_freq));
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RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
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RCC.cfgr().modify(|w| {
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w.set_pllmul(pll.mul);
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w.set_pllsrc(src_val);
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});
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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out_freq
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});
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// Configure sysclk
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let sys = match config.sys {
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Sysclk::HSI => unwrap!(hsi),
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Sysclk::HSE => unwrap!(hse),
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Sysclk::PLL1_P => unwrap!(pll),
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#[cfg(rcc_f0v4)]
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Sysclk::HSI48 => unwrap!(hsi48),
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#[allow(unreachable_patterns)]
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_ => unreachable!(),
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};
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let hclk = sys / config.ahb_pre;
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
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assert!(max::HCLK.contains(&hclk));
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assert!(max::PCLK1.contains(&pclk1));
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// Set latency based on HCLK frquency
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let latency = match hclk.0 {
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..=24_000_000 => Latency::WS0,
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_ => Latency::WS1,
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};
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FLASH.acr().modify(|w| {
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w.set_latency(latency);
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w.set_prftbe(true);
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});
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// Set prescalers
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// CFGR has been written before (PLL, PLL48) don't overwrite these settings
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RCC.cfgr().modify(|w| {
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w.set_ppre(config.apb1_pre);
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w.set_hpre(config.ahb_pre);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from
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// 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
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RCC.cfgr().modify(|w| w.set_sw(config.sys));
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while RCC.cfgr().read().sws() != config.sys {}
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let rtc = config.ls.init();
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set_clocks!(
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hsi: hsi,
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hse: hse,
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pll1_p: pll,
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sys: Some(sys),
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pclk1: Some(pclk1),
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pclk2: Some(pclk1),
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pclk1_tim: Some(pclk1_tim),
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pclk2_tim: Some(pclk1_tim),
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hclk1: Some(hclk),
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#[cfg(all(not(rcc_f37), adc3_common))]
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adc34: Some(adc34),
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#[cfg(stm32f334)]
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hrtim: hrtim,
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hsi48: hsi48,
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rtc: rtc,
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lse: None,
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);
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}
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
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pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
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pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
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pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
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pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
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}
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@ -1,9 +1,14 @@
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use crate::pac::flash::vals::Latency;
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pub use crate::pac::rcc::vals::{
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Adcpres as AdcPllPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv,
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Sw as Sysclk,
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};
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use crate::pac::rcc::vals::{Pllsrc, Usbpre};
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#[cfg(stm32f1)]
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pub use crate::pac::rcc::vals::Adcpre as ADCPrescaler;
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#[cfg(stm32f3)]
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pub use crate::pac::rcc::vals::Adcpres as AdcPllPrescaler;
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use crate::pac::rcc::vals::Pllsrc;
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#[cfg(stm32f1)]
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pub use crate::pac::rcc::vals::Pllxtpre as PllPreDiv;
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#[cfg(any(stm32f0, stm32f3))]
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pub use crate::pac::rcc::vals::Prediv as PllPreDiv;
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pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Sw as Sysclk};
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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@ -30,6 +35,8 @@ pub struct Hse {
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pub enum PllSource {
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HSE,
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HSI,
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#[cfg(rcc_f0v4)]
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HSI48,
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}
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#[derive(Clone, Copy)]
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@ -38,19 +45,21 @@ pub struct Pll {
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/// PLL pre-divider.
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///
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/// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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/// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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#[derive(Clone, Copy)]
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pub enum AdcClockSource {
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Pll(AdcPllPrescaler),
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Hclk(AdcHclkPrescaler),
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum AdcHclkPrescaler {
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Div1,
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@ -58,6 +67,7 @@ pub enum AdcHclkPrescaler {
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Div4,
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}
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#[cfg(stm32f334)]
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum HrtimClockSource {
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BusClk,
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@ -69,17 +79,23 @@ pub enum HrtimClockSource {
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pub struct Config {
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pub hsi: bool,
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pub hse: Option<Hse>,
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#[cfg(crs)]
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pub hsi48: Option<super::Hsi48Config>,
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pub sys: Sysclk,
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pub pll: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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#[cfg(not(stm32f0))]
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pub apb2_pre: APBPrescaler,
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#[cfg(not(rcc_f37))]
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#[cfg(stm32f1)]
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pub adc_pre: ADCPrescaler,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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pub adc: AdcClockSource,
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#[cfg(all(not(rcc_f37), adc3_common))]
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#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
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pub adc34: AdcClockSource,
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#[cfg(stm32f334)]
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pub hrtim: HrtimClockSource,
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@ -92,16 +108,24 @@ impl Default for Config {
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Self {
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hsi: true,
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hse: None,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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sys: Sysclk::HSI,
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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#[cfg(not(stm32f0))]
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apb2_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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#[cfg(not(rcc_f37))]
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#[cfg(stm32f1)]
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// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
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adc_pre: ADCPrescaler::DIV6,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(all(not(rcc_f37), adc3_common))]
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#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
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adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(stm32f334)]
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hrtim: HrtimClockSource::BusClk,
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@ -143,13 +167,18 @@ pub(crate) unsafe fn init(config: Config) {
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}
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};
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// configure HSI48
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#[cfg(crs)]
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let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
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#[cfg(not(crs))]
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let hsi48: Option<Hertz> = None;
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// Enable PLL
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// RM0316: "Reserved, must be kept at reset value."
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let pll = config.pll.map(|pll| {
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let (src_val, src_freq) = match pll.src {
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#[cfg(rcc_f3v3)]
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#[cfg(any(rcc_f0v3, rcc_f0v4, rcc_f3v3))]
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PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
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#[cfg(not(rcc_f3v3))]
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#[cfg(not(any(rcc_f0v3, rcc_f0v4, rcc_f3v3)))]
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PllSource::HSI => {
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if pll.prediv != PllPreDiv::DIV2 {
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panic!("if PLL source is HSI, PLL prediv must be 2.");
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@ -157,16 +186,21 @@ pub(crate) unsafe fn init(config: Config) {
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(Pllsrc::HSI_DIV2, unwrap!(hsi))
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}
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PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
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#[cfg(rcc_f0v4)]
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PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
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};
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let in_freq = src_freq / pll.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let out_freq = in_freq * pll.mul;
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assert!(max::PLL_OUT.contains(&out_freq));
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#[cfg(not(stm32f1))]
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RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
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RCC.cfgr().modify(|w| {
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w.set_pllmul(pll.mul);
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w.set_pllsrc(src_val);
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#[cfg(stm32f1)]
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w.set_pllxtpre(pll.prediv);
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});
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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@ -174,17 +208,16 @@ pub(crate) unsafe fn init(config: Config) {
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out_freq
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});
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|
||||
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
|
||||
let usb = match pll {
|
||||
Some(Hertz(72_000_000)) => {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
|
||||
Some(Hertz(48_000_000))
|
||||
}
|
||||
Some(Hertz(48_000_000)) => {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
|
||||
Some(Hertz(48_000_000))
|
||||
}
|
||||
Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
|
||||
Some(Hertz(48_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1),
|
||||
_ => None,
|
||||
};
|
||||
}
|
||||
.map(|usbpre| {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(usbpre));
|
||||
Hertz(48_000_000)
|
||||
});
|
||||
|
||||
// Configure sysclk
|
||||
let sys = match config.sys {
|
||||
|
|
@ -196,13 +229,28 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
|
||||
let hclk = sys / config.ahb_pre;
|
||||
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
|
||||
#[cfg(not(stm32f0))]
|
||||
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
|
||||
#[cfg(stm32f0)]
|
||||
let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
|
||||
|
||||
assert!(max::HCLK.contains(&hclk));
|
||||
assert!(max::PCLK1.contains(&pclk1));
|
||||
#[cfg(not(stm32f0))]
|
||||
assert!(max::PCLK2.contains(&pclk2));
|
||||
|
||||
#[cfg(stm32f1)]
|
||||
let adc = pclk2 / config.adc_pre;
|
||||
#[cfg(stm32f1)]
|
||||
assert!(max::ADC.contains(&adc));
|
||||
|
||||
// Set latency based on HCLK frquency
|
||||
#[cfg(stm32f0)]
|
||||
let latency = match hclk.0 {
|
||||
..=24_000_000 => Latency::WS0,
|
||||
_ => Latency::WS1,
|
||||
};
|
||||
#[cfg(any(stm32f1, stm32f3))]
|
||||
let latency = match hclk.0 {
|
||||
..=24_000_000 => Latency::WS0,
|
||||
..=48_000_000 => Latency::WS1,
|
||||
|
|
@ -213,18 +261,28 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
// RM0316: "The prefetch buffer must be kept on when using a prescaler
|
||||
// different from 1 on the AHB clock.", "Half-cycle access cannot be
|
||||
// used when there is a prescaler different from 1 on the AHB clock"
|
||||
#[cfg(stm32f3)]
|
||||
if config.ahb_pre != AHBPrescaler::DIV1 {
|
||||
w.set_hlfcya(false);
|
||||
w.set_prftbe(true);
|
||||
}
|
||||
#[cfg(not(stm32f3))]
|
||||
w.set_prftbe(true);
|
||||
});
|
||||
|
||||
// Set prescalers
|
||||
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_ppre1(config.apb1_pre);
|
||||
w.set_ppre2(config.apb2_pre);
|
||||
RCC.cfgr().modify(|w: &mut stm32_metapac::rcc::regs::Cfgr| {
|
||||
#[cfg(not(stm32f0))]
|
||||
{
|
||||
w.set_ppre1(config.apb1_pre);
|
||||
w.set_ppre2(config.apb2_pre);
|
||||
}
|
||||
#[cfg(stm32f0)]
|
||||
w.set_ppre(config.apb1_pre);
|
||||
w.set_hpre(config.ahb_pre);
|
||||
#[cfg(stm32f1)]
|
||||
w.set_adcpre(config.adc_pre);
|
||||
});
|
||||
|
||||
// Wait for the new prescalers to kick in
|
||||
|
|
@ -238,10 +296,10 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
|
||||
let rtc = config.ls.init();
|
||||
|
||||
#[cfg(not(rcc_f37))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37)))]
|
||||
use crate::pac::adccommon::vals::Ckmode;
|
||||
|
||||
#[cfg(not(rcc_f37))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37)))]
|
||||
let adc = match config.adc {
|
||||
AdcClockSource::Pll(adcpres) => {
|
||||
RCC.cfgr2().modify(|w| w.set_adc12pres(adcpres));
|
||||
|
|
@ -265,7 +323,7 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
}
|
||||
};
|
||||
|
||||
#[cfg(all(not(rcc_f37), adc3_common))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
|
||||
let adc34 = match config.adc34 {
|
||||
AdcClockSource::Pll(adcpres) => {
|
||||
RCC.cfgr2().modify(|w| w.set_adc34pres(adcpres));
|
||||
|
|
@ -316,18 +374,63 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
pclk1_tim: Some(pclk1_tim),
|
||||
pclk2_tim: Some(pclk2_tim),
|
||||
hclk1: Some(hclk),
|
||||
#[cfg(not(rcc_f37))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37)))]
|
||||
adc: Some(adc),
|
||||
#[cfg(all(not(rcc_f37), adc3_common))]
|
||||
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
|
||||
adc34: Some(adc34),
|
||||
#[cfg(stm32f334)]
|
||||
hrtim: hrtim,
|
||||
rtc: rtc,
|
||||
hsi48: hsi48,
|
||||
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
|
||||
usb: usb,
|
||||
lse: None,
|
||||
);
|
||||
}
|
||||
|
||||
#[cfg(stm32f0)]
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
use crate::time::Hertz;
|
||||
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
|
||||
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
|
||||
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
|
||||
pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
|
||||
}
|
||||
|
||||
#[cfg(stm32f1)]
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
use crate::time::Hertz;
|
||||
|
||||
#[cfg(not(rcc_f1cl))]
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
|
||||
#[cfg(not(rcc_f1cl))]
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
|
||||
|
||||
#[cfg(rcc_f1cl)]
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
|
||||
#[cfg(rcc_f1cl)]
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
|
||||
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
|
||||
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
|
||||
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
|
||||
pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
|
||||
|
||||
pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
|
||||
}
|
||||
|
||||
#[cfg(stm32f3)]
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
|
|
@ -1,257 +0,0 @@
|
|||
use crate::pac::flash::vals::Latency;
|
||||
use crate::pac::rcc::vals::Pllsrc;
|
||||
#[cfg(any(rcc_f1, rcc_f1cl))]
|
||||
use crate::pac::rcc::vals::Usbpre;
|
||||
pub use crate::pac::rcc::vals::{
|
||||
Adcpre as ADCPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Pllxtpre as PllPreDiv, Ppre as APBPrescaler,
|
||||
Sw as Sysclk,
|
||||
};
|
||||
use crate::pac::{FLASH, RCC};
|
||||
use crate::time::Hertz;
|
||||
|
||||
/// HSI speed
|
||||
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
|
||||
|
||||
#[derive(Clone, Copy, Eq, PartialEq)]
|
||||
pub enum HseMode {
|
||||
/// crystal/ceramic oscillator (HSEBYP=0)
|
||||
Oscillator,
|
||||
/// external analog clock (low swing) (HSEBYP=1)
|
||||
Bypass,
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Eq, PartialEq)]
|
||||
pub struct Hse {
|
||||
/// HSE frequency.
|
||||
pub freq: Hertz,
|
||||
/// HSE mode.
|
||||
pub mode: HseMode,
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Eq, PartialEq)]
|
||||
pub enum PllSource {
|
||||
HSE,
|
||||
HSI,
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Pll {
|
||||
pub src: PllSource,
|
||||
|
||||
/// PLL pre-divider.
|
||||
///
|
||||
/// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
|
||||
pub prediv: PllPreDiv,
|
||||
|
||||
/// PLL multiplication factor.
|
||||
pub mul: PllMul,
|
||||
}
|
||||
|
||||
/// Clocks configutation
|
||||
#[non_exhaustive]
|
||||
pub struct Config {
|
||||
pub hsi: bool,
|
||||
pub hse: Option<Hse>,
|
||||
pub sys: Sysclk,
|
||||
|
||||
pub pll: Option<Pll>,
|
||||
|
||||
pub ahb_pre: AHBPrescaler,
|
||||
pub apb1_pre: APBPrescaler,
|
||||
pub apb2_pre: APBPrescaler,
|
||||
|
||||
pub adc_pre: ADCPrescaler,
|
||||
|
||||
pub ls: super::LsConfig,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
hsi: true,
|
||||
hse: None,
|
||||
sys: Sysclk::HSI,
|
||||
pll: None,
|
||||
ahb_pre: AHBPrescaler::DIV1,
|
||||
apb1_pre: APBPrescaler::DIV1,
|
||||
apb2_pre: APBPrescaler::DIV1,
|
||||
ls: Default::default(),
|
||||
|
||||
// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
|
||||
adc_pre: ADCPrescaler::DIV6,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Initialize and Set the clock frequencies
|
||||
pub(crate) unsafe fn init(config: Config) {
|
||||
// Configure HSI
|
||||
let hsi = match config.hsi {
|
||||
false => {
|
||||
RCC.cr().modify(|w| w.set_hsion(false));
|
||||
None
|
||||
}
|
||||
true => {
|
||||
RCC.cr().modify(|w| w.set_hsion(true));
|
||||
while !RCC.cr().read().hsirdy() {}
|
||||
Some(HSI_FREQ)
|
||||
}
|
||||
};
|
||||
|
||||
// Configure HSE
|
||||
let hse = match config.hse {
|
||||
None => {
|
||||
RCC.cr().modify(|w| w.set_hseon(false));
|
||||
None
|
||||
}
|
||||
Some(hse) => {
|
||||
match hse.mode {
|
||||
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
|
||||
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
|
||||
}
|
||||
|
||||
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
|
||||
RCC.cr().modify(|w| w.set_hseon(true));
|
||||
while !RCC.cr().read().hserdy() {}
|
||||
Some(hse.freq)
|
||||
}
|
||||
};
|
||||
|
||||
// Enable PLL
|
||||
let pll = config.pll.map(|pll| {
|
||||
let (src_val, src_freq) = match pll.src {
|
||||
PllSource::HSI => {
|
||||
if pll.prediv != PllPreDiv::DIV2 {
|
||||
panic!("if PLL source is HSI, PLL prediv must be 2.");
|
||||
}
|
||||
(Pllsrc::HSI_DIV2, unwrap!(hsi))
|
||||
}
|
||||
PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
|
||||
};
|
||||
let in_freq = src_freq / pll.prediv;
|
||||
assert!(max::PLL_IN.contains(&in_freq));
|
||||
let out_freq = in_freq * pll.mul;
|
||||
assert!(max::PLL_OUT.contains(&out_freq));
|
||||
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_pllmul(pll.mul);
|
||||
w.set_pllsrc(src_val);
|
||||
w.set_pllxtpre(pll.prediv);
|
||||
});
|
||||
RCC.cr().modify(|w| w.set_pllon(true));
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
|
||||
out_freq
|
||||
});
|
||||
|
||||
#[cfg(any(rcc_f1, rcc_f1cl))]
|
||||
let usb = match pll {
|
||||
Some(Hertz(72_000_000)) => {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
|
||||
Some(Hertz(48_000_000))
|
||||
}
|
||||
Some(Hertz(48_000_000)) => {
|
||||
RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
|
||||
Some(Hertz(48_000_000))
|
||||
}
|
||||
_ => None,
|
||||
};
|
||||
|
||||
// Configure sysclk
|
||||
let sys = match config.sys {
|
||||
Sysclk::HSI => unwrap!(hsi),
|
||||
Sysclk::HSE => unwrap!(hse),
|
||||
Sysclk::PLL1_P => unwrap!(pll),
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
let hclk = sys / config.ahb_pre;
|
||||
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
|
||||
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
|
||||
|
||||
assert!(max::HCLK.contains(&hclk));
|
||||
assert!(max::PCLK1.contains(&pclk1));
|
||||
assert!(max::PCLK2.contains(&pclk2));
|
||||
|
||||
let adc = pclk2 / config.adc_pre;
|
||||
assert!(max::ADC.contains(&adc));
|
||||
|
||||
// Set latency based on HCLK frquency
|
||||
let latency = match hclk.0 {
|
||||
..=24_000_000 => Latency::WS0,
|
||||
..=48_000_000 => Latency::WS1,
|
||||
_ => Latency::WS2,
|
||||
};
|
||||
FLASH.acr().modify(|w| {
|
||||
w.set_latency(latency);
|
||||
// RM0316: "The prefetch buffer must be kept on when using a prescaler
|
||||
// different from 1 on the AHB clock.", "Half-cycle access cannot be
|
||||
// used when there is a prescaler different from 1 on the AHB clock"
|
||||
if config.ahb_pre != AHBPrescaler::DIV1 {
|
||||
w.set_hlfcya(false);
|
||||
w.set_prftbe(true);
|
||||
}
|
||||
});
|
||||
|
||||
// Set prescalers
|
||||
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_ppre1(config.apb1_pre);
|
||||
w.set_ppre2(config.apb2_pre);
|
||||
w.set_hpre(config.ahb_pre);
|
||||
w.set_adcpre(config.adc_pre);
|
||||
});
|
||||
|
||||
// Wait for the new prescalers to kick in
|
||||
// "The clocks are divided with the new prescaler factor from
|
||||
// 1 to 16 AHB cycles after write"
|
||||
cortex_m::asm::delay(16);
|
||||
|
||||
// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
|
||||
RCC.cfgr().modify(|w| w.set_sw(config.sys));
|
||||
while RCC.cfgr().read().sws() != config.sys {}
|
||||
|
||||
let rtc = config.ls.init();
|
||||
|
||||
set_clocks!(
|
||||
hsi: hsi,
|
||||
hse: hse,
|
||||
pll1_p: pll,
|
||||
sys: Some(sys),
|
||||
pclk1: Some(pclk1),
|
||||
pclk2: Some(pclk2),
|
||||
pclk1_tim: Some(pclk1_tim),
|
||||
pclk2_tim: Some(pclk2_tim),
|
||||
hclk1: Some(hclk),
|
||||
adc: Some(adc),
|
||||
rtc: rtc,
|
||||
#[cfg(any(rcc_f1, rcc_f1cl))]
|
||||
usb: usb,
|
||||
lse: None,
|
||||
);
|
||||
}
|
||||
|
||||
mod max {
|
||||
use core::ops::RangeInclusive;
|
||||
|
||||
use crate::time::Hertz;
|
||||
|
||||
#[cfg(not(rcc_f1cl))]
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
|
||||
#[cfg(not(rcc_f1cl))]
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
|
||||
|
||||
#[cfg(rcc_f1cl)]
|
||||
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
|
||||
#[cfg(rcc_f1cl)]
|
||||
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
|
||||
|
||||
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
|
||||
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
|
||||
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
|
||||
|
||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
|
||||
pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
|
||||
|
||||
pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
|
||||
}
|
||||
|
|
@ -18,10 +18,8 @@ mod hsi48;
|
|||
#[cfg(crs)]
|
||||
pub use hsi48::*;
|
||||
|
||||
#[cfg_attr(stm32f0, path = "f0.rs")]
|
||||
#[cfg_attr(stm32f1, path = "f1.rs")]
|
||||
#[cfg_attr(stm32f3, path = "f3.rs")]
|
||||
#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
|
||||
#[cfg_attr(any(stm32f0, stm32f1, stm32f3), path = "f013.rs")]
|
||||
#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f247.rs")]
|
||||
#[cfg_attr(stm32c0, path = "c0.rs")]
|
||||
#[cfg_attr(stm32g0, path = "g0.rs")]
|
||||
#[cfg_attr(stm32g4, path = "g4.rs")]
|
||||
|
|
|
|||
Loading…
Reference in a new issue