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Fix stm32l0 build

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This commit is contained in:
Ulf Lilleengen 2021-06-07 12:19:09 +02:00
parent f5e2fb9a5a
commit 1cd2c55b7c
2 changed files with 18 additions and 21 deletions
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2
embassy-stm32/src/clock.rs
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@ -83,7 +83,7 @@ impl<T: Instance> Clock<T> {
unsafe { unsafe {
let rcc = crate::pac::RCC; let rcc = crate::pac::RCC;
rcc.apb1enr() rcc.apb1enr()
.modify(|w| w.set_tim2en(crate::pac::rcc::vals::Lptimen::ENABLED)); .modify(|w| w.set_tim2en(true));
rcc.apb1rstr().modify(|w| w.set_tim2rst(true)); rcc.apb1rstr().modify(|w| w.set_tim2rst(true));
rcc.apb1rstr().modify(|w| w.set_tim2rst(false)); rcc.apb1rstr().modify(|w| w.set_tim2rst(false));
} }

37
embassy-stm32/src/rcc/l0/mod.rs
View file

@ -7,9 +7,7 @@ use core::marker::PhantomData;
use embassy::util::Unborrow; use embassy::util::Unborrow;
use embassy_extras::unborrow; use embassy_extras::unborrow;
use pac::dbg::vals::{DbgSleep, DbgStandby, DbgStop}; use pac::dbg::vals::{DbgSleep, DbgStandby, DbgStop};
use pac::rcc::vals::{ use pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
Crypen, Dbgen, Hpre, Iophen, Lptimen, Msirange, Plldiv, Pllmul, Pllon, Pllsrc, Ppre, Sw,
};
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC, /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
/// and with the addition of the init function to configure a system clock. /// and with the addition of the init function to configure a system clock.
@ -266,7 +264,7 @@ impl<'d> Rcc<'d> {
// NOTE(unsafe) We have exclusive access to the RCC and DBGMCU // NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
unsafe { unsafe {
if enable_dma { if enable_dma {
pac::RCC.ahbenr().modify(|w| w.set_dmaen(Crypen::ENABLED)); pac::RCC.ahbenr().modify(|w| w.set_dmaen(true));
} }
pac::DBGMCU.cr().modify(|w| { pac::DBGMCU.cr().modify(|w| {
@ -285,14 +283,14 @@ impl<'d> Rcc<'d> {
rcc.apb2rstr().modify(|w| w.set_syscfgrst(false)); rcc.apb2rstr().modify(|w| w.set_syscfgrst(false));
// Enable SYSCFG peripheral // Enable SYSCFG peripheral
rcc.apb2enr().modify(|w| w.set_syscfgen(Dbgen::ENABLED)); rcc.apb2enr().modify(|w| w.set_syscfgen(true));
// Reset CRS peripheral // Reset CRS peripheral
rcc.apb1rstr().modify(|w| w.set_crsrst(true)); rcc.apb1rstr().modify(|w| w.set_crsrst(true));
rcc.apb1rstr().modify(|w| w.set_crsrst(false)); rcc.apb1rstr().modify(|w| w.set_crsrst(false));
// Enable CRS peripheral // Enable CRS peripheral
rcc.apb1enr().modify(|w| w.set_crsen(Lptimen::ENABLED)); rcc.apb1enr().modify(|w| w.set_crsen(true));
// Initialize CRS // Initialize CRS
let crs = pac::CRS; let crs = pac::CRS;
@ -369,7 +367,7 @@ impl RccExt for RCC {
// Enable MSI // Enable MSI
unsafe { unsafe {
rcc.cr().write(|w| w.set_msion(Pllon::ENABLED)); rcc.cr().write(|w| w.set_msion(true));
while !rcc.cr().read().msirdy() {} while !rcc.cr().read().msirdy() {}
} }
@ -379,7 +377,7 @@ impl RccExt for RCC {
ClockSrc::HSI16 => { ClockSrc::HSI16 => {
// Enable HSI16 // Enable HSI16
unsafe { unsafe {
rcc.cr().write(|w| w.set_hsi16on(Pllon::ENABLED)); rcc.cr().write(|w| w.set_hsi16on(true));
while !rcc.cr().read().hsi16rdyf() {} while !rcc.cr().read().hsi16rdyf() {}
} }
@ -388,7 +386,7 @@ impl RccExt for RCC {
ClockSrc::HSE(freq) => { ClockSrc::HSE(freq) => {
// Enable HSE // Enable HSE
unsafe { unsafe {
rcc.cr().write(|w| w.set_hseon(Pllon::ENABLED)); rcc.cr().write(|w| w.set_hseon(true));
while !rcc.cr().read().hserdy() {} while !rcc.cr().read().hserdy() {}
} }
@ -399,7 +397,7 @@ impl RccExt for RCC {
PLLSource::HSE(freq) => { PLLSource::HSE(freq) => {
// Enable HSE // Enable HSE
unsafe { unsafe {
rcc.cr().write(|w| w.set_hseon(Pllon::ENABLED)); rcc.cr().write(|w| w.set_hseon(true));
while !rcc.cr().read().hserdy() {} while !rcc.cr().read().hserdy() {}
} }
freq.0 freq.0
@ -407,7 +405,7 @@ impl RccExt for RCC {
PLLSource::HSI16 => { PLLSource::HSI16 => {
// Enable HSI // Enable HSI
unsafe { unsafe {
rcc.cr().write(|w| w.set_hsi16on(Pllon::ENABLED)); rcc.cr().write(|w| w.set_hsi16on(true));
while !rcc.cr().read().hsi16rdyf() {} while !rcc.cr().read().hsi16rdyf() {}
} }
HSI_FREQ HSI_FREQ
@ -416,7 +414,7 @@ impl RccExt for RCC {
// Disable PLL // Disable PLL
unsafe { unsafe {
rcc.cr().modify(|w| w.set_pllon(Pllon::DISABLED)); rcc.cr().modify(|w| w.set_pllon(false));
while rcc.cr().read().pllrdy() {} while rcc.cr().read().pllrdy() {}
} }
@ -447,7 +445,7 @@ impl RccExt for RCC {
}); });
// Enable PLL // Enable PLL
rcc.cr().modify(|w| w.set_pllon(Pllon::ENABLED)); rcc.cr().modify(|w| w.set_pllon(true));
while !rcc.cr().read().pllrdy() {} while !rcc.cr().read().pllrdy() {}
} }
@ -526,14 +524,13 @@ pub struct LSE(());
pub unsafe fn init(config: Config) { pub unsafe fn init(config: Config) {
let rcc = pac::RCC; let rcc = pac::RCC;
let enabled = Iophen::ENABLED;
rcc.iopenr().write(|w| { rcc.iopenr().write(|w| {
w.set_iopaen(enabled); w.set_iopaen(true);
w.set_iopben(enabled); w.set_iopben(true);
w.set_iopcen(enabled); w.set_iopcen(true);
w.set_iopden(enabled); w.set_iopden(true);
w.set_iopeen(enabled); w.set_iopeen(true);
w.set_iophen(enabled); w.set_iophen(true);
}); });
let r = <peripherals::RCC as embassy::util::Steal>::steal(); let r = <peripherals::RCC as embassy::util::Steal>::steal();