Add DMA read + write functions
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a7d6bc7ba5
commit
1d49b3444f
2 changed files with 42 additions and 10 deletions
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@ -5,26 +5,45 @@ use core::task::{Context, Poll, Waker};
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use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
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use embassy_util::waitqueue::AtomicWaker;
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use futures::Future;
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use pac::dma::vals::DataSize;
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use crate::pac::dma::vals;
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use crate::{pac, peripherals};
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pub fn copy<'a, C: Channel, W: Word>(ch: impl Peripheral<P = C> + 'a, from: &[W], to: &mut [W]) -> Transfer<'a, C> {
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assert!(from.len() == to.len());
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pub(crate) fn read<'a, C: Channel, W: Word>(ch: impl Peripheral<P = C> + 'a, from: *const W, to: *mut [W]) -> Transfer<'a, C> {
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let (ptr, len) = crate::dma::slice_ptr_parts_mut(to);
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copy(ch, from as *const u32, ptr as *mut u32, len, W::size())
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}
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pub(crate) fn write<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const [W],
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to: *mut W,
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) -> Transfer<'a, C> {
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let (from_ptr, len) = crate::dma::slice_ptr_parts(from);
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copy(ch, from_ptr as *const u32, to as *mut u32, len, W::size())
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}
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fn copy<'a, C: Channel>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const u32,
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to: *mut u32,
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len: usize,
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data_size: DataSize,
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) -> Transfer<'a, C> {
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into_ref!(ch);
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unsafe {
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let p = ch.regs();
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p.read_addr().write_value(from.as_ptr() as u32);
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p.write_addr().write_value(to.as_mut_ptr() as u32);
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p.trans_count().write_value(from.len() as u32);
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p.read_addr().write_value(from as u32);
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p.write_addr().write_value(to as u32);
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p.trans_count().write_value(len as u32);
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compiler_fence(Ordering::SeqCst);
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p.ctrl_trig().write(|w| {
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w.set_data_size(W::size());
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w.set_data_size(data_size);
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w.set_incr_read(true);
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w.set_incr_write(true);
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w.set_chain_to(ch.number());
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@ -60,7 +79,7 @@ impl<'a, C: Channel> Drop for Transfer<'a, C> {
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impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
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impl<'a, C: Channel> Future for Transfer<'a, C> {
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type Output = ();
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fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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self.channel.set_waker(cx.waker());
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if self.channel.is_running() {
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@ -110,13 +129,15 @@ pub trait Channel: Peripheral<P = Self> + sealed::Channel + Into<AnyChannel> + S
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}
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fn is_running(&self) -> bool {
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self.regs().ctrl_trig().read().en()
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unsafe { self.regs().ctrl_trig().read().en() }
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}
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fn set_waker(&self, waker: &Waker) {
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STATE.channels[self.number() as usize].waker.register(waker);
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}
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fn on_irq() {}
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fn degrade(self) -> AnyChannel {
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AnyChannel { number: self.number() }
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}
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@ -177,6 +198,17 @@ macro_rules! channel {
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};
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}
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// TODO: replace transmutes with core::ptr::metadata once it's stable
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#[allow(unused)]
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pub(crate) fn slice_ptr_parts<T>(slice: *const [T]) -> (usize, usize) {
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unsafe { core::mem::transmute(slice) }
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}
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#[allow(unused)]
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pub(crate) fn slice_ptr_parts_mut<T>(slice: *mut [T]) -> (usize, usize) {
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unsafe { core::mem::transmute(slice) }
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}
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channel!(DMA_CH0, 0);
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channel!(DMA_CH1, 1);
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channel!(DMA_CH2, 2);
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@ -128,7 +128,7 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
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}
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::copy(ch, buffer, unsafe { T::regs().uartdr().ptr() });
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let transfer = crate::dma::write(ch, buffer, T::regs().uartdr().ptr() as *mut _);
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transfer.await;
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}
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Ok(())
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@ -178,7 +178,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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}
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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let transfer = crate::dma::copy(ch, unsafe { T::regs().uartdr().ptr() }, buffer);
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let transfer = crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, buffer);
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transfer.await;
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}
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Ok(())
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