Merge pull request #2244 from embassy-rs/rm-xtensa
executor: remove arch-xtensa.
This commit is contained in:
commit
1dc31c4627
4 changed files with 5 additions and 93 deletions
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@ -5,6 +5,10 @@ All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
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The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
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and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
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and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
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## Unreleased
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- Removed `arch-xtensa`. Use the executor provided by the HAL crate (`esp-hal`, `esp32s3-hal`, etc...) instead.
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## 0.3.3 - 2023-11-15
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## 0.3.3 - 2023-11-15
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- Add `main` macro reexport for Xtensa arch.
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- Add `main` macro reexport for Xtensa arch.
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@ -57,7 +57,6 @@ critical-section = { version = "1.1", features = ["std"] }
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_arch = [] # some arch was picked
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_arch = [] # some arch was picked
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arch-std = ["_arch", "critical-section/std"]
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arch-std = ["_arch", "critical-section/std"]
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arch-cortex-m = ["_arch", "dep:cortex-m"]
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arch-cortex-m = ["_arch", "dep:cortex-m"]
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arch-xtensa = ["_arch"]
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arch-riscv32 = ["_arch", "dep:portable-atomic"]
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arch-riscv32 = ["_arch", "dep:portable-atomic"]
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arch-wasm = ["_arch", "dep:wasm-bindgen", "dep:js-sys"]
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arch-wasm = ["_arch", "dep:wasm-bindgen", "dep:js-sys"]
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@ -1,89 +0,0 @@
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#[cfg(feature = "executor-interrupt")]
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compile_error!("`executor-interrupt` is not supported with `arch-xtensa`.");
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#[cfg(feature = "executor-thread")]
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pub use thread::*;
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#[cfg(feature = "executor-thread")]
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mod thread {
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use core::marker::PhantomData;
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use core::sync::atomic::{AtomicBool, Ordering};
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pub use embassy_macros::main_riscv as main;
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use crate::{raw, Spawner};
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/// global atomic used to keep track of whether there is work to do since sev() is not available on Xtensa
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static SIGNAL_WORK_THREAD_MODE: AtomicBool = AtomicBool::new(false);
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#[export_name = "__pender"]
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fn __pender(_context: *mut ()) {
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SIGNAL_WORK_THREAD_MODE.store(true, Ordering::SeqCst);
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}
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/// Xtensa Executor
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pub struct Executor {
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inner: raw::Executor,
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not_send: PhantomData<*mut ()>,
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}
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impl Executor {
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/// Create a new Executor.
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pub fn new() -> Self {
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Self {
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inner: raw::Executor::new(core::ptr::null_mut()),
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not_send: PhantomData,
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}
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}
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/// Run the executor.
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///
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/// The `init` closure is called with a [`Spawner`] that spawns tasks on
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/// this executor. Use it to spawn the initial task(s). After `init` returns,
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/// the executor starts running the tasks.
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///
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/// To spawn more tasks later, you may keep copies of the [`Spawner`] (it is `Copy`),
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/// for example by passing it as an argument to the initial tasks.
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///
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/// This function requires `&'static mut self`. This means you have to store the
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/// Executor instance in a place where it'll live forever and grants you mutable
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/// access. There's a few ways to do this:
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///
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/// - a [StaticCell](https://docs.rs/static_cell/latest/static_cell/) (safe)
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/// - a `static mut` (unsafe)
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/// - a local variable in a function you know never returns (like `fn main() -> !`), upgrading its lifetime with `transmute`. (unsafe)
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///
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/// This function never returns.
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pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
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init(self.inner.spawner());
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loop {
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unsafe {
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self.inner.poll();
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// Manual critical section implementation that only masks interrupts handlers.
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// We must not acquire the cross-core on dual-core systems because that would
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// prevent the other core from doing useful work while this core is sleeping.
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let token: critical_section::RawRestoreState;
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core::arch::asm!("rsil {0}, 5", out(reg) token);
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// we do not care about race conditions between the load and store operations, interrupts
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// will only set this value to true.
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// if there is work to do, loop back to polling
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if SIGNAL_WORK_THREAD_MODE.load(Ordering::SeqCst) {
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SIGNAL_WORK_THREAD_MODE.store(false, Ordering::SeqCst);
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core::arch::asm!(
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"wsr.ps {0}",
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"rsync", in(reg) token)
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} else {
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// waiti sets the PS.INTLEVEL when slipping into sleep
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// because critical sections in Xtensa are implemented via increasing
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// PS.INTLEVEL the critical section ends here
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// take care not add code after `waiti` if it needs to be inside the CS
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core::arch::asm!("waiti 0"); // critical section ends here
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}
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}
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}
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}
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}
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}
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@ -1,5 +1,4 @@
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#![cfg_attr(not(any(feature = "arch-std", feature = "arch-wasm")), no_std)]
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#![cfg_attr(not(any(feature = "arch-std", feature = "arch-wasm")), no_std)]
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#![cfg_attr(feature = "arch-xtensa", feature(asm_experimental_arch))]
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#![allow(clippy::new_without_default)]
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#![allow(clippy::new_without_default)]
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#![doc = include_str!("../README.md")]
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#![doc = include_str!("../README.md")]
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#![warn(missing_docs)]
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#![warn(missing_docs)]
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@ -21,12 +20,11 @@ macro_rules! check_at_most_one {
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check_at_most_one!(@amo [$($f)*] [$($f)*] []);
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check_at_most_one!(@amo [$($f)*] [$($f)*] []);
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};
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};
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}
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}
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check_at_most_one!("arch-cortex-m", "arch-riscv32", "arch-xtensa", "arch-std", "arch-wasm",);
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check_at_most_one!("arch-cortex-m", "arch-riscv32", "arch-std", "arch-wasm",);
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#[cfg(feature = "_arch")]
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#[cfg(feature = "_arch")]
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#[cfg_attr(feature = "arch-cortex-m", path = "arch/cortex_m.rs")]
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#[cfg_attr(feature = "arch-cortex-m", path = "arch/cortex_m.rs")]
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#[cfg_attr(feature = "arch-riscv32", path = "arch/riscv32.rs")]
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#[cfg_attr(feature = "arch-riscv32", path = "arch/riscv32.rs")]
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#[cfg_attr(feature = "arch-xtensa", path = "arch/xtensa.rs")]
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#[cfg_attr(feature = "arch-std", path = "arch/std.rs")]
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#[cfg_attr(feature = "arch-std", path = "arch/std.rs")]
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#[cfg_attr(feature = "arch-wasm", path = "arch/wasm.rs")]
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#[cfg_attr(feature = "arch-wasm", path = "arch/wasm.rs")]
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mod arch;
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mod arch;
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