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Make changes to Write as well as Transfer

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This commit is contained in:
Richard Dodd 2021-05-05 19:18:57 +01:00
parent 9de12a0a7a
commit 212e83aa22
1 changed files with 4 additions and 8 deletions
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12
embassy-nrf/src/spim.rs
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@ -280,7 +280,6 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spim<'d, T> {
compiler_fence(Ordering::SeqCst);
let r = T::regs();
let s = T::state();
// Set up the DMA write.
r.txd
@ -298,23 +297,20 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spim<'d, T> {
.maxcnt
.write(|w| unsafe { w.maxcnt().bits(recv.len() as _) });
// Reset and enable the event
// Disable the end event since we are busy-polling.
r.events_end.reset();
r.intenset.write(|w| w.end().set());
// Start SPI transaction.
r.tasks_start.write(|w| unsafe { w.bits(1) });
// Wait for 'end' event.
while r.events_end.read().bits() == 0 {}
// Conservative compiler fence to prevent optimizations that do not
// take in to account actions by DMA. The fence has been placed here,
// after all possible DMA actions have completed.
compiler_fence(Ordering::SeqCst);
// Wait for 'end' event.
while r.events_end.read().bits() == 0 {
continue;
}
Ok(())
}
}